JPH04109629A - High breakdown-strength mos transistor - Google Patents

Abstract

PURPOSE:To lower the drain breakdown strength of a high breakdown-strength MOS transistor, and to improve drivability by forming a deep channel doping region elevating substrate concentration and a shallow channel doping region compensating the channel doping of the deep channel doping region. CONSTITUTION:A first conductivity type first channel region 2 reducing a first conductivity type resistor formed on the surface of a first conductivity type semiconductor substrate 1 and composed of a first impurity and a second impurity increasing the first conductivity type resistor and a first conductivity type second channel region 2' consisting of the first impurity shaped under the first channel region are provided. A gate insulating film 3 formed onto the semiconductor substrate 1, a gate electrode 4 shaped onto the gate insulating film 3, and second conductivity type source-drain regions 6, 7 are formed. The channel doping of different depth is conducted twice at that time, substrate concentration is increased by deep channel doping, and concentration is lowered by shallow channel doping. Accordingly, a high breakdown-strength MOS transistor having strong punch-through resistance, high surface breakdown and also drivability can be acquired.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a MOS transistor with a high drain breakdown voltage among MOS transistors used in LSIs and ICs.

[Summary of the invention]

The present invention relates to a high-voltage MO3) transistor that uses deep channel doping to increase the substrate concentration to increase bunch-through resistance, and shallow channel doping to lower the substrate concentration to increase the surface breakdown voltage and driveability. .

[Conventional technology]

The conventional technology will be explained using FIGS. 3 and 4. FIG. 3 shows a conventional LDDMO3 transistor, in which a substrate 1 has a channel doped region 2, a gate oxide Wa3, a gate pole 4, an LDD section, and a source/drain 6.7. FIG. 4 shows a MOS transistor having a high withstand voltage of 50 .ANG. or more, in which the LDD portion consists of a field' dope below the LOCO 3, and the source and drain are surrounded by a well 8.

[Problem to be solved by the invention]

However, when the channel doped region 2 is located near the surface, the electric field at the drain end at the surface is strong and surface breakdown is likely to occur. In addition, since the concentration is low in the deeper part of the channel, the depletion layer tends to extend from the drain and has low punch-through resistance.

[Means to solve the problem]

Therefore, channel doping was performed twice at different depths, with the deep channel doping increasing the substrate concentration and the shallow channel doping decreasing the concentration.

[Effect]

By taking the above measures, a high voltage MO3I-transistor with strong punch-through resistance, high surface breakdown, and high drivability can be obtained.

〔Example〕

A first embodiment of the present invention will be described with reference to FIG. FIG. 1 shows an LDD type MOS transistor. A gate oxide W13 and a gate electrode 4 are provided on a P-type Si substrate 1, and there are an LDD 5 and a source/drain 6.7. The channel doped layer has a dual structure of a deep layer 2 of only boron and a shallow layer 2 of boron and arsenic.Boron is ion-implanted at an energy of 50 to 200 Kel/, and arsenic is implanted at an energy of 100 KeV or less. .

Because arsenic has a large atomic radius, it has a short range and does not diffuse during post-implantation heat treatment, making it possible to form a very shallow layer.

The dark voltage of the transistor is controlled by the doses of both. When the LDD phosphorus dose is 5X10"/-Toshita, Vt++ = 0.7V, and the gate oxide film is 250 people, the surface breakdown is 1O-15V, but the same VtK
When the present invention is used, a withstand voltage of 20 V or more can be obtained, and drivability can also be improved.

FIG. 2 shows a second embodiment according to the invention. The structure is similar to that of the first embodiment, but the LDD is made of phosphorus field doped under the LOCO 8, and an N well 8 is provided under the source/drain.

Punch-through and surface breakdown vary depending on field dope, L length, etc., but VT)I=1. OV, 1x
A breakdown voltage of 40 to 50 V can be obtained by single channel doping with field doping of lQ13/d. On the other hand, in the second embodiment, which has a dual structure of a deep channel doped layer 2 made of only boron and a shallow layer 2 made of boron and arsenic, the same vyN
A breakdown voltage of 60 to 70V can be obtained.

Although the first and second embodiments have been explained using N-channel MO3) transistors, it is also possible to make a high-voltage P-channel MOS transistor with a single channel dope of phosphorus and BF2.

〔Effect of the invention〕

As described above, by providing a deep channel doped region that increases the substrate concentration and a shallow channel doped region that compensates for this channel doping, the drain breakdown voltage of the high voltage MO3) transistor is increased and the drivability is improved. can be done.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of an LDD high-voltage MO3 transistor according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view of a high-voltage MOS transistor according to a second embodiment of the present invention, and FIG. 3 is a cross-sectional view of an LDD MO3 transistor according to a prior art. )A cross-sectional view of a transistor. FIG. 4 is a cross-sectional view of a high voltage MOS transistor according to the prior art.・・Semiconductor substrate 2゛・・・Channel doped region・・Gate oxide film・・Gate electrode・・LDD ・・Source・Drain・・Well and above Applicant: Seiko Electronics Co., Ltd. Agent Patent attorney: Keinosuke Hayashi

Claims (1)

[Claims] The first impurity of the first conductivity type, which is provided on the surface of the semiconductor substrate of the first conductivity type, and includes a first impurity that lowers the resistance of the first conductivity type and a second impurity that increases the resistance of the first conductivity type. a second channel region of the first conductivity type made of the first impurity provided under the first channel region, a gate insulating film provided on the semiconductor substrate, and the gate insulating film. A high voltage MOS transistor comprising a gate electrode provided above, and source/drain regions of the second conductivity type adjacent to the first channel region and the second channel region.