US4966859A - Voltage-stable sub-μm MOS transistor for VLSI circuits - Google Patents

Voltage-stable sub-μm MOS transistor for VLSI circuits Download PDF

Info

Publication number
US4966859A
US4966859A US07/293,567 US29356789A US4966859A US 4966859 A US4966859 A US 4966859A US 29356789 A US29356789 A US 29356789A US 4966859 A US4966859 A US 4966859A
Authority
US
United States
Prior art keywords
conductivity type
source
implantation
substrate
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US07/293,567
Inventor
Lothar Risch
Reinhard Tielert
Wolfgang Mueller
Christoph Werner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Application granted granted Critical
Publication of US4966859A publication Critical patent/US4966859A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/105—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with vertical doping variation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/126—Power FETs

Definitions

  • This invention relates to a voltage-stable MOS transistor for VLSI circuits having a semiconductor substrate of a first conductivity type and a planarly disposed epitaxial layer thereon, with an overlying insulating layer and, on the latter, a gate electrode consisting of polysilicon. Highly doped source and drain zones of the second conductivity type are generated, extending into the surface area, and a zone of the first conductivity type functioning as a channel zone is disposed between the source and drain zones, exhibiting a different concentration of implanted doping substance in the direction toward the substrate.
  • the invention also relates to a method for manufacturing the aforesaid MOS transistor.
  • transistors having channel lengths less than 1.5 ⁇ m are required which operate with the standard voltage of 5 volts (-2.5 volts substrate voltage).
  • the poor reproducibility of the threshold voltage represents a difficult technical problem. This is because of fluctuations in channel length or insufficient voltage stability as the result of avalanche multiplication, especially when coupled with a bipolar effect.
  • An object of the present invention is to provide a MOS transistor for VLSI circuits (sub- ⁇ m range) which exploits the advantages of a deep implantation with high dose on the short channel effect of the threshold voltage and thereby avoids the breakdown of the transistor at relatively low drain voltages
  • a further object of the present invention is to provide a method for manufacturing the aforesaid MOS transistor, which is as simple as possible to execute.
  • the substrate of the first conductivity type is lowresistant material and the epitaxial layer is high-resistant material and of the same conductivity type as the substrate;
  • the epitaxial layer exhibits a layer thickness which maximally amounts to ten times the depth of the source/drain zones, but which amounts at least to twice the depth of the concentration maximum of the doping substance particles implanted in the channel zone;
  • the channel region of the first conductivity type exhibits an increasing doping concentration in the direction of the substrate, whereby the concentration maximum of the implanted doping substance of the first conductivity type in the channel region of the first conductivity type extends to behind the source/drain zone of the second conductivity type, such that the region with the concentration maximum of the implanted doping substance surrounds the edge of the source/drain zone in the region of the gate electrode.
  • the short channel effect on the threshold voltage is greatly reduced, due to the influence of the deep implantation. It has been discovered during investigations of the breakdown behavior that, at the beginning of the avalanche multiplication of the channel current, the hole current flowing off to the substrate effects a voltage drop. This voltage drop leads to an internal bias voltage of the MOS transistor which increases the channel current. Given further increase of the substrate current, the bipolar effect then occurs. Accordingly, the substrate assumes the role of a base of a bipolar transistor, so that an additional current which leads to breakdown of the MOS transistor is now injected over the layer sequence now corresponding to emitter, base, and collector.
  • the transistor of the present invention suppresses this voltage drop, generated by the avalanche multiplication current, because the MOS structure is constructed on a low-resistance substrate and a thin, high-resistant epitaxial layer is situated thereon.
  • the internal bias voltage and bipolar effect are largely eliminated and, thus, a higher drain voltage of the MOS transistor is achieved.
  • the overlap of the channel doping with the source/drain implantation is reduced using an additional implantation for the channel implantation before source/drain implantation and thus the circuit speed of the transistor is increased. In this way, epitaxial layer assumes the realization of the low-doped zone.
  • FIGS. 1 through 4 show cross-sectional views of a transistor constructed in accordance with the invention, at several successive stages of manufacture.
  • FIGS. 5 and 6 show sections through characteristic transistor regions and the concentration curve along section lines V--V', and VI--VI' in FIG. 4.
  • a highly doped silicon substrate body 1 (p ++ ⁇ 10 17 cm -3 ), which is ⁇ 500 ⁇ m thick, has a lower doped epitaxial silicon layer 2 (p - ⁇ 1 ⁇ 10 15 cm -3 ), such layer having been precipitated on its surface from the gaseous phase with a layer thickness of 2 ⁇ m.
  • an intermediate layer 3 is formed between the substrate 1 and the layer 2, as a result of diffusion from the substrate 1.
  • An insulation layer 4 consisting of SiO 2 with a layer thickness of less than 30 nm is grown on the substrate (1, 2, 3) coated in that manner, said insulation layer 4 being later employed in specific regions of the circuit as gate oxide.
  • an implantation mask 5, consisting of photosensitive resist is applied to the substrate (1, 2, 3) provided with the SiO 2 layer 4, in such manner that the gate regions remain free for functioning later in the transistor.
  • a double implantation of the channel region with doping substance particles consisting of boron ions 6 is then executed (FIG. 3), whereby the deep implantation (see region 7) simultaneously generates the field implantation.
  • the improvement of the short channel effect on the threshold voltage and the improvement of the differential threshold behavior is then achieved by means of the plateau-like doping profile of the regions 7 and 8 which is produced by the double implantation 6.
  • the region 7 having the high doping serves to shield the potential at the source at the surface and in the volume (SDIBL, VDIBL) from the drain voltage.
  • Typical implantation parameters for the deep implantation are 1 through 3 ⁇ 10 12 B cm -2 at 140 keV.
  • the threshold voltage of the transistor is set in the region 8 with the flat boron implantation and the lower dose.
  • Typical implantation values are 2 through 6 ⁇ 10 11 B cm -2 at 25 keV.
  • the resist mask 5 is removed and the polysilicon gate material and electrode material are applied in a known manner, and the gate electrode 9 is structured (FIG. 4).
  • the gate electrode 9 is structured (FIG. 4).
  • the source/drain regions 10 are then generated in a known manner by means of an arsenic implantation, whereby a range from 0.3 through 0.4 ⁇ m is set for the depth of these regions. As shown in FIG.
  • FIG. 4 shows the inventive transistor structure provided with the source/drain and gate terminals, S, D and G, respectively.
  • FIG. 5 shows the concentration curve N A (cm -3 ) along the section line V--V' in FIG. 4 (the channel region); and FIG. 6 shows the concentration curve N A ,D cm -3 ) along the section line VI--VI' in FIG. 4 (the source/drain region).
  • the individual doping regions (1, 2, 3, 7, 8 and 10) are indicated in FIGS. 5 and 6.
  • N A and N D denote acceptor and donor concentrations respectively.
  • the n+ substrate capacitance is reduced by the low-doped epitaxial region 2, given simultaneous increase of the breakdown voltage of the pn junction.
  • the broken line in FIG. 6 indicates the position of the pn junction.
  • the non-self-adjusting implantation mask for the channel region can be reliably adjusted with an overlap of 0.5-1.0 ⁇ m, using the current state of the art.
  • the internal bias voltage of the transistor, and the turn on of the parasitic bipolar transistor, are prevented by the low-resistant regions 1 and 3. Due to the drop of the doping concentration between the maximum of 11 of the implantation and the substrate 1, the substrate body effect is reduced at high substrate voltages so that the transistor can also be employed as a transfer gate.
  • the tail of the doping substance concentration 7 should therefore overlap with the tail of the substrate doping 3 in order to avoid punch-through effects.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A voltage-stable sub-μm-MOS transistor for VLSI circuits consist of a low-resistant silicon substrate of a first conductivity type with a high-resistant, thin, epitaxial layer of the first conductivity type situated thereon and on which a gate electrode consisting of polysilicon is disposed. Highly doped source/drain zones of the second conductivity type form a channel region of the first conductivity type. A doping substance concentration, rising in the direction of the substrate, is generated by means of double implantation, whereby the concentration maximum extends to behind the source/drain zones. A method for manufacturing same incorporates steps of forming the several layers, applying a mask, executing a double implantation in the channel region, and forming the gate electrode.

Description

This is a division, of U.S. patent application Ser. No. 462,401, filed Jan. 31, 1983, now abandoned.
FIELD OF THE INVENTION
This invention relates to a voltage-stable MOS transistor for VLSI circuits having a semiconductor substrate of a first conductivity type and a planarly disposed epitaxial layer thereon, with an overlying insulating layer and, on the latter, a gate electrode consisting of polysilicon. Highly doped source and drain zones of the second conductivity type are generated, extending into the surface area, and a zone of the first conductivity type functioning as a channel zone is disposed between the source and drain zones, exhibiting a different concentration of implanted doping substance in the direction toward the substrate. The invention also relates to a method for manufacturing the aforesaid MOS transistor.
BACKGROUND The Prior Art
Due to continuing miniaturization of integrated MOS circuits, transistors having channel lengths less than 1.5 μm are required which operate with the standard voltage of 5 volts (-2.5 volts substrate voltage). The poor reproducibility of the threshold voltage represents a difficult technical problem. This is because of fluctuations in channel length or insufficient voltage stability as the result of avalanche multiplication, especially when coupled with a bipolar effect.
It is known from the prior art, for example the article by R. H. Dennard et al "Design of Ion-Implanted MOSFET's With Very Small Physical Dimensions" in IEEE Solid State Circuits, Vol. SC-9, pp. 256 through 268, 1974, to resolve this problem by using a MOS transistor constructed on a high-resistant substrate which receives a double implantation in the channel region and exhibits reduced source/drain penetration depths as well as a thin gate oxide.
The idea of double implantation in the channel region, for example, in a publication by P. P. Wang, in the IEEE, ED-24 (1977), pp. 196 through 204, is not fully exploited in practice. Specifically, a far smaller dose is selected for the deep implantation than would be optimum for shielding the drain voltage from the source, so as not to reduce the turnover voltage stability of the transistor.
Other ideas, such as double-implanted MOS structures, double-diffused MOS structures, MOS structures with buried zones, MOS structures with separate gates and weakly doped drain zones are likewise known for resolving the problem, but involve greater complexity and poorer reproducibility of the long channel threshold voltage as disadvantages.
BRIEF DESCRIPTION OF THE INVENTION
An object of the present invention is to provide a MOS transistor for VLSI circuits (sub-μm range) which exploits the advantages of a deep implantation with high dose on the short channel effect of the threshold voltage and thereby avoids the breakdown of the transistor at relatively low drain voltages
A further object of the present invention is to provide a method for manufacturing the aforesaid MOS transistor, which is as simple as possible to execute.
These objects are achieved by a transistor of the initially specified type which is characterized by having the following features:
(a) the substrate of the first conductivity type is lowresistant material and the epitaxial layer is high-resistant material and of the same conductivity type as the substrate;
(b) the epitaxial layer exhibits a layer thickness which maximally amounts to ten times the depth of the source/drain zones, but which amounts at least to twice the depth of the concentration maximum of the doping substance particles implanted in the channel zone; and
(c) the channel region of the first conductivity type exhibits an increasing doping concentration in the direction of the substrate, whereby the concentration maximum of the implanted doping substance of the first conductivity type in the channel region of the first conductivity type extends to behind the source/drain zone of the second conductivity type, such that the region with the concentration maximum of the implanted doping substance surrounds the edge of the source/drain zone in the region of the gate electrode.
Further embodiments and further developments of the invention will be apparent from the following description and the accompanying drawings.
The following considerations have led to the invention; the short channel effect on the threshold voltage is greatly reduced, due to the influence of the deep implantation. It has been discovered during investigations of the breakdown behavior that, at the beginning of the avalanche multiplication of the channel current, the hole current flowing off to the substrate effects a voltage drop. This voltage drop leads to an internal bias voltage of the MOS transistor which increases the channel current. Given further increase of the substrate current, the bipolar effect then occurs. Accordingly, the substrate assumes the role of a base of a bipolar transistor, so that an additional current which leads to breakdown of the MOS transistor is now injected over the layer sequence now corresponding to emitter, base, and collector.
The transistor of the present invention suppresses this voltage drop, generated by the avalanche multiplication current, because the MOS structure is constructed on a low-resistance substrate and a thin, high-resistant epitaxial layer is situated thereon. Thus, the internal bias voltage and bipolar effect are largely eliminated and, thus, a higher drain voltage of the MOS transistor is achieved. Moreover, the overlap of the channel doping with the source/drain implantation is reduced using an additional implantation for the channel implantation before source/drain implantation and thus the circuit speed of the transistor is increased. In this way, epitaxial layer assumes the realization of the low-doped zone.
BRIEF DESCRIPTION OF THE DRAWINGS
Reference will now be made to the accompanying drawings, in which:
FIGS. 1 through 4 show cross-sectional views of a transistor constructed in accordance with the invention, at several successive stages of manufacture.
FIGS. 5 and 6 show sections through characteristic transistor regions and the concentration curve along section lines V--V', and VI--VI' in FIG. 4.
For purposes of greater clarity, illustrations of adjacent regions of the transistor such as, for example, the insulation regions (LOCOS regions) separating the active transistor regions, have been omitted.
DESCRIPTION OF THE PREFERRED EMBODIMENT
The manufacture of an n-channel MOS transistor is described on the basis of FIGS. 1 through 4. The same reference symbols apply to identical parts in all Figures.
As shown in FIG. 1, a highly doped silicon substrate body 1 (p++ ≈1017 cm-3), which is ≈500 μm thick, has a lower doped epitaxial silicon layer 2 (p- ≈1×10 15 cm-3), such layer having been precipitated on its surface from the gaseous phase with a layer thickness of 2 μm. During this growth, an intermediate layer 3 is formed between the substrate 1 and the layer 2, as a result of diffusion from the substrate 1. An insulation layer 4 consisting of SiO2 with a layer thickness of less than 30 nm is grown on the substrate (1, 2, 3) coated in that manner, said insulation layer 4 being later employed in specific regions of the circuit as gate oxide.
As shown in FIG. 2, an implantation mask 5, consisting of photosensitive resist is applied to the substrate (1, 2, 3) provided with the SiO2 layer 4, in such manner that the gate regions remain free for functioning later in the transistor.
With the assistance of this implantation mask 5, a double implantation of the channel region with doping substance particles consisting of boron ions 6 is then executed (FIG. 3), whereby the deep implantation (see region 7) simultaneously generates the field implantation. The improvement of the short channel effect on the threshold voltage and the improvement of the differential threshold behavior is then achieved by means of the plateau-like doping profile of the regions 7 and 8 which is produced by the double implantation 6. The region 7 having the high doping serves to shield the potential at the source at the surface and in the volume (SDIBL, VDIBL) from the drain voltage.
Typical implantation parameters for the deep implantation (region 7) are 1 through 3×1012 B cm-2 at 140 keV. The threshold voltage of the transistor is set in the region 8 with the flat boron implantation and the lower dose. Typical implantation values are 2 through 6×1011 B cm-2 at 25 keV.
After completion of the boron double implantation 6, the resist mask 5 is removed and the polysilicon gate material and electrode material are applied in a known manner, and the gate electrode 9 is structured (FIG. 4). Upon employment of the gate electrode 9 as an implantation mask, the source/drain regions 10 are then generated in a known manner by means of an arsenic implantation, whereby a range from 0.3 through 0.4 μm is set for the depth of these regions. As shown in FIG. 4, the concentration maximum of the boron implantation (i.e., the dotted line 11) is overlain by (or is located beneath) lies behind the source/drain regions 10 (in contrast to the structure disclosed on page 263 of Dennard, in which the source/drain zones extend deeper into the substrate than the deep implantation). FIG. 4 shows the inventive transistor structure provided with the source/drain and gate terminals, S, D and G, respectively.
FIG. 5 shows the concentration curve NA (cm-3) along the section line V--V' in FIG. 4 (the channel region); and FIG. 6 shows the concentration curve NA,D cm-3) along the section line VI--VI' in FIG. 4 (the source/drain region). The individual doping regions (1, 2, 3, 7, 8 and 10) are indicated in FIGS. 5 and 6. NA and ND denote acceptor and donor concentrations respectively.
The disadvantages of reversing the classical doping profile (as described, for example, in Wang and Dennard) on other transistor properties, such as n+ substrate capacitance and avalanche-induced bipolar effects, are compensated by the doping regions 1, 2, 3.
The n+ substrate capacitance is reduced by the low-doped epitaxial region 2, given simultaneous increase of the breakdown voltage of the pn junction. The broken line in FIG. 6 indicates the position of the pn junction. The non-self-adjusting implantation mask for the channel region can be reliably adjusted with an overlap of 0.5-1.0 μm, using the current state of the art.
The internal bias voltage of the transistor, and the turn on of the parasitic bipolar transistor, are prevented by the low- resistant regions 1 and 3. Due to the drop of the doping concentration between the maximum of 11 of the implantation and the substrate 1, the substrate body effect is reduced at high substrate voltages so that the transistor can also be employed as a transfer gate. The tail of the doping substance concentration 7 should therefore overlap with the tail of the substrate doping 3 in order to avoid punch-through effects.
It will be clear to those skilled in the art that various modifications or additions may be made in the present invention, which is intended to be defined and secured by the appended claims.

Claims (3)

What is claimed is:
1. A method for manufacturing a voltage-stable short-channel MOS transistor having a sub-μm channel length with the following characteristics;
(a) a semiconductor substrate of a first conductivity type and an epitaxial layer planarly disposed thereupon and an insulating layer disposed on said epitaxial layer, a gate electrode disposed on said insulating layer, said electrode consisting of polysilicon, said epitaxial layer having highly doped source and drain zones of the second conductivity type extending into its surface region, with a region of the first conductivity type functioning as a channel zone disposed between the source and drain zones, said region exhibiting a different concentration of implanted doping substance in the direction of the substrate;
(b) the substrate of the first conductivity type is formed of low-resistant material and the epitaxial layer is formed of high-resistant material and of the same conductivity type as the substrate;
(c) the epitaxial layer has a thickness which maximally amounts to ten times the depth of the source/drain zones but which at least amounts to twice the depth of the concentration maximum of the doping substance implanted in the channel zone;
(d) the channel region of the first conductivity type exhibits an increasing doping concentration in the direction of the substrate, whereby the concentration maximum of the implanted doping substance of the first conductivity type in the channel region of the first conductivity type is overlain by the source and drain zones of the second conductivity type, such that the region with the concentration maximum of the implanted doping substance shields the edges of the source and drain zones in the region of the gate electrode;
said method comprising the steps of:
(e) precipitating an epitaxial, p-doped silicon layer with a layer thickness in the range from 1.5 through 5 μm on a lower-resistant substrate consisting of p-conductive silicon;
(f) growing thereon an insulating layer for use as a gate oxide layer;
(g) applying an implantation mask consisting of photosensitive resist such that the gate region of the transistor to be produced layer remains free thereof;
(h) executing a double implantation in the channel region by means of superimposing a deep and flat boron ion implantation by means of setting different implantation energies and doses, said deep boron ion implantation being performed with a higher dose than said flat boron ion implantation;
(i) removing the implantation mask;
(j) generating and structuring the gate electrode consisting of polysilicon; and
(k) executing the source-drain implantation at the outer surface of said epitaxial layer to form said source and drain zones at a level less deep than the level of maximum concentration of said deep boron ion implantation, using the gate electrode as an implantation mask whereby the source and drain zones each overlie and overlap a part of said deep boron ion implantation.
2. The method according to claim 1, wherein the gate oxide layer thickness dox is set to less than 30 nm.
3. The method according to claim 1, wherein the dose and energy of said flat boron ion implantation are set to 2 through 6×1011 cm-2 and 25 keV, and the dose and energy of the said deep boron ion implantation are set to 1 through 3 ×1012 cm-2 and 140 keV.
US07/293,567 1982-03-09 1989-01-03 Voltage-stable sub-μm MOS transistor for VLSI circuits Expired - Lifetime US4966859A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19823208500 DE3208500A1 (en) 1982-03-09 1982-03-09 VOLTAGE-RESISTANT MOS TRANSISTOR FOR HIGHLY INTEGRATED CIRCUITS
DE3208500 1982-03-09

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US06462401 Division 1983-01-31

Publications (1)

Publication Number Publication Date
US4966859A true US4966859A (en) 1990-10-30

Family

ID=6157752

Family Applications (1)

Application Number Title Priority Date Filing Date
US07/293,567 Expired - Lifetime US4966859A (en) 1982-03-09 1989-01-03 Voltage-stable sub-μm MOS transistor for VLSI circuits

Country Status (6)

Country Link
US (1) US4966859A (en)
EP (1) EP0088399B1 (en)
JP (1) JPS58165381A (en)
AT (1) ATE35068T1 (en)
CA (1) CA1203321A (en)
DE (2) DE3208500A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5610429A (en) * 1994-05-06 1997-03-11 At&T Global Information Solutions Company Differential analog transistors constructed from digital transistors
US5683934A (en) * 1994-09-26 1997-11-04 Motorola, Inc. Enhanced mobility MOSFET device and method
USRE41764E1 (en) 1999-06-11 2010-09-28 Thomas Skotnicki Semiconductor device with compensated threshold voltage and method for making same

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59177960A (en) * 1983-03-28 1984-10-08 Hitachi Ltd Semiconductor device and manufacture thereof
JPH0770476B2 (en) * 1985-02-08 1995-07-31 株式会社東芝 Method for manufacturing semiconductor device
IT1214615B (en) * 1985-06-19 1990-01-18 Ates Componenti Elettron N-CHANNEL MOS TRANSISTOR WITH LIMITATION OF THE PERFORATION EFFECT (PUNCH-THROUGH) AND RELATED TRAINING PROCESS.
EP0434850A4 (en) * 1989-07-18 1991-10-02 Seiko Instruments Inc. Semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5380172A (en) * 1976-12-25 1978-07-15 Fujitsu Ltd Semiconductor device
JPS5384571A (en) * 1976-12-29 1978-07-26 Fujitsu Ltd Insulating gate type field effect transistor and its manufacture
JPS5632757A (en) * 1979-08-25 1981-04-02 Semiconductor Res Found Insulated gate type transistor and integrated circuit

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1153428A (en) * 1965-06-18 1969-05-29 Philips Nv Improvements in Semiconductor Devices.
JPS5389681A (en) * 1977-01-19 1978-08-07 Hitachi Ltd Mis type semiconductor device
US4225877A (en) * 1978-09-05 1980-09-30 Sprague Electric Company Integrated circuit with C-Mos logic, and a bipolar driver with polysilicon resistors
JPS55134974A (en) * 1979-04-06 1980-10-21 Nec Corp Manufacturing of semiconductor device
JPS56146276A (en) * 1980-02-29 1981-11-13 Chiyou Lsi Gijutsu Kenkyu Kumiai Insulating gate type field-effect transistor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5380172A (en) * 1976-12-25 1978-07-15 Fujitsu Ltd Semiconductor device
JPS5384571A (en) * 1976-12-29 1978-07-26 Fujitsu Ltd Insulating gate type field effect transistor and its manufacture
JPS5632757A (en) * 1979-08-25 1981-04-02 Semiconductor Res Found Insulated gate type transistor and integrated circuit

Non-Patent Citations (8)

* Cited by examiner, † Cited by third party
Title
IEEE Journal of Sol. Stat. Circuits vol. Sc 9 No. 5, Oct., 1974, pp. 256 268. *
IEEE Journal of Sol. Stat. Circuits vol. Sc-9 No. 5, Oct., 1974, pp. 256-268.
IEEE Trans. on Elecktro Devices vol. ED 24, No. 3, Mar., 1977, pp. 196 204. *
IEEE Trans. on Elecktro Devices vol. ED-24, No. 3, Mar., 1977, pp. 196-204.
Konaka et al., "Suppression of Anomalous Drain Current in Short Channel MOSFET," Jap. Jour. Applied Physics, vol. 18 (1979), Supplement 18-1, pp. 27-33.
Konaka et al., Suppression of Anomalous Drain Current in Short Channel MOSFET, Jap. Jour. Applied Physics, vol. 18 (1979), Supplement 18 1, pp. 27 33. *
Yoshida et al., "Thermal Stability and Secondary Breakdown in Planar Power MOSFET's," IEEE Trans. on Electron Devices, vol. ED-27, No. 2, 2/80, pp. 395-398.
Yoshida et al., Thermal Stability and Secondary Breakdown in Planar Power MOSFET s, IEEE Trans. on Electron Devices, vol. ED 27, No. 2, 2/80, pp. 395 398. *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5610429A (en) * 1994-05-06 1997-03-11 At&T Global Information Solutions Company Differential analog transistors constructed from digital transistors
US5683934A (en) * 1994-09-26 1997-11-04 Motorola, Inc. Enhanced mobility MOSFET device and method
USRE41764E1 (en) 1999-06-11 2010-09-28 Thomas Skotnicki Semiconductor device with compensated threshold voltage and method for making same

Also Published As

Publication number Publication date
ATE35068T1 (en) 1988-06-15
EP0088399A2 (en) 1983-09-14
DE3208500A1 (en) 1983-09-15
EP0088399B1 (en) 1988-06-08
EP0088399A3 (en) 1986-01-15
DE3377039D1 (en) 1988-07-14
JPS58165381A (en) 1983-09-30
CA1203321A (en) 1986-04-15

Similar Documents

Publication Publication Date Title
US4946799A (en) Process for making high performance silicon-on-insulator transistor with body node to source node connection
US4306916A (en) CMOS P-Well selective implant method
US4899202A (en) High performance silicon-on-insulator transistor with body node to source node connection
US5406110A (en) Resurf lateral double diffused insulated gate field effect transistor
US4965213A (en) Silicon-on-insulator transistor with body node to source node connection
US5144390A (en) Silicon-on insulator transistor with internal body node to source node connection
US5465000A (en) Threshold adjustment in vertical DMOS devices
KR950006479B1 (en) Laieral transistor
US6022778A (en) Process for the manufacturing of integrated circuits comprising low-voltage and high-voltage DMOS-technology power devices and non-volatile memory cells
US7554159B2 (en) Electrostatic discharge protection device and method of manufacturing the same
US4974051A (en) MOS transistor with improved radiation hardness
US5134447A (en) Neutral impurities to increase lifetime of operation of semiconductor devices
US5362982A (en) Insulated gate FET with a particular LDD structure
US20040043568A1 (en) Electrostatic discharge protection device and method of manufacturing the same
US5026656A (en) MOS transistor with improved radiation hardness
JPS58147074A (en) Metal oxide semiconductor transistor device and method of producing same
US5104818A (en) Preimplanted N-channel SOI mesa
EP0176409A2 (en) Cmos circuit having a reduced tendency to latch
US4966859A (en) Voltage-stable sub-μm MOS transistor for VLSI circuits
US5008719A (en) Dual layer surface gate JFET having enhanced gate-channel breakdown voltage
US5221635A (en) Method of making a field-effect transistor
JP2933796B2 (en) Method for manufacturing semiconductor device
US4728998A (en) CMOS circuit having a reduced tendency to latch
US7736961B2 (en) High voltage depletion FET employing a channel stopping implant
US5118632A (en) Dual layer surface gate JFET having enhanced gate-channel breakdown voltage

Legal Events

Date Code Title Description
STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12