JPH0410806A - Digital filter - Google Patents

Abstract

PURPOSE:To eliminate the need for employing a sophisticated ROM by eliminating a sampling clock and sampling noise by one analog filter even when the transmission speed of an input digital signal differs. CONSTITUTION:Selector circuits 9A-11A whose circuit number is equal to the number of sampling clocks are provided to a selector 1, and assuming that clocks whose clock frequencies as twice, 4 times and 8 times are inputted from sampling clock inputs 9-11, then the selector circuits 9A-11A are set to be in the passing or blocking state respectively by using a 2-bit control signal and only a required sampling clock is inputted to a low-order address of a ROM 3. Other addresses of the ROM 3 are set to an L level. The resulting signal is subject to re-timing by a latch circuit 4 and supplied to a D/A converter 5, in which the signal is converted into an analog voltage. The sampling speed of the output of the D/A converter 5 is changed with respect to the transmission speed so that the frequency band of sampling noise is selected to an attenuation band of an analog filter 6. Thus, a required spectrum is obtained by using only one analog filter.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital filter, and more particularly to a variable transmission rate digital filter used for limiting the transmission band of a digital modulation device.

[Conventional technology]

In the conventional variable transmission speed digital filter, as shown in the configuration diagram in FIG. Each bit of the serial data is sequentially delayed by 1 bit by n bits and input to the upper address of the ROM 3 as n-bit parallel data. Further, sampling clock inputs 9 to 11 of 2 to m times the data clock synchronized with the clock input 8 of the input data are input to the lower addresses of the ROM 3. With this sampling clock, RO
By reading out the filtering data written in M to the latch circuit 4, it becomes a table reference type n-tap m-times sample acyclic filter (referred to as an FIR filter). The output of this latch circuit 4 is converted into an analog signal by a D/A converter 5. Next, the output of the D/A converter 5 is selected by the selector switch 14 and passed through the analog filters 6A to 6C (U) deviation power), and only the required spectrum is extracted and the final data is obtained from the data output 13 (power). ing.

Now, for example, if the transmission speed variable type data input data clock is 64KB/s, 128KB/s, IMB/
Three types of transmission speeds are available, and the sampling clock is 8 times that of the data clock.

Suppose that three types of clocks, 16 times and 32 times (m = 32 >), are input from sample name clock inputs 9 to 12. In this case, the transmission speed is 64 KB/s, 128 KB
/s and IMB/S input data are 32 times and 16 times, respectively.
It is sampled with a sampling clock that is twice or eight times faster. Here, when two input data with transmission speeds of 64 KB/S and IMB/s are input, the multiple m is assigned in descending order of the input data, and two types of sampling, 32 times and 16 times, are assigned. sampled by clock. In other words, the normalization rate f s / f R, which is the ratio of the input data clock frequency fR to the sampling clock frequency fs, is equal to f s / f R = 8 or 16 even for the same IMB/S input data. In addition, a sampling clock of 16 KB/s, which is quite high, must be used for reading the ROM3. The role of the analog filters 6A to 6C is to extract the spectrum fR of the desired wave and to remove sampling noise generated at integral multiples of the sampling clock frequencies f5 and fs. This role will be supplementarily explained with reference to FIG. 3, which shows the relationship between the spectrum of the output of the D/A converter 5 and the band of the analog filter. As can be easily understood from this diagram, if the sampling frequency f5 of the digital filter is normalized by m times the transmission speed, then if the transmission speed changes, the required bandwidth fR to pass the spectrum of the desired wave will change. Instead, the sampling frequency f5 changes, and the frequency of sampling noise changes.

That is, as shown in the specific numerical example above, the analog filter and data clock IM when input data uses a sampling frequency fs = 64 x 32 KB/S for a data clock of 64 KB/5 (fR).
For B/S (fll), when using an analog filter with fs=IX18MB/S, unless you prepare another analog filter according to the transmission speed and change the band, sampling noise will be reduced. It becomes impossible to remove it at any transmission speed. Therefore, in the conventional example, as shown in FIG.
A method was adopted in which 6C was selected and switched using a selector switch 14 according to the transmission speed.

[Problem to be solved by the invention]

The above-mentioned conventional digital filter requires a plurality of analog filters and a selector switch to select any one of them, so it has the disadvantage that the circuit scale becomes extremely large. In addition, since the sampling clock is assigned sequentially from the highest multiple m, there is a possibility that the ROM will be read at the sampling clock frequency or a higher frequency, especially when data with a high transmission speed is input. There is a drawback that ROM must be used.

An object of the present invention is to provide a digital filter that can be realized with a single analog filter even when the data input transmission speed changes over a wide range, and that does not require the use of a high-grade ROM such as a high-speed ROM. .

[Means to solve the problem]

The digital filter of the present invention includes a shift register that inputs a plurality of digital signals having different transmission speeds and each clock of the digital signals and performs serial-to-parallel conversion, and a shift register that inputs the parallel signal to an upper address and converts the digital signal. A ROM that inputs the sampling clock to the lower address, and filtering data stored in advance in the ROM based on the information of the upper and lower addresses are read out and converted from digital to analog, and then the desired analog signal is extracted. In a digital filter that has an analog filter that removes unnecessary sampling noise, a sampling clock A with a frequency 2# (L is a natural number) times the clock frequency of the expected input digital signal is prepared and sequentially input. a selector for selecting an arbitrary sampling clock from the plurality of sampling clocks A according to a control signal corresponding to digital signals having different transmission speeds and inputting the selected sampling clock to a lower address of the ROM; is characterized in that even if the input digital signals have different transmission speeds, they are removed by one analog filter.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. The embodiment shown in FIG. 1 has a data cuff, a shift register 2. ROM3. Latch circuit 4. D/A converter 5
．． In this embodiment, the data output 13 includes sampling clock inputs 9 to 15, a selector 1, and one analog filter 6. A digital input signal, which is serial data inputted from the data register 2, is delayed by 1 to n bits by the clock input 8 in the shift register 2, and is inputted to the upper address of the ROM 3 as an n-bit parallel signal. Next, high-speed sampling clocks 9 to 11 are input to the selector 1. In this embodiment, the maximum number of samples required when the transmission speed is varied is the number of samples required when the transmission speed is set to the minimum (for example, 64K B/S), as shown in the specific numerical example above. 32 times), and this maximum number of samples is taken as the power.

Also, the multiple of the minimum sample is the limit of the attenuation characteristic at the cutoff frequency of the analog filter's low-pass filter,
It is determined from the read speed when using a normal ROM, and is generally four times the transmission speed. In the sampling clock inputs 9 to 15, a plurality of sampling clocks of 2 to L times, for example, 4.8 degrees 16.32 times (L=32) are inputted, assuming data of various transmission speeds in advance. The selector 1 is a circuit that selects an arbitrary sampling clock according to the data transmission speed of the data input 1, and performs a selection operation using a control signal 16 according to input data. Now, - as an example, input data clock 64KB/S, 128KB/S, IMB/S
, the sampling clocks are selected as 32 times, 16 times, and 4 times, respectively. Therefore, the cutoff frequency of the analog filter is 64X32=2048
KHz, 128X16=2098KHz.

IX4 = a frequency slightly lower than 4MHz (for example, IMHz
) can be realized with one analog filter set to

Also, since the sampling frequency clock of the data input IMB/S is 4MB/S, a normal ROM can be used. As shown in the circuit diagram of FIG. 2, the selector 1 includes selector circuits 9A to IIA corresponding to the number of input sample link clocks.
For example, a sampling clock input 9
Assuming that 2x, 4x, and 8x clocks are input from ~11, each selector circuit 9A-IIA is set to pass or block operation by two control signals, and only the necessary sampling clock is input to the lower address of ROM3. is input. The address of other ROM '3 is °“L
“It is fixed at a level.

This signal is retimed by a latch circuit 4 and outputted as an analog voltage by a D/A converter 5. At the output of this D/A converter 5, the sampling rate is varied in accordance with the transmission rate so that the frequency band of the sampling noise falls within the attenuation range of the analog filter, so the output of the analog filter 6 is the input transmission rate. Even if you change the spectrum, it is always possible to obtain the desired spectrum with one analog filter.

〔Effect of the invention〕

As explained above, the present invention includes a selector that inputs a plurality of sampling clocks corresponding to data inputs having different transmission speeds and selects an arbitrary sampling clock based on an external control signal, and one analog By having a filter, it is possible to provide a digital filter with a simple circuit configuration that does not require a plurality of conventional analog filters and selector switches for these analog filters. Further, by employing the above-mentioned selector, there is an effect that a ROM having a normal read speed can be used as the ROM used for this digital filter.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention, FIG. 2 is a circuit diagram of the selector 1 in FIG. 1, FIG. 3 is an explanatory diagram for removing a general sampling signal and sampling noise, and FIG. FIG. 2 is a configuration diagram of a conventional digital filter. 1...Selector, 2...Shift register, 3...
ROM, 4... latch circuit, 5... D/A converter,
6.6A-6C...Analog filter, 7...Data input, 8...Data clock input, 9-1.1.
15...Sampling clock input, 13...Data output, 16...Control signal input.

Claims (1)

[Scope of Claims] 1. A shift register that inputs a plurality of digital signals having different transmission speeds and each clock of the digital signals and performs serial-to-parallel conversion; A ROM that inputs a sampling clock for sampling each of In a digital filter that has an analog filter that removes unnecessary sampling noise, a sampling clock A with a frequency 2l (l is a natural number) times the clock frequency of an expected input digital signal is prepared, and the transmission rate that is sequentially input is a selector for selecting an arbitrary sampling clock from the plurality of sampling clocks A and inputting it to a lower address of the ROM according to a control signal corresponding to a different digital signal; A digital filter characterized in that even if the transmission speeds of the signals are different, they can be removed by one analog filter. 2. The upper and lower limit values of the 2l times correspond to the lowest and highest transmission rate sampling clocks of the input digital signal, respectively, and the upper and lower limit values of the 2l times correspond to the high frequency cutoff characteristics of the analog filter. 2. The digital filter according to claim 1, wherein the digital filter is determined in accordance with a cutoff frequency of the digital filter.