JPH02256307A - Binary transversal filter - Google Patents

Abstract

PURPOSE:To eliminate the need for a memory for high speed operation, to increase number of taps and to improve the resolution by allowing n-set of memories to apply weighting sum processing to a received input data while being shared. CONSTITUTION:Two ROMs 11, 12, two shift registers 21, 22 and a data selector 30 are provided to binary transversal filters. Then, a received data DTin is given to the shift registers 21, 22, in which the data is sampled mutually at an interval of one period with a phase difference of pi respectively. The weight sum data corresponding to an output data of the shift registers 21, 22 is read from the ROMs 11, 12. Then the data are selected alternately alternatively with a data selector 30 and D/A-converted, then even When a minute tap weighted data is obtained, the CLK 11, 12 can select the data DTin while the speed of a clock CLK is kept without any modification.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a binary transversal filter used for roll-off shaping in, for example, a digital wireless communication device.

(Prior Art) Circuits that perform roll-off shaping in digital wireless communication systems include conventional frequency domain filters such as LCR filters and time domain filters such as binary transversal filters. Among these, in the case of a binary transversal filter, for example, an m-value filter, firstly, received input data is sampled using a clock obtained by multiplying the clock by n, and is serially shifted into a shift register. Data is output in parallel from this shift register every time one bit is shifted and input, and the parallel output data is supplied as an address to a read-only memory (ROM) serving as a weighted addition circuit. This ROM stores in advance weighted addition data corresponding to all patterns of data supplied as the addresses.

Therefore, each time data is output in parallel from the shift register, weighted and added compensation data corresponding to this data is read out from the ROM. And this R
The compensation data read from the OM is converted into an analog signal by a digital-to-analog converter, smoothed, and output. When this type of filter is used, since it operates digitally, it is possible to always perform close to ideal compensation for input data.

(Problem to be Solved by the Invention) However, such a conventional filter samples the received input data with a clock n times as large as the received input data and accesses the ROM. For this reason, a high-speed ROM that operates at n times the speed of the transmission lock is required, and this type of ROM generally has a small capacity, so the number of taps cannot be increased, and the resolution cannot be increased. was there. Moreover, even larger capacity wireless transmission systems could not be used due to the operating limits of the ROM.

Therefore, the present invention focuses on this point and aims to increase the number of taps and improve the resolution by eliminating the need for memory for high-speed operation.
The purpose of the present invention is to provide a binary transversal filter that can be used satisfactorily even in large-capacity wireless transmission systems.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides an m-value binary transversal filter that samples received data at one period interval with a mutual phase difference of 2π/n and serially samples the received data at one period interval. Input the m x n shift registers to be shifted in and the parallel outputs of these m x n shift registers as addresses, and read out the weighted addition data stored in advance corresponding to these parallel outputs. X n memories,
A selector that sequentially selectively outputs each weighted addition data read from these m×n memories, and an analog signal of the weighted addition data selectively outputted by this selector at a frequency n times the sampling frequency. It is equipped with a digital-to-analog converter for converting into

(Function) As a result, according to the present invention, the weighted addition process for the received input data is divided among n memories, so even when obtaining fine tap weighting data, each memory is operated at the clock speed of the data. It is possible to operate with

Therefore, a memory for high-speed operation is not required, and therefore, the number of taps can be increased and the resolution can be improved. It also becomes possible to apply it to large-capacity wireless transmission systems.

(Example) Next, an example of the present invention will be described with reference to the drawings. still,
In this embodiment, the cases of m-1 (binary) and n-2 (π phase shift) will be explained as examples.

FIG. 1 shows the configuration of a binary transversal filter in the same embodiment.

This filter consists of two read-only memories (ROMs) 1
1.12, and two bit shift registers 21.22 provided corresponding to these ROMI 1.12,
It is equipped with a data selector 3o.

First of all, the shift register 21 samples the received data DTin in synchronization with the clock CLK delayed by π/n (in this embodiment, n-2, so π/2) by the delay element 41, and serially shifts the input data. On the other hand, the shift register 22 samples and serially inputs the received data D T in in synchronization with the clock delayed by the delay element 41 and further delayed by 2π/n (equal to π) by the delay element 42 . That is, these shift registers 21 and 22 sample the received data DT1n with a mutual phase shift difference of 2π/n (π).

These shift registers 21 and 22 shift input of the received data D T in by one bit each time.
The input bit data (A1) (A2) are output in parallel and supplied to each of the ROMIs 1 to 12 as addresses.

ROMII, 12 are the shift registers 21, 22,
The tap weighted addition data corresponding to all patterns of the data fAt ], (A21 supplied from the shift registers 21 and 22 are stored in advance, and this data is Tap weighted addition data (Dl) corresponding to data
, (D2) is read. The data selector 30 receives the tap weighted addition data +D11 . +D21, the delay element 41
The digital-to-analog (D/A) converter 50 alternately switches and outputs alternatively in synchronization with the delayed clock.
supply to. Note that 43 is a delay element that finely adjusts the timing of the switching clock.

The D/A converter 50 selects and outputs the tap weighted addition data (D+ l , N
) 21 by the multiplier 51 (nm2 in this embodiment)
Therefore, each signal is converted into an analog signal in synchronization with a clock that has been multiplied by 2. After harmonic components are removed from this analog signal by a low-pass filter 52, it is output as data DTout with waveform distortion compensated for. Ru.

Because of this configuration, if the received data D T
Single pulse with period T (-0,5T≦0
, 5T period is "1 degree, and other periods are "0"). Then, this received data DTln is shifted into the shift registers 21 and 22 in synchronization with the clock CLK. At this time, , each shift register 1
1. ．． The clock CLK supplied to delay element 4
By passing through 1.42, there is a phase difference of π from each other.

Therefore, when the received data DTin is input to the shift registers 21 and 22, they are sampled at timings having a phase difference of π from each other and at each cycle.

The received data input to each shift register 21.22 is then output as bit (e.g. 8 bits) parallel data iA1), (A2) every time one bit is input. are respectively supplied as addresses.

Here, each ROM II, 12 has a shift register 21.
Tap weighted addition data corresponding to all patterns of received data (A1) (A2) supplied from 22 is stored in advance. For example, for received data of a single pulse with a period T, the ideal pulse response x shown in FIG.
Weighted addition data representing (t) is stored in advance.

Therefore, the sampling data fA1) of the single pulse received from each shift register 21 and 22, (
When A21 is output as an address, each ROMII,
From 12 onwards, aO+22+... shown in Figure 2 respectively.
, a14 and al+ a3+ . . . a 15 weighted addition data (8 bits) N) tl (D2) are read out, respectively. Then, these weighted addition data (D+l, fD2) are outputted by the pig selector 30 to the clock CLK which has passed through delay elements 41 and 43, respectively.
are selected and output alternately in synchronization with. For example, the weighted addition data (Dl) read from the ROMII is selected during the "H" level period of the clock CLK, while the weighted addition data (D2) read from the ROM 12 is selected during the "L" level period of the clock CLK. selected.

The weighted addition data (Dl) and (D2) alternately selected and output from the data selector 30 are D/A
Converter 50 is supplied. And this D/A converter 5
After the digital signal is converted into an analog signal at 0, the harmonic components are removed by the low-pass filter 52, resulting in a compensated single pulse (pulse response X(t) shown in Figure 2). Output.

In this embodiment, in the binary transversal filter, two ROMII, 12 and two shift registers 21, 22 and a data selector 30 are provided, and the received data DTin is sent to each of the shift registers. 21 and 22 are sampled at one period interval with a mutual phase difference of π, and these shift registers 2
The weighted addition data corresponding to the output data of 1°22 is read out from each of the ROM IIs and 12, and these weighted addition data are alternately and selectively selected by the data selector 30 for use in D/A conversion. , the weighted addition process for the received data D T In is performed by two ROs.
Since the process is shared between MII and MII 12, even when obtaining detailed tap weighting data, each ROMII
, 12 can operate as they are at the speed of the clock CLK of the received data DTIn. This eliminates the need for a ROM for high-speed operation, allowing the number of taps to be increased and resolution to be improved. Furthermore, since the data selector 30 can be directly caused to perform a selection operation using the clock CLK of the received data DT1n, a high-speed data selector can be made unnecessary. Therefore, it is possible to fully apply the present invention to large-capacity wireless transmission systems.

Note that the present invention is not limited to the above embodiments. For example, in the above embodiment, the case of n-2 (π phase) has been described, but it can be implemented in the same way even in the case of n-3 or more. For example, in the case of n-4, there are 4 ROMs, 4
It is sufficient to provide four shift registers and a data selector capable of selectively selecting one of the four shift registers, and to sample and shift received data using the four shift registers at timings having a phase difference of π/2. Further, in the above embodiment, the case where a single pulse is input as received data has been explained as an example, but by storing in advance weighted addition data corresponding to patterns of all received data that can be input to each ROM, Compensation can be made in the same way even if any other pattern of received data is input.

In addition, the type and configuration of the memory that stores the weighted addition data, the configuration of the D/A converter, the number of input bits, etc. can be modified in various ways without departing from the gist of the present invention.

[Effects of the Invention] As described in detail above, according to the present invention, mxn shift registers each sample received data at one period interval with a phase difference of 2π/n and serially shift input; m x n memories into which the parallel outputs of these m x n shift registers are input as addresses, respectively, and weighted addition data stored in advance corresponding to these parallel outputs are read out; a selector that sequentially selectively outputs each weighted addition data read from the memory; and a selector that converts the weighted addition data, which has been increased in selection ratio, into an analog signal at a frequency n times the sampling frequency. By being equipped with a digital-to-analog converter, it is possible to increase the number of taps and improve resolution without the need for memory for high-speed operation, and the binary transversal can be used satisfactorily even in large-capacity wireless transmission systems. Filters can be provided.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram showing the configuration of a binary transversal filter according to an embodiment of the present invention, and FIG. 2 is a diagram showing an example of a pulse response waveform used to explain the operation of the filter. 11.12...Shift register, 21.22...R
OM, 30...Data selector, 41, 42°43.
...Delay element, 50...D/A converter, 51...2
Multiplier, 52...Low pass filter.

Claims (1)

[Claims] In an m-value binary transversal filter, there are m×n shift registers that sample received data at one period interval with a mutual phase difference of 2π/n and serially shift the input data, and these m×n shift registers. There are m×n memories into which the parallel outputs of the shift registers are respectively input as addresses and pre-stored weighted addition data corresponding to these parallel outputs are read out, and data read out from these m×n memories. a selector that sequentially selectively outputs each of the weighted addition data; and a digital converter that converts the weighted addition data selectively output from the selector into an analog signal at a frequency n times the sampling frequency.
A binary transversal filter characterized by comprising an analog converter.