RU2172554C2 - Delta-codec - Google Patents

Abstract

FIELD: electrical communications; digital telephone sets. SUBSTANCE: delta-codec that has analog integrators of first and second digital-to-analog converters of delta-coder and delta-decoder, respectively, as well as input low-frequency filter and fifth-order output filter built around change-over capacitors whose capacitance is passed from phase-locked loop at frequency of 128 kHz which is synchronized in phase at frequency of 32 or 64 kHz of input sync signal is provided, in addition, with input digital signal level shifting device. Delta-codec circuit is built around single chip which provides for its miniaturization and makes it possible to vary data transmission rate in codec and to extend codec speed variation range . EFFECT: improved conversion of fast-varying analog signals into digital form. 4 cl, 1 dwg

Description

 The invention relates to techniques for electrical communications and can find application, for example, in digital telephones for the qualitative conversion of rapidly changing analog signals into digital form.

Closest to the claimed solution for the technical nature and the technical result achieved is the delta codec for Auth. St. USSR N 1725398, publ. 04/07/92, M. Cl. ⁵ H 03 M 3/02, comprising a delta encoder and a delta decoder, the delta encoder comprising a comparator, the output of which is connected to the first input of the first quantization step change control circuit (SIDC), in which the first shift register is included in the first input, and the output is the first digital-to-analog converter (DAC), to the first input of which the first digital integrator is connected, the output of the first ICM circuit is connected to the first input of the comparator, the second input of which is connected to the first input information bus, and to the first output information bus the output of the serial code of the first shift register, which is also connected to the second input of the first DAC, is connected, the delta decoder contains the second ICD circuit, in which the second shift register is turned on at the first input, and the second DAC is connected at the output, the second digital is connected to its first input integrator, the output of the second ICC circuit is connected to the second output information bus, and the first input of the second ICC circuit is connected to the second input information bus, while the output of the serial code of the second shift register is connected to orym input of the second DAC.

 In this delta codec, the first quantization step change control circuit consists of the first shift register, the first logic circuit, the first digital integrator, the first DAC and, accordingly, the second ICC circuit consists of the second shift register, the second logic circuit, the second digital integrator, the second DAC, for a clock generator uses a reference generator, and in the delta encoder and delta decoder circuits, digital integrators are made using a reversible counter, quantization step decoders, multi plexors. And analog DAC integrators use resistive arrays.

 The main disadvantages of this delta codec are both the impossibility of changing the information transfer rate in the delta codec due to the use of a clock reference generator, and the use of elements of the functional nodes of the codec circuit in the form of a resistive matrix in the digital-to-analog converters of the encoder and decoder that are difficult to implement on a single chip. And all this does not allow expanding the ranges of change of encoder operating speeds and providing miniaturization of the entire codec circuit execution.

 The basis of the invention is the task of creating an effective delta codec by providing both changes, if necessary, the information transfer rate in the codec, and the execution of its entire circuit on a single chip, which will allow both to expand the range of variation of the codec's operating speeds and provide miniaturization his whole scheme.

 The problem is solved in that in a delta codec containing a delta encoder and a delta decoder, the delta encoder comprising a comparator, the output of which is connected to the first input of the first quantization step change control circuit (CID), in which the first input includes the shift register, and the output is the first digital-to-analog converter (DAC), to the first input of which the first digital integrator is connected, the output of the first ICM circuit is connected to the first input of the comparator, the second input of which is connected to the first input information the first bus, and the output of the serial code of the first shift register, which is also connected to the second input of the first DAC, is connected to the first output information bus, the delta decoder contains the second UISHK circuit, in which the second shift register is turned on at the first input, and the second DAC at the output , to the first input of which a second digital integrator is connected, the output of the second ICMI circuit is connected to the second output information bus, and the first input of the second ICMI circuit is connected to the second input information bus, while the output is sequential The second code of the second shift register is connected to the second input of the second DAC. In this case, the analog integrators of the first and second DACs, respectively, of the delta encoder and delta decoder are made on switched capacitors and a phase locked loop (PLL) is introduced, the output of which is connected via the clock generator to the corresponding clock inputs of the first and second DACs, while the output the PLL clock is connected to the corresponding inputs of the first and second shift registers, the first and second DIs, and the first and second PLL inputs are the sync bus, respectively and the first delta codec control bus. The PLL block circuit contains a voltage controlled oscillator (VCO), the output of which is the PLL output and connected through a divider to the PLL output clock and the first input of the phase comparator, the second input of which is connected to the bus through the first level shifter of the input digital signals (CMSC) sync pulses of the delta codec, while the output of the phase comparator through the first low-pass filter (LPF) is connected to the input of the VCO, and the second input of the divider is connected through the second device of the control system to the first control bus del and codec. Also, the delta codec contains a third control system, the input of which is connected to the second control bus of the delta codec, and the output is connected through the first control input of the first ICC circuit with the corresponding control inputs of the first shift register, the first and second DI, the fourth control system, the input of which is connected with the third control bus of the delta codec, and the output is connected to the second control input of the first ICC circuit. The first input of the second UISHK circuit is connected to the second input information bus through the fifth control system. It contains the sixth control system, the input of which is connected to the fourth control bus of the delta codec, and the output is connected through the third control inputs of the first and second UISHK circuits, respectively, with the corresponding control inputs of the first and second digital integrators. In addition, in the delta encoder, the first input data bus is connected to the second input of the comparator via a series-connected differential amplifier, an anti-aliasing filter and a second low-pass filter, which is made on switched capacitors and whose clock input is connected to the corresponding output of the clock shaper. And in the delta decoder, the output of the second ICIS circuit is connected to the second output information bus through a fifth-order filter and a third low-pass filter, connected in series, while the fifth-order filter is made on switched capacitors and whose clock input is connected to the corresponding output of the clock generator. Between the output of the first encoder ICC circuit and the first output information bus, an output device with three operating states, respectively, on, off, and switching, is turned on, and the control input of the output device is the fifth control bus of the delta codec.

 The implementation of analog integrators of the first and second digital-to-analog converters of a delta encoder and a delta decoder on switched capacitors with the introduction of a PLL, in which the PLL outputs are connected to the control inputs of the first and second DACs, allows for the implementation of the entire codec circuit on a single chip, because elements in the form of resistive matrices in the DAC of the encoder and decoder are excluded, which are difficult to implement in doing so, thereby miniaturizing the execution of the entire delta codec circuit. At the same time, at the same time, if necessary, a change in the information transfer rate in the codec is ensured, at which the quality of the codec does not decrease due to phase-locked loop frequency adjustment, thereby expanding the range of changes in the speed of the codec while maintaining its qualitative performance.

 The implementation of the PLL with a divider of the pulse repetition rate applied to the phase comparator and to the first and second shift registers, the first and second digital integrators allows for a change in the transmission rate of information in the codec.

 Using the first and second devices for shifting the levels of input digital signals in the PLL allows you to reduce the level of switching interference by transferring the incoming pulses from a low level to a higher one, where the signal-to-noise ratio is higher.

 The use of a third device for shifting the levels of input digital signals, connected to the first shift register and the first and second digital integrators of the first and second ICM circuits, can also reduce the level of switching noise.

 Using the fourth device for shifting the levels of input digital signals connected to the first logic circuit through the second control input of the first ICC circuit, it also allows reducing the level of switching noise.

 The use of a fifth device for shifting the levels of input digital signals connected to the second shift register through the first input of the second ICC circuit also allows reducing the level of switching noise.

 The use of the sixth device for shifting the levels of input digital signals connected to the corresponding control inputs of the first and second digital integrators, respectively, of the first and second ICM circuits, can also reduce the level of switching noise.

 The implementation of the input filters of the delta encoder on switched capacitors with the connection of their control through the pulse shaper to the PLL allows for their miniaturization while maintaining the required quality of their work when the information transfer speed changes.

 The implementation of the output filters of the delta encoder on switched capacitors with the connection of their control through the pulse shaper to the PLL allows for their miniaturization while maintaining the required quality of their work when the information transfer speed changes.

 The use of an output device with three operating states in the delta codec allows additionally providing both on / off of the encoder output and switching of its output.

 The above confirms the existence of a causal relationship between the totality of the essential features of the claimed invention and the achieved technical result.

 This set of essential features allows, in comparison with the prototype, to ensure the implementation of the entire codec scheme on one chip, while simultaneously ensuring, if necessary, changing the information transfer rate in the codec, which in turn allows miniaturizing the delta codec scheme and expanding the range of codec speed changes while maintaining its high-quality performance indicators.

 According to the authors, the claimed technical solution meets the criteria of the invention of "novelty" and "inventive step", because the set of essential features characterizing the claimed delta codec is new and does not follow explicitly from the prior art.

 The invention is illustrated in the drawing, which shows a structural diagram of a delta codec.

 A preferred embodiment of the delta codec in accordance with the drawing comprises a delta encoder 1 and a delta decoder 2, the delta encoder 1 comprising a differential amplifier 3, an anti-aliasing filter 4, a second low-pass filter (LPF) 5 connected in series with its outputs / inputs on switched capacitors, comparator 6, first shift register 7, first logic circuit 8, first digital integrator 9 (DI), first digital-to-analog converter 10 (DAC) made on switched capacitors, output device 11, but The ta-decoder 2 contains a second shift register 12, a second logic circuit 13, a second DI - 14, a second DAC - 15 made on switched capacitors connected in series with its first information outputs / inputs, a fifth-order filter 16 made on switched capacitors, and a third low-pass filter 17, phase locked loop 18 (PLL), consisting of a voltage controlled oscillator (VCO) 19, a frequency divider 20 into two or four, a phase comparator 21, the first low-pass filter-22, while the output of the VCO-19 is the output of block 18 and connected through The divider 20 with the output of the clock pulses of the block 18 and the first input of the phase comparator 21, the second input of which is connected to the input bus 24 of the clock pulses through the first device 23 for shifting the levels of the input digital signals (СУВЦС), and the output of the phase comparator 21 is connected to the input of the VCO through the first LPF-22 -19, and the second input, which is the control input of block 18, divider 20, is connected through the second device СУВЦС-25 to the first control bus 26 of the delta codec.

 In the delta encoder 1, the differential amplifier 3, the anti-aliasing filter 4 and the second low-pass filter 5 are the input filter circuit, and in the delta decoder 2 the fifth-order filter 16, the third low-pass filter 17 is the output filter circuit, while the first input data bus 27 is connected with the input of the differential amplifier 3, the first DAC 10 is connected to the first input of the comparator 6, the second input of which is connected to the output of the second low-pass filter-5, and the corresponding outputs of the parallel code of the first shift register 7 are connected to the corresponding inputs of the first logic circuit 8, the output of the serial code of the first register 7 is connected to the second information input of the first DAC-10 and through the output device 11 to the first output information bus 28, the control input of the output device 11 is connected to the fifth control bus 29 of the delta codec, and the third bus 30 control system, the delta codec is connected through the fourth device 31 to the control system with the control input of the first logic circuit 8. The second input information bus 32 is connected through the fifth device 33 to the control system from the information input of the second register 12 shift, while the corresponding outputs of the parallel code of the second register 12 are connected to the corresponding inputs of the second logic circuit 13, the output of the serial code of the second register 12 is connected to the second information input of the second DAC-15, and the output of the third low-pass filter-17 is connected to the second output information bus 34. The second bus 35 for controlling the delta codec through the third SUVTSS-36 device is connected to the corresponding control inputs of the first register 7, the first and second TsI-9 and 14, the fourth bus 37 is connected through the sixth SUVTSS-38 device Nena with the respective control inputs of said first and second digital integrators. The PLL clock output is connected to the corresponding clock pulses of the first and second shift registers 7 and 12, the first and second digital integrators 9 and 14. The PLL output at the output of the VCO-19 through the corresponding outputs of the shaper 39 is connected to the corresponding clock inputs of the first DAC-10, the second LPF -5 and second DAC-15, filter 16 of the fifth order.

 In this case, the first quantization step change control circuit (SISC) 40 consists of a first shift register 7, a first logic circuit 8, a first digital integrator 9, a first DAC - 10 and, accordingly, a second SIRC circuit 41 consists of a second shift register 12, a second logic circuit 13 , the second digital integrator 14, the second DAC - 15.

 Logic circuits 8, 13 are made in the form of the first and second "AND" circuits, the outputs of which are connected to the corresponding inputs of the "OR" circuit, while the first "I" circuit has four direct inputs, and the second "I" circuit has four inverse inputs, which are connected to the corresponding outputs of the parallel code of the shift registers 7 or 12, and the output of the OR circuit of the corresponding logic circuits 8, 13 is connected to the corresponding input of the DI 9 or 14. At the same time, the level of the logic unit appears at the output of the OR circuit whenever in the input pulse sequence, at the inputs of logic circuits 8, 13 at least four identical symbols (0000 or 1111) follow in a row. And the logic circuits 8, 13 are logic circuits for allocating the same symbols (BOC).

 In another embodiment of the logic circuits 8, 13, the first and second "And" circuits may have a number of direct lines and a corresponding number of inverse inputs other than four. In this case, the number of outputs of the parallel code of the registers 7 or 12 shifts accordingly changes.

One of the options for performing logic circuits 8 and 13 and their connection in the delta codec is described in ed. St. USSR N 1725398, publ. 04/07/92, M. Cl. ⁵ H 03 M 3/02 "Delta codec".

 The output device 11 is made in the form of a logical repeater (buffer amplifier) with a control input that provides the output device 11 with three states: on, when a logical “1” signal is present at the output, off — a logical “0” signal is present at the output, switching - at the output there is a high-resistance state (i.e., an open state with an output resistance of more than 10 MOhm) and can be performed on the K561LN1 chip (see page 207, V.I.Shilo, Popular digital circuits, Chelyabinsk, “Metallurgists” "Chelyabinskoye Office, 1988). The third state provides the ability to switch during parallel operation of the delta codecs.

 Devices 23, 25, 31, 33, 36, 38 for shifting the levels of input digital signals are made in the form of logic level converters (buffer amplifiers), for example, using the K564PU6 chip (see page 218, V.I.Shilo, Popular digital microcircuits, Chelyabinsk, Metallurgy, Chelyabinsk Branch, 1988). These converters contain several channels for shifting logic levels from low to high with their control input. Such a shift provides normalized levels of logical signals at the outputs of the control system.

 The delta codec works as follows.

 The signal from a microphone (not shown) through the first input information bus 27 is fed to the input of a differential amplifier 3, which simultaneously amplifies and forms a band of the transmitted signal from 0.3 to 3.4 kHz, passes an anti-aliasing filter 4 with a cutoff frequency of 10 kHz, which counteracts the imposition of spectra, excluding false low-frequency components, and then the signal goes to the second low-pass filter-5, performed on switched capacitors, the capacitance of which is switched at a frequency of 128 kHz, providing the necessary filter 5 whose analog output signal is supplied to a second input of the comparator 6, the first input of which is applied the reduced value of the signal in the previous time from the DAC 10 output. As a result of comparator 6 of these two signals, an error signal is generated at its output, which is fed to the information input of the first register 7, while in the circuit consisting of the first shift register 7, the first logic circuit 8, the first digital integrator 9, the first DAC-10 , the change in the quantization step is controlled.

 In this case, the logic circuit 8 generates a signal of increment of the quantization step in the presence of three or four (depending on the given companding law) logic “1” or logic “0” at the outputs of the parallel code of shift register 7 and vice versa, when logical “1” and logical are alternated "0" conditions are created to reduce the quantization step and, accordingly, better transmission of low-level signals. In the first case, the input of the digital integrator 9 receives a logical "0", and in the latter, a logical "1".

 With a positive value of the error signal in this circuit, a pulse of positive polarity is formed at the output of the DAC-10, otherwise a pulse of negative polarity.

 The magnitude of the quantization step is determined by the amplitude of the output pulses of the DAC-10, in which the matrix of the analog integrator is made on switched capacitors, the capacitance of which is switched at a frequency of 128 kHz to restore the analog signal from the signal received in it in digital form. The delta decoder 2 circuit works in a similar way when a digital signal is input from the bus 32 to the input of the second shift register 12 with the control of changing the quantization step when the signal passes through the second logic circuit 13, TsI-14, TsAP-15, at the output of which the signal passes a fifth-order filter 16, made on switched capacitors, the capacitance of which is switched at a frequency of 128 kHz, providing the necessary filter characteristic, then the signal passes the third low-pass filter-17 and enters the second output bus 34 information ui.

 And from the output of the serial code of the register 7, the signal is digitally transmitted through the output device 11 to the first output information bus 28. In this case, the PLL ensures phase synchronization of the control of switched capacitors in the second low-pass filter-5, the fifth-order filter 16 and the analog integrators DAC-10 and DAC-15 at a frequency of 128 kHz, the inputs of which the control signal is supplied from the PLL through the generator 39 clock pulses. The phase of the frequency of 128 kHz is synchronized by the PLL with the phase of the stable frequency of 32 kHz of the clock signal, which is fed to the input of the phase comparator 21 of the PLL from the input bus 24 of the clock pulses.

 The compliance of the proposed technical solution to the criteria of the invention "industrial applicability" is confirmed by the specified example of the implementation of the delta codec.

Claims (4)

 1. A delta codec comprising a delta encoder and a delta decoder, wherein the delta encoder includes a comparator, the output of which is connected to the information input of the first quantization step change control circuit (DCI), the output of which is connected to the first input of the comparator, the second input which is the first input information bus of the delta codec, the first output information bus of which is the output of the serial code of the HMI control circuit, and the delta decoder includes the second HMI control circuit, the output and the first input of which oh are respectively the second output information bus and the second input information bus of the delta codec, as well as a clock generator (TI), characterized in that a controlled voltage generator (VCO) is introduced into it, the output of which is connected through the frequency divider to the first input of the phase comparator whose output through the first low-pass filter (LPF) is connected to the input of the VCO, the output of which is also connected to the input of the shaper TI, the outputs of which are connected to the corresponding clock inputs of the first and second Ishk control schemes, the frequency divider output is also connected to the respective clock inputs of the first and second Ishk control circuits, and the second input of the phase comparator and the other input of the frequency divider are respectively the clock bus and the first bus master delta codec.  2. The delta codec according to claim 1, characterized in that in the delta encoder the first input information bus of the delta codec is connected to the second input of the comparator through a series-connected differential amplifier, anti-aliasing filter and a second low-pass filter, which is made on switched capacitors, and a clock the input of the second low-pass filter is connected to the corresponding output of the shaper TI.  3. The delta codec according to any one of claims 1 and 2, characterized in that in the delta decoder the output of the second HMI control circuit is connected to the second output information bus of the delta codec through a fifth-order filter and a third low-pass filter, the fifth filter order is made on switched capacitors, and the fifth-order filter clock input is connected to the corresponding output of the clock shaper.  4. The delta codec according to any one of claims 1 to 3, characterized in that the output device is entered with three operating states, respectively, on, off and switch, the output of the serial code of the first control circuit of the HMI connected to the input of the output device, the control input and the output of which is the fifth control bus and the first output information bus of the delta codec, respectively.