JPH04107953A - Wiring method of semiconductor device - Google Patents

Abstract

PURPOSE:To conduct arrangement and wiring according to a current density by obtaining a current value through simulation for each net, by comparing the current value with an allowable current value and by changing the arrangement or wiring width, when the current value exceeds the allowable current value. CONSTITUTION:A unit no-load current flowing per unit frequency of each cell or element to be laid out and the lead-dependent factor of each cell or element is prepared beforehand. Also, a logical simulation 14 is conducted based on logic circuit data 12 and operating test pattern data 13 to obtain the number of times of operation of each net so that the number of times of operation of each net and the test period and number of test patterns at that time are prepared beforehand. Each cell or element is arranged and wired based on logic circuit data 12; a wiring information composed of wiring width, wiring length and load capacity is obtained for each net; and the value of a current flowing through each net is operated based on the number of times of operation, test period, number of test patterns and wiring information. When the current value exceeds an allowable current value, the arrangement or wiring width is changed. Thus, it is possible to prevent electromigration.

Description

[Detailed Description of the Invention] [Summary] Regarding a wiring method for a semiconductor device, the purpose is to enable wiring with a line width that corresponds to the current density, and to prevent harmful effects such as electromigration and local heating. The unit no-load current flowing per unit frequency of a cell or element and the load dependence coefficient of each cell or element are prepared in advance, and a logic simulation is performed based on logic circuit data and operation test pattern data to calculate the number of operations of each net. The number of operations for each net, the test cycle at that time, and the number of test patterns are prepared in advance, and each cell or element is placed and routed based on the logic circuit data, and the wiring width, wiring length, and load are calculated for each net. The wiring information consisting of capacitance is obtained, and the current value flowing through each net is calculated based on the number of operations, test cycle, number of test patterns, and wiring information. If this current value exceeds the allowable current value, the cell or element is Configurations that change the layout or wiring width (7).

In addition, data on the unit no-load current, load dependence coefficient, and wiring width of multiple types of wiring for each wiring layer are prepared in advance, and a logic simulation is performed using logic circuit data and operation test pattern data to perform the number of operations for each net. , find the test period and the number of test patterns, calculate the wiring conditions for each net of the logic circuit based on the prepared unit no-load current, load dependence coefficient, wiring width, and number of operations,
The configuration is such that the logic circuit is arranged and routed based on the wiring conditions.

[Industrial application fields] The present invention relates to a wiring method for semiconductor devices.

In recent years, semiconductor devices have become more highly integrated, faster, and smaller. Accordingly, countermeasures such as electromigration of aluminum wiring, local heating, etc. will be required.

[Prior Art] Conventionally, automatic wiring and wiring systems perform placement and wiring according to the connection strength between each element or each block, with the main focus on increasing the integration and speed of semiconductor devices.

Further, one wiring width for power supply lines, signal lines, etc. is prepared for each wiring layer, and the wiring with the prepared line width is used fixedly.

[Problems to be Solved by the Invention] However, although the current density of each net depends on the operating frequency, load capacitance, and wiring width, the wiring width of each net in each wiring layer is different for each net. The line width was determined without consideration of the operating frequency and wiring capacity. As a result, the current density varied, causing problems such as chromatomigration and heat generation in areas where the operating frequency was high.

The present invention has been made in order to solve the above problems, and its purpose is to enable wiring with a line width that corresponds to current density, and to prevent harmful effects such as electromigration and local heating in semiconductors. An object of the present invention is to provide a method for wiring a device.

[Means for Solving the Problems] FIG. 1 is a principle flowchart explaining the first invention.

First, logic simulation is performed using logic circuit data and operation test pattern data.

Then, the number of times each net of the logic circuit operates is determined, and the test period and number of test patterns at that time are determined.

Further, the unit no-load current flowing per unit frequency of each cell or element laid out based on the logic circuit data and the load dependence coefficient of each cell or element are also prepared in advance.

Subsequently, each cell or element is arranged based on the logic circuit data. Wiring is performed after the placement of cells or elements is completed.

Next, for each net of the placed and routed logic circuit, the wiring width,
Find wiring information consisting of wiring length and load capacity.

Then, a current value for each net is calculated using this wiring information, the number of operations, the test cycle, the number of test patterns, the unit no-load current of the cell or element, and the load dependence coefficient.

The calculated current value is compared with a previously prepared allowable current value. If the allowable current value is exceeded, processing is performed to change the arrangement of cells or elements or change the wiring width.

FIG. 2 is a principle flowchart explaining the second invention.

First, the unit no-load current flowing per unit frequency of each cell or element laid out based on logic circuit data, the load dependence coefficient of each cell or element, and the wiring of multiple types of wiring prepared for each wiring layer. Prepare width data.

Logic simulation is performed based on the logic circuit data and operation test pattern data to determine the number of operations of each net. Next, wiring conditions are calculated for each net of the logic circuit based on the unit no-load current, load dependence coefficient, wiring width, and number of operations. Subsequently, the logic circuit is placed and routed based on the wiring conditions.

[Operation] In the first invention, the value of the current flowing for each net is determined by simulation, and the current value in that net is compared with an allowable current value at which no electromicrolysis or local heat generation occurs. As a result, if the allowable current value is exceeded, instructions are given to change the layout or wiring width, so each net is placed and routed according to the current density that corresponds to the actual operation. Problems such as clays and localized heat generation will no longer occur.

In the second invention, when performing placement and routing based on logic circuit data, the wiring conditions are determined for each net in advance, so placement and routing can be performed without electromigration or local heat generation. .

Embodiment 1 Hereinafter, the first wiring method for a semiconductor device embodying the present invention will be described.
Examples will be described according to the drawings.

FIG. 2 shows a system configuration diagram of an automatic wiring simulation device 11 for semiconductor integrated circuits consisting of a computer.
Logic circuit data stored in the logic circuit data storage means 12 and operational test pattern data stored in the operational test pattern storage means 13 are input to the automatic wiring simulation apparatus 11. This logic circuit data and operation test pattern data are stored in the logic simulation means 14.
is input.

The logic simulation means 14 calculates the number of operations, test period, number of test patterns, etc. of each net by simulation based on the logic circuit data in the logic circuit data storage means 12 and the operation test pattern data in the operation test pattern storage means 13. , is stored in the test pattern storage means 15 as test pattern data.

Further, the logic circuit data is input to a layout processing means 16 and a wiring processing means 17. Layout processing means 1
6 performs placement processing of each cell and element based on the logic circuit data in the logic circuit data storage means 12. In other words,
Layout processing is performed so that the distance between each cell and between elements is the shortest possible, and the wiring capacitance and wiring length are minimized as much as possible.

Next, the wiring processing means 17 performs actual wiring processing between each cell and between elements based on the result of this layout processing and the logical data.

Then, based on the actual wiring processing, the wiring information processing means 18 performs arithmetic processing on the wiring information for each net.

In other words, the wiring information processing means 18 calculates the wiring length for each net,
Wiring information consisting of wiring width, wiring capacitance, load capacitance, etc. is obtained, and after arithmetic processing is performed on this wiring information, it is stored in the wiring information storage means 19 as wiring information data.

Further, in the current data storage means 20 of the automatic wiring simulation device 11, a device simulator (not shown) is used to store the current value IO1 flowing through an element per unit frequency in a no-load state for each cell and each element, that is,
A unit no-load current value and its load capacity dependence coefficient 11 are calculated and stored as current data δ.

Then, based on the test pattern data, wiring information data, and current data stored in each of the storage means 15, 19, and 20, the current density calculation means 21 calculates the current value (2) flowing for each net.

In other words, the current value I flowing through each net is: ■ (Io + it xC) x Nx (1/ (TxPN
). Then, the current density calculation means 21 calculates the current value I based on this calculation formula, and then calculates the current density IO flowing for each net based on the wiring information data. Then, the determining means 22 determines that this current density Id is the same or lower than the allowable current density 1, which is calculated in advance by comparing this current density Id with the allowable current density ■ that does not cause electromigration or local heat generation in the net. If it is a value, the layout of each cell and element,
The actual wiring process connecting each cell and element is determined and terminated.

If the calculated current density Id exceeds the allowable current density 1k, a change command signal is sent to the determining means 22, layout processing means 16, and wiring processing means 17. Then, the layout processing means 16 changes the layout of each cell and element based on this change command signal, and then the wiring processing means 1
7, the actual wiring process is performed by widening the wiring width.

Then, after the wiring information processing means 18 calculates the wiring information data again, the current density 1d flowing in each net is calculated based on the calculation formula to make the current density Id lower than the allowable current density value Jk.

As a result, by changing the layout of cells and elements, the wiring length can be shortened and the wiring capacitance can be reduced, and the current capacity can be increased by widening the wiring width, which reduces electromigration and local heat generation. Prevention can be carried out.

Note that in this embodiment, the current density Id was determined and compared, or it is also possible to compare the current value I determined by the above calculation formula with a predetermined allowable current value.

Next, a second embodiment of the present invention will be described.

Components having the same configuration or the same function as those of the first embodiment will be designated by the same reference numerals and their explanation will be omitted.

As shown in FIG. 4, automatic wiring simulation device 1
1, the logic circuit data of the logic circuit data storage means 12 and the operation test pattern data of the operation data test pattern storage means 13 are input. That is, the logic circuit data and operation test pattern data are input to the logic simulation means 14.

The logic simulation means 14 calculates the number of operations of each net, the test period, the number of test patterns, etc. by simulation based on the logic circuit data and operation test pattern data, and stores them in the test pattern storage means 15 as test pattern data. .

Further, the automatic wiring simulation device 11 is provided with a wiring width data storage means 25 for storing wiring width data of a plurality of types of wiring prepared in advance for each wiring layer. and,
The logic data is calculated based on the logic circuit data from the logic circuit data storage means 12, the test pattern data from the test pattern storage means 15, the current data from the current data storage means 20, and the wiring width data from the wiring width data storage means 25. The wiring condition calculation means 23 calculates the wiring conditions for each net, and stores them in the wiring condition storage means 24 as wiring condition data. That is, the wiring conditions are determined for each net in advance, and the wiring condition data is calculated so that the conditions are such that electromigration, local heat generation, etc. do not occur.

Subsequently, the layout processing means 16 stores the wiring condition storage means 2.
Cells and elements are arranged based on the logic circuit data based on the wiring condition data stored in step 4. After the layout processing means 16 finishes arranging the cells and elements, the wiring processing means 17 performs actual wiring between each cell and between elements while adjusting the wiring width based on the wiring condition data.
The layout of each cell and element and the actual wiring process for connecting each cell and element are determined and the process ends.

In this second embodiment, the logic circuit data storage means 1
Layout processing means 16 based on the logic circuit data of 2.
Since the cell and element layout processing is performed based on the wiring condition data obtained by the wiring condition calculating means 23, the cell and element layout and wiring can be performed in advance without electromigration, local heat generation, etc. .

[Effects of the Invention] As described in detail above, the present invention has the excellent effect of enabling wiring with a line width that corresponds to the current density and preventing harmful effects such as electromigration and local heating.

FIG. 2 is a principle flowchart explaining the second invention, FIG. 3 is a block diagram showing a semiconductor device of the first invention, and FIG. 4 is a block diagram showing a semiconductor device of the second invention.

In the figure, LIT automatic wiring simulation device, 12 logic circuit data storage means, 13 operation test pattern data storage means, 15 test pattern storage means, 19 wiring information storage means, 20 current data storage means, 24 years old wiring. condition storage means; 25 is wiring width data storage means;

[Brief explanation of drawings]

FIG. 1 is a principle flowchart explaining the first invention; Figure 1 Figure 2 is a principle flow chart explaining the first invention.

Claims (1)

[Claims] 1. A unit no-load current flowing per unit frequency of each cell or element laid out based on logic circuit data and a load dependence coefficient of each cell or element are prepared in advance, and the logic circuit Logic simulation is performed based on the data and operation test pattern data to determine the number of operations of each net, the number of operations of each net, the test period at that time, and the number of test patterns are prepared in advance, and each cell is calculated based on the logic circuit data. Also, arrange and route the elements, obtain wiring information consisting of wiring width, wiring length, and load capacitance for each net, and calculate the current value flowing through each net based on the number of operations, test cycle, number of test patterns, and wiring information. 1. A wiring method for a semiconductor device, which comprises calculating the current value, and changing the arrangement of cells or elements or changing the wiring width if the current value exceeds an allowable current value. 2. The unit no-load current flowing per unit frequency of each cell or element laid out based on logic circuit data, the load dependence coefficient of each cell or element, and the wiring of multiple types of wiring prepared for each wiring layer. In addition to preparing width data, a logic simulation is performed based on the logic circuit data and operation test pattern data to determine the number of operations of each net, and the number of operations of each net, the test cycle at that time, and the number of test patterns are prepared in advance. Then, wiring conditions are calculated for each net of the logic circuit based on the prepared unit no-load current, load dependence coefficient, wiring width, and number of operations, and the logic circuit is placed and routed based on the wiring conditions. A wiring method for a semiconductor device, characterized in that: