JPH0756982A - Layout method and layoutability evaluation device - Google Patents

Abstract

PURPOSE:To shorten layout design time by evaluating the decree of difficulty of the layout of a designed circuit between a design process and a layout process, and correcting the circuit corresponding to an evaluation result. CONSTITUTION:In a computer device 11 for logical synthesis which comprises CAD, etc., a memory device 12 is constituted of a data base 15 for design consisting of logical design data and a floor plan, a data base 16 for prediction, and a know-how data storage part 17 in which know-how data that is criterion for the ease of the layout is stored. A processing part 13 evaluates the degree of difficulty of the layout of the circuit by comparing the design data stored in the data base 15 for design with the criterion in the know-how data storage part 17. A layout difficulty/ease evaluation process is provided between the design process and the layout process, and the circuit is corrected so as to perform the layout corresponding to the evaluation result, and after that, the layout is performed in the layout process. Therefore, the circuit can be corrected before the layout is performed actually.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout method and a layoutability evaluation device, and an LS
The present invention relates to a layout method and a layoutability evaluation device for performing layout and wiring to be mounted on I.

At present, as the scale of LSI is increasing, LS
The proportion of layouts in the design process of I has become extremely high. This is due to the increase in the time required for layout processing and the number of layouts.

The time required for the layout processing depends on the layout tool, and for example, an LSI having a 200K gate scale.
It takes more than a week, but if you do it once or twice, it is not a problem, and the number of times is a problem.

The number of layouts depends on the logic design and floor plan, and in order to reduce the number of layouts, it is necessary to keep the circuit from being modified after the layout process.

[0005]

2. Description of the Related Art FIG. 14 shows an explanatory view of a conventional LSI layout method. Conventionally, in the case of performing layout in an LSI, first, logic design is performed by CAD or the like (step S1-1).

Next, the circuit designed in step S1-1 is subjected to layout processing such as placement and wiring based on the floor plan (step S1-2). After the processing, the laid-out circuit is logically simulated and an error is discriminated (step S1-3).

When an error is determined in step S1-3 and the circuit needs to be changed, step S1
If the circuit is changed to -1 and the layout has a problem, the process returns to step S1-2 to repeat the layout process (step S1-4). If no error is detected in step S1-3, the layout is completed (step S1-5).

As described above, in the conventional LSI layout process, the layout process of arranging and wiring based on the floor plan is performed immediately after the logical design, and the circuit is corrected and the layout is changed until the error is eliminated. , The layout process was repeated.

[0009]

However, in the conventional LS,
In the layout in the design process of I, the layout was directly performed regardless of the ease of layout of the designed logic circuit to the given floor plan. Therefore, if the circuit needs to be modified, the circuit is modified. After doing
The layout process is required again, the number of layout processes is increased, and it takes time to design.

The present invention has been made in view of the above points, and a layout method and a layoutability evaluation for evaluating the ease of layout of a circuit designed before actual layout and shortening the layout design time. The purpose is to provide a device.

[0011]

According to the present invention, there is provided a layout method including a design process for designing a circuit and a layout process for performing a layout based on the circuit designed in the design process. And a layout difficulty evaluation step that evaluates the difficulty of the layout of the circuit designed in the design step, and corrects the circuit so that the circuit can be laid out according to the evaluation result in the layout difficulty evaluation step. Layout is performed in the layout process.

[0012]

Operation: Before the actual layout, the evaluation data indicating the difficulty level of the layout is obtained based on the design data designed in the design process, and the difficulty level of the layout is evaluated, so that the circuit layout of the circuit can be achieved without performing the actual layout. Determine the need for modification.

Therefore, the circuit can be modified before the actual layout, the circuit need not be modified after the layout, and the number of actual layouts can be reduced.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an explanatory diagram of a layout method according to an embodiment of the present invention. Step S4-1 shows a design process for performing logic design of a circuit mounted on the LSI. Logical design is CA
This is performed by a logic design computer device such as D. Next, based on the circuit data designed in step S4-1, an evaluation step (step S4-2) for evaluating the difficulty of the layout is performed. Evaluation process (Step S
In 4-2), the ease of layout of the circuit designed using the know-how data and the like obtained based on past experience is judged by the layoutability evaluation device described later.

If it is determined in step S4-2 that layout is possible, a layout step (step S4)
-3) is carried out. Layout process (step S4-
In 3), the layout such as wiring on the bulk is actually performed by the circuit designed by using a computer dedicated to the layout.

After the layout is completed, the circuit is simulated. If no error occurs as a result of the simulation, the layout is OK and the layout ends (steps S4-4 and S4-5).

If the layout is determined to be difficult in step S4-2, the circuit and floor plan are corrected until the layoutability evaluation apparatus determines that the layout is possible.

In other words, when the layout is actually performed in step S4-4, the layout is performed based on the design circuit data in a state in which the circuit is modified so that the layout is possible. Therefore, an error rarely occurs in step S4-4.

If an error occurs in step S4-4, if there is a change in the circuit, the circuit is modified in step S4-1, and the layoutability is evaluated again by the layoutability evaluation device. If the circuit is not corrected, the layout is redone (step S4).
-6).

Even if an error occurs in step S4-4, since layout ease is evaluated by the layoutability evaluation device and the circuit data has been corrected, many errors do not occur, and the layout does not occur. The number of times can be reduced.

As described above, by using the layoutability evaluation device in the layout process, the number of layouts can be reduced, so that the time required for layout can be reduced.

For example, when laying out a 200K class LSI, the layout process is conventionally performed at least three times, and if one layout process takes one week, it takes three weeks or more. The layoutability is evaluated by the layoutability evaluation device, and the layout process is performed after the design is changed according to the evaluation, whereby the layout can be completed by one layout process.

FIG. 2 shows a block diagram of the first embodiment of the layoutability evaluation apparatus used in the layout evaluation step (step S4-2) of the present invention. In the figure, 11
Indicates a computer device for logic synthesis which constitutes CAD or the like.

The computer device 11 mainly displays a storage device 12 in which various data are stored, a data processing unit 13 that executes a process based on the data stored in the storage device 12, and a result processed by the data processing unit 13. Display device 14
Etc. The storage device 12 is based on the logic design data previously designed by the computer for logic design, the design database 15 including a floor plan for deciding the arrangement of blocks on the bulk, and the logic design data stored in the design database 15. The generated prediction database 16 and the know-how data in which the know-how data, which is created in advance based on the past layout and serves as a criterion for determining the ease of the layout, are stored, are stored in the storage unit 17.

In the design database 15, the configuration of the logic elements and connections of the logic circuit to be mounted on the LSI is divided into blocks according to the function and stored. Based on the data stored in the design database 15, the prediction database 16 is used by the processing unit 13 as the usage rate, the number of terminals, and the number of basic cells BC (Bas) for each constituent block.
The number of ic cells), the number of nets, and the number of elements are calculated, and the predicted data at the time of layout generated based on these data is stored.

FIG. 3 shows an internal configuration diagram of the prediction database 16. The prediction database 16 is a chip name storage unit 18,
It is composed of a block number storage unit 19 and a prediction data management table composed of a block data table 20.

The chip name storage section 18 stores a chip name for distinguishing a chip to be evaluated (predicted),
A block data table 20 in which the number of blocks mounted on the chip is stored in the block number storage unit 19
Are prepared for the number of blocks, and each block data table has a block name storage unit 21, a usage rate storage unit 22, a terminal number storage unit 23, and a BC (Basic Cell) number storage unit 2.
4, net number storage unit 25, element number storage unit 26, number of terminals /
A net number storage unit 27, a BC number / element number storage unit 28, a terminal number / element number storage unit 29, a terminal number / BC number storage unit 30, and an inter-block net table 31.

The block name storage unit 21 stores block names for distinguishing blocks in each block data table. The usage rate storage unit 22 stores the ratio of each block to the whole. The terminal number storage unit 23 stores the number of terminals included in the block. The BC number storage unit 24 stores the number of basic cells (BC) such as flip-flops and AND gates. The net number storage 25 stores the number of nets in the block. The number of elements storage unit 26 stores the number of elements such as transistors used in the block. The number of terminals / number of nets storage unit 27 stores the ratio of the number of terminals to the number of nets in the block. The ratio of the BC number to the element number is stored in the BC number / element number storage unit 28. The number of terminals / number of elements storage unit 29 stores the ratio of the number of terminals to the number of elements. The number of terminals / number of BC storage unit 30 stores the ratio of the number of terminals to the number of BCs.

The inter-block net table 31 is prepared for each block connected to the block, and stores the number of nets for the other block connected to the block. The block name storage unit 32 and the nets are stored. The number storage unit 33 is included. Block name storage unit 32
The other party block name for distinguishing the other party block connected to the block is stored. The net number storage unit 33 stores the number of nets between the block and the partner block.

FIG. 4 shows a block diagram of the contents of the know-how data storage unit 17. The know-how data storage unit 17 is provided with a know-how table 35 for each usage rate, which is the ratio of blocks to the entire know-how data management table 34, and the know-how table stores the ratio of the number of terminals to the number of BCs at each usage rate. Has been done.

The know-how data indicates the ratio of the number of terminals to the limit number of BCs that can be laid out for each usage rate obtained by the layout processing up to now.

In the processing section B, after the prediction data is created based on the design data, the ease of layout is judged based on the prediction data and the know-how data.

FIG. 5 shows an explanatory diagram of the operation of determining the ease of layout of the processing unit 13. When determining the ease of layout, the processing unit 13 retrieves know-how data having the same usage rate as the usage rate stored in the prediction data of the prediction block whose ease is to be determined (step S2-
1).

Next, a comparison is made between the number of terminals / BC in the know-how data of the retrieved usage rate and the number of terminals / BC in the prediction block (step S2-2).

If the value of the number of terminals / BC number of the prediction block is larger than the value of the number of terminals / BC number of the know-how data as a result of the size comparison in step S2-2, the layout of the prediction block is more difficult than the past data. It shows that
A message indicating that the circuit needs to be modified is displayed on the display device 4 (step S2-3).

If the value of the number of terminals / the number of BCs of the prediction block is smaller than the value of the number of terminals / BCs of the know-how data as a result of the size comparison in step S2-2, the layout of the prediction block is possible from the past data. It is considered that there is, and a message to that effect is displayed on the display device 4. Next, the inter-block net table 21 is searched for the one having the maximum inter-block net number (step S2-4). Here, the one with the largest number of nets between blocks is the one with the largest number of nets connected to the prediction block. Placing the nets close to each other makes wiring easier and the area required for wiring can be made smaller. As an advantage. Therefore, the block having the maximum number of nets with respect to the prediction block is displayed on the display device 4 so that the layout can be easily performed (step S2-5).

The above steps S2-1 to S2-5 are executed for all blocks (steps S2-6, S).
2-7).

As described above, the easiness and difficulty of layout can be easily evaluated for each block mounted on the LSI based on the design data, and the layout of the blocks can also be suggested, so that the layout of the circuit before the actual layout is performed. Knowing the necessity of correction and an advantageous layout method, the layout can be executed smoothly.

FIG. 6 shows a block diagram of the second embodiment of the layoutability evaluation apparatus of the present invention. Computer device 41
Is composed of a storage device 42, a processing unit 43, and a display device 44.

The storage device 42 stores the design circuit database 4
5, temporary load capacity storage unit 46, bulk data library 4
7. The floor plan data storage unit 48. The design time database 45 stores data indicating the configuration of the circuit previously designed by the logic design computer.

The floor plan data storage unit 48 stores floor plan data for determining the arrangement position of each block constituting the circuit on the bulk.

FIG. 7 shows an explanatory view of floor plan data. FIG. 7A shows a plan view of the bulk. 49 in the figure
Indicates a bulk, and the module 5 is placed on the bulk 49.
0, 51, 52, 53, 54 and microcells 55, 5
6 shall be formed. FIG. 7B shows the floor plan data. The floor plan data is represented by the coordinates (x, y) of each component in the directions of the arrows X and Y, where "1" is a predetermined unit length, and the coordinates of the point a are (x, y) = (1, 1). , The module 50 has a rectangular shape, and therefore the point b (1,4
01) and the point c (100, 600) can be represented by the two points. Similarly, the module 51 is point d
It is represented by (1,201) and the point e (100,400). The module 52 has a point a (1, 1) and a point f (100,
200), the module 53 is point g (100,571),
Point h (200,600), module 54 is point i (10
0,301) and the point j (200,570).

Further, since the shapes of the microcells 55 and 56 are predetermined, the arrangement can be determined by the coordinates of one point. The microcell 55 is the point k (110, 130), and the microcell 56 is the point l (110, 10). ).

As described above, the floor plan data is stored in the modules 50 to 54 and the micro cell 5 on the bulk 49.
It is composed of coordinates that determine areas 5, 56.

The temporary load capacity storage unit 46 calculates the load capacity attached to the wiring generated in each block based on the floorplan data stored in the floorplan data storage unit 48,
It is stored as a temporary load capacity. This temporary load capacity is calculated by the processing unit 43 according to the size of each block.

The bulk data library 48 stores data relating to the characteristics of the bulk on which the circuit is mounted. FIG. 8 shows a block diagram of the bulk data library. The bulk data library 48 has a bulk data management table 57 provided for each block, and the bulk data management table 57 includes bulk size storage units 58 and 59, BC size storage units 60 and 61, a factor storage unit 62, and difficulty. And a wiring layer table storage unit 65.

The bulk size storage units 58 and 59 store the horizontal and vertical sizes of the bulk to be used. The BC size storage units 60 and 61 store the horizontal and vertical sizes of the basic cells used. The factor storage unit 62 stores a factor for calculating the wiring area according to the performance of the layout tool for layout.

The difficulty evaluation reference value storage unit 63 stores the usage rate of the reference which is the limit of layout on the bulk. The wiring layer number storage unit 64 stores the number of wiring layers used.

The wiring layer table 65 is provided for each wiring layer, and includes a wiring direction storage unit 66, a wiring length storage unit 67, a wiring width storage unit 68, a wirable line number storage unit 69, and a wiring dedicated area storage unit 70.

The wiring direction storage unit 66 stores data indicating the wiring direction of the wiring layer. The wiring length storage unit 67 stores data indicating the wiring length per unit capacity of the wiring layer. The wiring width storage unit 68 stores data indicating the wiring width. The writable number storage unit 69 stores data indicating the number of writable lines on a cell.
The wiring-dedicated area storage unit 70 stores data by occupying the amount of the wiring-dedicated area.

The processing unit 43 reads out necessary data from the data stored in the design circuit database 45, the temporary load capacity data storage unit 46, the floor plan data storage unit 47, and the bulk data library 48, and processes the data. The easiness of layout is evaluated, and the result is displayed on the display device 44.

FIG. 9 shows an evaluation operation explanatory diagram of the second embodiment of the present invention. When evaluating the easiness of layout, the processing unit 43 first reads the circuit data, the temporary load capacitance, the bulk data from the design circuit database 45, the temporary load capacitance data storage unit 46, the floor plan data storage unit 47, and the bulk data library 48. Input floorplan data, statistically calculate the temporary load capacity attached to the wiring of the circuit from the circuit data, perform simulation, and analyze the design data consisting of the total temporary load capacity etc. for each chip level or unit module (block) Create data (step S3-
1).

Next, floorplan-specific data consisting of floorplan-specific cell-placeable areas and wirable areas is created from the floorplan data and bulk data (step S3-2). At this time, the floorplan-specific data is created for each block.

Next, the following processing is executed for each block. First, the wiring area b is calculated (step S3-).
4).

The wiring area is obtained by the following equations (1) and (2).

(Temporary load capacity) × (wiring length per unit capacity) × (wiring width) = (wiring area a) (1) At this time, the layout tool uses all of the available wiring areas Therefore, the wiring area b that matches the performance of the layout tool is calculated by multiplying the wiring area a by bulk data and a predetermined factor α stored in advance in accordance with the layout reel.

A × α = b (2) Next, the cell allocable area for the wiring area is calculated (step S3-5). There are a region b in which wiring on a block is possible, a region c in which wiring is possible on a cell (hereinafter referred to as a wiringable region on a cell) c, and a region in which only wiring is possible (hereinafter referred to as “wiring dedicated region”) d.

Therefore, the area obtained by subtracting the on-cell wirable area c and the wiring exclusive area d from the wiring area b becomes the cell arrangable area e used as the wiring area required in the actual layout. This is an area where cells used as wiring areas can be arranged.

Therefore, (wiring area cell allocable area e) = (wiring area b)-(cell routable area c)-(wiring dedicated area d) (3) Next, cell allocable area f Is calculated (step S3-
6). The cell allocable area f is the cell use area g plus the cell allocable area e for wiring area calculated in step S3-5. Therefore, (cell usable area f) = (cell used area g) + (wiring area cell placeable area e) (4) Next, the usage rate of the cells on the block is obtained (step S
3-6). The usage rate h of the cell on the block is determined by step S
It is calculated by dividing the cell usable area f obtained in 3-6 by the cell arrangeable area i.

The cell allocable area i is a floor plan specific data and is a value already obtained for each block and indicates a cell allocable area on the block.

(Usage rate h) = (cell available area f) / (cell allocable area i) (5) Next, the difficulty level evaluation is executed based on the usage rate h obtained in step S3-7. And is displayed on the display device 44 (step S3-8).

Bulk data management table 4 is used for the difficulty evaluation.
7, the difficulty level evaluation reference value stored in the difficulty level evaluation reference value storage unit 53 is compared with the usage rate h obtained in step S3-7. For example, A is easy when possible, B when possible, and C when difficult. Is displayed.

At this time, if the usage rate h is sufficiently smaller than the difficulty evaluation reference value, the proportion of cells is small, so it is judged that wiring is easy, and A, the usage rate h is near the difficulty evaluation reference value. Sometimes, when the usage rate h is larger than the difficulty evaluation reference value, it is determined that the wiring is difficult because the ratio of the cells is large, and it is evaluated as C.

In the present embodiment, the evaluation of the difficulty level is divided into ranks A, B and C by comparison with the difficulty evaluation reference value, but the present invention is not limited to this and only the usage rate h is displayed. However, the designer himself may evaluate from the usage rate h.

FIG. 10 to FIG. 13 show actual evaluation examples.
The LSI of FIG. 10 is composed of four modules 81 to 84. The module 81 has 35,682 BCs, and the area is 212 basic cells in the X direction and 307 in the Y direction.
It has basic cells and its total temporary load capacity is 8143
8.2 (1u: 1u is a unit equivalent to Farad F)
Also, the BC / area is 54.8 (%) and the number of terminals is 4000.
4 (pieces), number of nets 9391 (pieces), P / N (number of terminals /
(Number of nets) 4426, the usage rate h is calculated as 80.4% in such a module 81, and the difficulty level is evaluated as B in this device. When the designer who performs the layout evaluated the module 81 in three stages of A, B, and C, the evaluation of B was also obtained, which was the same as the evaluation of this device. When the modules 82, 83, and 84 were also evaluated in the same manner, the evaluation of the device and the evaluation of the designer were the same.

FIG. 11 shows another LSI evaluated in the same manner as in FIG. 10. Some modules have different evaluations from the device and the designer, but the evaluations are almost the same.

Further, FIGS. 12 and 13 also evaluate different LSIs, respectively, and it can be seen that the evaluations by the device and the designer are substantially the same as in FIGS. 10 and 11.

As described above, as can be seen from FIGS. 10 to 13, according to the present evaluation apparatus, highly accurate evaluation is possible,
By using this, it is possible to find a difficult layout without actually performing the layout, and it becomes possible to modify the circuit before performing the layout. Further, when the layout fails, the main cause is a wiring failure of a specific block (short circuit due to a layout that cannot be wired). Can be evaluated, and the circuit can be promptly modified without unnecessary circuit modification.

[0069]

As described above, according to the present invention, the layout ease of the circuit designed before the layout processing is evaluated,
Since the circuit can be modified before the actual layout process,
The number of layout processes can be reduced, and the layout process time can be shortened.

[Brief description of drawings]

FIG. 1 is an operation explanatory diagram of an embodiment of a layout method of the present invention.

FIG. 2 is a configuration diagram of a first embodiment of an evaluation device of the present invention.

FIG. 3 is a configuration diagram of a prediction database of the first embodiment of the evaluation apparatus of the present invention.

FIG. 4 is a configuration diagram of know-how data of the first embodiment of the evaluation apparatus of the present invention.

FIG. 5 is an explanatory diagram of an evaluation operation of the first embodiment of the evaluation device of the present invention.

FIG. 6 is a configuration diagram of a second embodiment of the evaluation device of the present invention.

FIG. 7 is an explanatory diagram of floor plan data of the second embodiment of the evaluation device of the present invention.

FIG. 8 is a block diagram of bulk data of a second embodiment of the evaluation apparatus of the present invention.

FIG. 9 is an explanatory diagram of an evaluation operation of the second embodiment of the evaluation device of the present invention.

FIG. 10 is a diagram showing an evaluation result by a second embodiment of the evaluation apparatus of the present invention.

FIG. 11 is a diagram showing an evaluation result by a second embodiment of the evaluation device of the present invention.

FIG. 12 is a diagram showing an evaluation result by a second embodiment of the evaluation device of the present invention.

FIG. 13 is a diagram showing an evaluation result by a second embodiment of the evaluation apparatus of the present invention.

FIG. 14 is an operation explanatory diagram of a conventional layout method.

[Explanation of symbols]

 S4-1 Design process S4-2 Layoutability evaluation process S4-3 Layout process 12,42 Storage device 13,43 Processing unit 14,44 Display device

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Hiroshi Ikuma 3-28-1, Joto, Oyama-shi, Tochigi Prefecture Fujitsu Digital Technology Limited

Claims (5)

[Claims] 1. A layout method comprising a design step (S4-1) for designing a circuit and a layout step (S4-3) for performing layout based on the circuit designed in the design step (S4-1), The design process (S4-1) and the layout process (S
4-3) and the design process (S4-1).
The layout difficulty evaluation step (S4-2) for evaluating the difficulty of the layout of the circuit designed in 1. is performed, and the circuit is modified so that the circuit can be laid out according to the evaluation result of the layout difficulty evaluation step (S4-2). After that, the layout method is characterized in that the layout is performed in the layout step (S4-3). 2. A design data storage means (15, 45) in which design data of a circuit to be laid out is stored, and a layout difficulty based on the design data stored in the design data storage means (15, 45). Evaluation data creating means (13, 43) for creating evaluation data representing, and evaluation means for evaluating the degree of difficulty of the layout of the circuit based on the evaluation data created by the evaluation data creating means (13, 43) ( 13, 43), and a layoutability evaluation device. 3. The evaluation data creating means (13, 43)
2. The layoutability evaluation according to claim 1, wherein the number of terminals with respect to the number of basic cells forming a circuit is calculated as the evaluation data from the design data stored in the design data storage means (15, 45). apparatus. 4. The evaluation data creating means (13, 43)
Calculates, as the evaluation data, a ratio of cells excluding an area used for wiring from an area where a circuit is mounted based on the design data stored in the storage means (15, 45) in the design data. The layoutability evaluation device according to claim 1. 5. The evaluation means (13, 43) has a reference evaluation data storage means (17, 63) in which reference evaluation data that can be laid out in a past circuit is stored.
The evaluation data created by the evaluation data creating means (13, 43) is compared with the reference evaluation data stored in the reference evaluation data storage means (17, 63) to determine the layout difficulty evaluation. The layoutability evaluation device according to claim 1 or 2.