JPH033348A - Designing method for lsi - Google Patents

Abstract

PURPOSE:To realize the automatic design of a highly reliable LSI by estimating power consumption of each basic unit to be arranged in an LSI chip, and arranging each of the basic units in accordance with said power consumption so as to uniformize the power consumption distribution in the LSI chip. CONSTITUTION:In a designing method of LSI, a plurality of cells or function blocks called as basic units are arranged in an LSI Chip 7. In this designing method, a first step and a second step are provided. In the first step, the power consumption of each basic unit arranged in the LSI chip 7 is estimated, in accordance with a test pattern 4 for testing the LSI chip 7 and the generation frequency of the test pattern 4. In the second step, each of the above basic units is so arranged that the power consumption distribution in the LSI Chip 7 is uniformized, in accordance with the power consumption of each basic unit estimated by the first step. Thereby it can be prevented that a region where a lot of heat locally generates is formed in the LSI chip, so that a highly reliable LSI can be automatically designed.

Description

Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) The present invention relates to an LSI design method for designing an LSI in which a plurality of cells or basic units called functional blocks are arranged in an LSI chip. .

(Prior art) A ten-conductor integrated circuit (LSI) called a gate array or standard cell generally has three chips as shown in FIG.
A basic unit 31 called a cell 31a or a functional block (also referred to as a macro cell) 31b is placed on the cell 31a, and the cells are connected by aluminum (or polysilicon) wiring.

Such LSIs are usually designed automatically using a computer. Among them, cell 31a within 3° of the chip
A number of methods have been proposed for arranging the functional blocks 31b and wiring between them (rLsI-CAD (II)-LSI Layout CAD-J, Journal of the Institute of Electronics, Information and Communication Engineers, Vol.7
1. No. 1, pp. 80-87 (1988)). In these methods, emphasis has been placed on reducing the wiring length of each signal as much as possible and realizing the completed chip in as small an area as possible.

Furthermore, in recent years, some signals have been identified.
A design method has also been proposed in which each basic unit is arranged and wired between these basic units so that the delay due to wiring is within a predetermined limit value.

(Problems to be Solved by the Invention) As described above, in the conventional design method, the chip area and the delay of each signal are treated as important items, but other factors are hardly considered. I can't find anything that takes into account power supply-related wiring or chip power consumption. However, as process technology advances in the future, the minimum pattern width will become 0.8 μm to 0.5 μm (as a result, it will be necessary to prevent wiring stress and migration due to chip heat generation to improve LSI reliability. However, since conventional design methods lack such consideration, the following problems may occur.

In FIG. 4, cells with diagonal lines indicate a large number of cells 43.
This type of buffer cell 41 consumes a lot of power and generates a large amount of heat. Assume that these buffer cells 41 are arranged in a concentrated manner in a limited area within the chip 40 for the purpose of minimizing the wiring length as shown in FIG. 4 (this is quite possible with conventional design methods). Since this portion generates a high amount of heat, there is a risk that the surrounding wiring and the patterns within these buffer cells 41 may also melt and become disconnected. Distributing such buffer cells 41 as shown in FIG. 5 is preferable from the viewpoint of reliability of the LSI, although the wiring length becomes longer. However, in conventional design methods, in order to obtain such a placement, the designer has no choice but to intervene by modifying the placement or specifying a forced placement before placement, which lengthens the design period. It was also the cause of this.

The present invention has been made in consideration of the above circumstances, and is an LS that can automatically design a highly reliable LSI.
The purpose of this paper is to provide a design method for I.

[Structure of the invention]

(Means for Solving the Problems) The present invention provides a test pattern for testing an LSI chip and a A first step of measuring the power consumption of each basic unit arranged in the LSI chip based on the frequency of occurrence of this test pattern;
and a second step of arranging each basic unit so that the power consumption within the LSI chip is predicted to be uniform based on the power consumption of each basic unit predicted in the step.

(Function) According to the first method of constructing an LSI of the present invention configured as described above, the power consumption of each basic unit arranged in the LSI chip is reduced by r.Dl in the first step, and this P
In the second step, each basic unit is arranged so that the power consumption IH4 within the LSI chip is uniform based on the measured power consumption of each basic unit.

As a result, it is possible to prevent a locally high heat generation region from being formed within the LSI chip, and a highly reliable LSI can be automatically designed.

(Example) FIG. 11 shows a specific example of an apparatus for implementing the LSI design method according to the present invention. The device of this specific example includes a power consumption prediction means 1 which calculates the power consumption of each basic unit called a cell or a functional block in an LSI chip by ]-4Ill, and a power consumption prediction means 1 which calculates the power consumption of each basic unit called 1'711+ of each basic unit. Each basic unit is arranged in the LSI chip 7, and arrangement/wiring means for wiring between the basic units is provided.

The basic concept of power consumption prediction by the power consumption T measuring means 1 will be explained by taking a CMOS circuit as an example.

Power consumption P of an inverter, which is the basic unit of a CMOS circuit
Inv is known to be given by. Here, CL is the load capacity, DD is the power supply voltage, and f is the frequency of the input signal. A general CMOS circuit is realized as a modification of a CMOS inverter, so a CMOS cell (or functional block)
The power consumption is considered to be approximately proportional to the frequency of the input signal (ie, the number of changes in the human input signal per second). This way of thinking will give you a rough estimate, but it won't go far wrong. For each cell, this proportionality coefficient is measured in advance and registered in the library 3. Then, the power consumption prediction means 1 simulates the LS1 circuit using the connection data 5 equivalent to the given LS1 circuit based on the given test pattern 4, and calculates each cell (or functional block) in the LSI circuit. Calculate the number of times the input signal changes (per second).

The simulation method is well known, for example, the following reference: "Fundamentals of VLSI CAD", Kani et al., Chapter 4, p.
p96-99, Ohmsha (1983).

As a result, for the given test pattern T, the number of input signal changes f1j(C) is calculated for each cell C, so the power consumption P of the cell C due to this test pattern T
(T,) is J P (T,)-f (C)Xp (C)
(2) c, ITj and =l are calculated. Here p (C) is the change in input signal 1
This is the power consumption of cell C per cycle. This is calculated by performing a simulation for each test pattern T, and the final power consumption estimate Δl11directP of the cell C is determined. Here, n is the number of test patterns, and r is the degree of opening at which the test pattern T occurs. Na 3
J o, r, is 0≦rj≦1
．． satisfies rj-1.

Preliminary DI of power consumption of each cell C obtained in this way
The value P is stored in memory 6.

Next, the placement/wiring means 2 places and wires each cell or functional block based on the predicted value P of power consumption of each cell C stored in the memory 6 and the connection data 5. Here, the cells or functional blocks are arranged so that power consumption is uniformly distributed within the chip. An outline of this arrangement method will be described below.

This method is an improvement of the previously known MEN-CUT method. In the MIN-CUT method, as shown in FIG. 2, cell placement is determined by recursively repeating division within the chip 21. At the time of each division, cells within the region R to be divided are assigned to the small regions r1 and rl generated by the division, but at this time, this division line (this is called a cut line) 2
Assignment is determined while exchanging cells between the two small areas so that the number of signals that cross R5 is as small as possible, and the areas of the two areas r1 and R2 are approximately equal. In other words, the product of the area `` and the area r2 (total cell area) is A
(rl) and A(rl), and the power consumption of region " and region r2 (sum of cell power consumption in the region) is P (r
1).

As P (r 2 ), the following condition Δ(rl, rl) W-CI-IA (rl) −A
(rl) l+βφIP (r) −P (rl)
I≦δ (4) Allow the exchange of cells in area ``1 with cells in area r2 only within the range that satisfies ``I≦δ'' (4). Here, α.

β and δ are positive constants. In this way, not only the surface area of the inner region but also the power consumption can be divided almost in half.

When the algorithm of this embodiment is used, each time the chip is divided, the cells within the divided area are divided so that the area of each area and the power consumption within each area are as equal as possible after division. This is because in equation (4), the difference between the two regions is constrained to be as small as possible. As a result, as division is repeated and cell locations are determined, power consumption is gradually distributed evenly within the chip, reducing the risk of local heat generation.

Note that even if a constraint such as equation (4) is added, the quality of the arrangement is thickened (no deterioration occurs) because the division is performed so that the number of wires crossing the cut line 25 is as small as possible during division.

As explained above, according to this embodiment, it is possible to prevent a locally high temperature region from being formed in the LSI chip 7, and thereby it is possible to automatically design a highly reliable LSI. can.

In addition, in the above embodiment, explanation was given using a CMO3 circuit as an example, but in the case of an NMOS circuit, the power consumption calculation method is -
# Just change it, everything else should be the same. In the case of an NMOS circuit, power consumption occurs when the output of an inverter included in the circuit becomes 0, so basically the power consumption of the cell is uniquely determined for each input cover turn. Therefore, if the relationship between the human cover turn and the power consumption is described in the library 3, the power consumption can be calculated by performing a simulation in the same way as in the case of CMOS. It is also possible to calculate power by circuit simulation or the like without using logic simulation. However, the major drawback of this method is that it is time consuming, but the accuracy is good.

It is also possible to use other methods for arranging the cells. For example, by setting an attractive force on each cell that is proportional to the connection signal with other cells, and giving a repulsive force that is proportional to the product of the power consumption and inversely proportional to the distance, the equilibrium state in the given dynamical system can be changed. Another possible method is to obtain the arrangement.

〔Effect of the invention〕

According to the present invention, a highly reliable LSI can be automatically designed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a specific example of a device implementing the LSI design method according to the present invention, FIG. 2 is an explanatory diagram explaining the cell arrangement method according to the present invention, and FIG. 3 is a schematic diagram of an LS1 circuit. 4 and 5 are cell layout diagrams of LSI chips laid out by the conventional cell layout method. 1... Power consumption prediction means, 2... Placement/wiring means,
3...Library, 4...Test pattern, 5...
- Connection data, 6... memory, 7... laid out LSI chip.

Claims (1)

[Claims] LS for designing an LSI in which a plurality of cells or basic units called functional blocks are arranged in an LSI chip.
In the design method of I, the power consumption of each basic unit arranged in the LSI chip is predicted based on a test pattern for testing the LSI chip and the frequency of occurrence of this test pattern.
and a second step of arranging each basic unit so that the power consumption distribution within the LSI chip is uniform based on the power consumption of each basic unit predicted by this first step. An LSI design method characterized by: