JPH04102974A - Circuit logical description system - Google Patents

Abstract

PURPOSE:To reduce designer's misdesign and to improve design work by collecting the same sort of black box pins on a logical circuit diagram as a bundled pin. CONSTITUTION:Since the same sort of pins expressing the logic of a circuit on a logical circuit diagram are processed as a bundled pin, pins A0 to A15 can be expressed as on bundled pin BUSA having 16-bit width. Similarly, pins B0 to B15 and C0 to C15 can be respectively expressed as BUSB and BUSC. Although 48 pins corresponding to I/O pins should be written in a conventional method, the logic of a circuit can be expressed only by 3 pins in this method. Since a black box N is not expanded even when the number of pins in a box M is increased, the generation of an error can be suppressed even when the designer simultaneously designing both the boxes M, N.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit logic description method for expressing the logic of a circuit as a high-level description method on a logic circuit diagram.

[Conventional technology]

Conventionally, this type of circuit logic description method is based on 5. On a logic circuit, many pins of a black box that represent the logic of the circuit had to be defined individually.

FIG. 5 is a diagram showing an example of a logic circuit and a truth table in the conventional technology, in which (a) shows a black box and its pins, (
b) is a specific example of a truth table for a black box.

In FIG. 5 (a>, (b), the same type of pins that black box M has are AO~A15.BO~B15.Co-
With 16 lines for each C15, a total of 48 lines had to be written by human output. Therefore, even if there are pins of the same type, if the number of pins is increased, the black box M must be enlarged before the pins can be described.

[Invention or problem to be solved]

In the conventional '71@logic description method described above, all values must be individually defined for the pins of the fluff box on the logic circuit diagram. Therefore, as the number of pins on the box increases, the black hooks become larger, and at the same time, there is a disadvantage that it is easy for designers to make mistakes, contributing to design errors.

[Means to solve the problem]

The circuit logic description method of the present invention collects a plurality of bins and treats them as a pin when expressing the logic of a circuit on a logic circuit diagram, and uses table generation means to generate a table according to the logic from a black box. The table generating means is characterized in that it comprises an input device that inputs data, an arithmetic processing device that performs arithmetic processing on the input data, and an East Bin Analysis 1! that analyzes the East Pin! iM and an output device that outputs the calculation result, and furthermore, the east bin analysis mechanism searches for the black box from the logic circuit diagram, extracts a bin name from this black box, and extracts the bin name from the black box. The feature is that the east pin name is searched from inside, and the bundle pin is analyzed from this bundle pin name to extract the logic.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, this embodiment includes an arithmetic processing device 2 that performs arithmetic processing of data input from an input device 1 and sequence control with other mechanisms, and a bundle pin analysis 4f that analyzes bundled pins.
ii3, a data storage device 6 for storing data,
The bundle pin analysis mechanism 3 includes an output device 7 that outputs calculation results, and an east pin extraction @horizontal 4 that searches and extracts east pins.
It is composed of a logic extraction mechanism 5 that extracts the logic of the extracted bundle pins.

FIG. 2 is a flowchart showing the operation of FIG. 1.

First, step 11) searches for black boxes from the logic circuit diagram. Next, a pin name is extracted from the black box (Step 2), and a bundle pin name is searched from among these pin names (Step 3). Here, the East Bin name is enclosed by putting a number in parentheses ("<", "′>"') after the alphabetic character without indicating the hit width. For example, BUSA <0-15
If it is written as ＞, the pin called BUSA is]
It means 6 pins I/width, and if you break this pin apart, it will be BUSAO, BUSAI.

BUSA2. ~BUSA], 5, and so on.

At this time, a truth table is generated. In the table, pin names are defined at intervals according to the digit width of the pin.

The designer only has to write the values in this table. Next, the bundle pin is analyzed (step 14), and logic is extracted (step 15). Steps 11 to 15 are the functions of the east pin analysis mechanism 3 shown in FIG.

Next, FIG. 3 <a,> and (1) are diagrams showing a black box, its pins, and a truth table for the black box in one embodiment of the present invention.

In FIGS. 3(a) and 3(b), the pin of black box N is the east pin, and BUSA and BUSBBUSC each have a value of 1 to 16 bits.

In Figure 3, the same type of pin is treated as the east pin, and the fifth
Pins AO to A15 in the figure are 16-bit wide east pin B
It can be represented by one line as USA. Similarly, pins BO to B], 5
．． CO to C15 can each be expressed as BUSBBUSC. In other words, in the prior art, as described above, it was necessary to write 48 lines in total for input and output, but in this embodiment, even if the input and output are combined, the deviation in the description of 3 lines can be avoided in time. Further, even if the number of pins increases, as long as the number of pins of the same type as those described in this embodiment is increased, the number of pins can be easily increased by changing the bit width of the pins.

Next, the truth tables of the conventional example and the embodiment of the present invention will be explained. The truth table in FIG. 5(b) does not represent binary numbers and x (don't care), which can be 0 or 1.

On the other hand, the truth table in Figure 3(b) shows the binary number and ton 1.
In addition to Hecare×, it can also be expressed in hexadecimal. How to represent hexadecimal numbers will be explained using FIG. 4.

FIG. 4 is a diagram illustrating a specific example of the east pin in FIG. 3. As mentioned above, since the pin bundle BUSA has a width of 16 bits, it is expressed as BUSAO to BUSA15. In this embodiment, 4 bits represent one hexadecimal digit, so the 16-bit width is divided into 4-bit units and represented by 4 hexadecimal digits. Third
In the figure, BUSAO~3. BUSA4~7. BUSA8～
1.1. Each of BUSA12 to 15 is represented by one digit.

The value of BUSAO~3 is ] in hexadecimal.

The others are expressed in the same way, and the BUSA hexadecimal number is 4 digits IX
It is appropriate to express it as XX'''.

〔Effect of the invention〕

As explained above, the present invention has the advantage that by collecting pins of the same type in a black box on a logic circuit diagram and forming a bundle of pins, the designer's design errors can be reduced and the design can be improved. There is.

[Brief explanation of the drawing]

FIG. 1 is a Bux-Cock diagram that does not show an embodiment of the present invention, and FIG. 2 is a flowchart 1 showing the operation of FIGS.
, ) and (b) are diagrams that do not show the black hox, its pins, and truth table in one embodiment of the present invention, FIG. 4 is a diagram explaining a specific example of the bundle pin in FIG. 3, and FIG. a
) and (b) are diagrams showing an example of a logic circuit and a truth table in the conventional technology. ]...Input device, 2...Arithmetic processing unit, 3...Bundle pin analysis mechanism, 4...East pin extraction mechanism, 5...Logic extraction mechanism, 6...Data storage device, 7.Output Device, 1]・
...Blackhox search, 12...Pin extraction, 13
...Bundle pin search, 14...East pin analysis, 15...
Logic extraction, BUSA, BUSB, BUSC... bundle pin, M. N...Black Fox.

Claims (1)

[Scope of Claims] 1. A table generating means is provided which collects a plurality of pins and treats them as a bundle of pins when expressing the logic of a circuit on a logic circuit diagram, and generates a table according to the logic from a black box. A circuit logic description method characterized by: 2. The table generation means includes an input device that inputs data;
2. The circuit logic description method according to claim 1, further comprising: an arithmetic processing device that performs arithmetic processing on the input data; a bundled pin analysis mechanism that analyzes the bundled pins; and an output device that outputs the calculation results. 3. The bundle pin analysis mechanism searches the black box from the logic circuit diagram, extracts a pin name from this black box, searches for a bundle pin name from among the pin names, and extracts a bundle pin from the bundle pin name. 3. The circuit logic description method according to claim 2, wherein the logic is extracted by analyzing.