JPS62182920A - Arithmetic unit for tag architecture - Google Patents

Abstract

PURPOSE:To couple a tag and a data field in a single machine cycle by providing internally a logic circuit which receives information including a tag value, information including the data field, and tag and field designating information as inputs and couples them logically to generate data with the tag. CONSTITUTION:AND circuit 6 operates AND at every 4 bits of a tag word 2 and those of a field mask 4, and an AND circuit 7 operates AND between 4 bits of a data word 3 and those of the field mask 4 inverted by a NOT circuit 8. Consequently, the output 9 of the AND circuit 6 has the tag value in a higher order N-bit position and has all '0' in a lower order N'-bit position, and the output 10 of the AND circuit 7 has the data field in the lower order N'-bit position and has all '0' in the higher order N-bit position. An OR circuit 11 operates OR at every bit of the output 9 of the AND circuit 6 and that of the output 10 of the AND circuit 7. As the result, data 5 with the tag which has the tag value in the higher order N-bit position and has the data field in the lower order N'-bit position is obtained as the output of the OR circuit 11.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a tag calculator, that is, a type of computer in which each piece of data has a tag indicating its attribute, and particularly relates to an arithmetic unit for the tag calculator.

[Background of the invention]

In a Neumann computer, the attributes of data (numeric or character, binary or decimal, fixed-point or floating-point notation, etc.) cannot be known from the data itself, but are determined unilaterally by the program. . For example, data specified as an operand of a decimal addition instruction is processed as a decimal number, regardless of its substance. Therefore, in a Neumann-type computer, separate instructions must be prepared for each data attribute for one type of I-arithmetic operation (for example, addition), and these separate instructions must be used correctly in a program. . on the other hand,
In a program written in a high-level language, the attributes of variables (data) are revealed by type information belonging to the variables themselves.

The gap between this structure of a program in a high-level language and the above-mentioned architecture of a Neumann computer places a heavy burden on software creation.

One of the means for compensating for the above-mentioned drawbacks of the Neumann type computer is the tag architecture.

In a tag architecture, each data unit (eg, a word) in a storage device has a field for information indicating attributes of the data, and this field or its contents is called a tag. A computer with a tag architecture, that is, a tag calculation, has many features that a Neumann type computer does not have. For example, the instructions for the tag calculator may be generic (g6neric). There is no need to prepare a separate operation instruction for each attribute of data, and a single type of operation instruction can perform operations on data of all attributes by selecting the execution process according to the analysis result of the operand tag. can be controlled. Descriptions of general tag architectures can be found, for example, in G., J.

Written by Myers” Advances in (:o
Mputer Architecture, 5eco
nd Edition” John Wiley &
5ons, 1982. Discussed on pages 58-67. The tag architecture is particularly useful for processing the LISP language, and many LISP-only machines have adopted it (Information Processing Vot., 23 A.
8, August 1982, pp. 757-772)
.

The functions required to realize a tag architecture include separating tags and data bodies, analyzing tags, and combining tags with calculation results. The tag architecture in some traditional LISP machines is:

In order to efficiently separate the tag and the data body, AL
A mask/selection circuit for tag processing is provided before the U. However, special hardware is required to efficiently combine tags with calculation results.

No report found. Joining tags to calculation results as normal A
To achieve this using LU's two-person logical combination mechanism, it is necessary to extract the part that should become a tag field from information including tag values, extract the part that should become a data field from the calculation result, and extract the part that should become a data field from the information including the tag value. The combination of fields requires three passes through the ALU, or the execution of 93 instructions.

[Object of the Invention] An object of the present invention is to provide a mechanism that can efficiently perform the function of combining tags and data bodies necessary for tag architecture.

[Summary of the invention]

The present invention is characterized by receiving as input information including a tag value, information including a data body, and field specification information indicating each bit field of the tag of tagged data and the data body, and logically combining them. The point is that a logic circuit that generates tagged data is built into an arithmetic unit (ALU).

This allows the process of combining the information containing the tag value, the information containing the data body, and the field specification information to form tagged data to be performed during the same machine cycle as the operation to obtain the data body, or in an additional single machine cycle. can be completed in several machine cycles.

[Embodiments of the invention]

FIG. 1 shows an example of a logic circuit for coupling a tag to a body of data (hereinafter referred to as tag coupling circuit) suitable for use in the present invention. The tag combining circuit 1 includes tag words 2 . Data word 3 and field mask 4 are input to terminals T and D.
and M, respectively, and generate a tagged data word 5 at output terminal TD. Tag word 2 is a word containing a tag value.

In this example, the tag value occupies the upper N bits of the tag word. Data word 3 is usually a word resulting from some operation, in this example.

The lower N' bits are occupied by the data body. The word length is N+N' bits. field mask 4
is placed in the bit position corresponding to each bit in the tag field (upper N bits in this example) of tagged data 5.
1'', and the remaining pit positions, that is, the pit positions corresponding to each bit in the data field of the tagged data 5 (lower N' pits in this example), have °0''.

The AND circuit 6 generates a bitwise AND of the tag word 2 and the field mask 4. The AND circuit 7 generates a bitwise AND of the data word 3 and the field mask 4 inverted by the NOT circuit 8. Therefore, the output 9 of the AND circuit 6 includes the tag value in the upper N bit positions, all 1'0'' in the lower N' bit positions, and the AN
The output 10 of the D circuit 7 includes the data body at the lower N' pit positions and all "O's" at the upper N pit positions. The OR circuit 11 outputs the output 9 of the AND circuit 6 and the output 1 of the AND circuit 7.
Generates a bitwise OR of 0s. As a result, the top N
Tagged data 5 having the tag value at the pit position and the data body at the lower N' bit position is obtained as the output of the OR circuit 11.

The usage of 11'' and at O'' in the field mask 4 may be reversed to that in FIG. In that case, the NOT circuit 8 is placed at the input circuit of the AND circuit 6. If the field mask 4 is held in a group of flip-flops and the false outputs of these flip-flops can be used, the NOT circuit 8 can be omitted. Furthermore, instead of AND-OR logic, an equivalent logic circuit may be constructed using a NOR circuit or a NAND circuit.

FIG. 2 shows a first embodiment of the invention. Computing unit (
The ALU (ALU) 20 has a block (ALB) 21 that performs functions corresponding to those of a conventional ALU, and a tag combining circuit 1 shown in FIG.

Data used as operands for general arithmetic and logic operations are supplied from ALU input A and ALU input B to ALB 21 as inputs 22 and 23. The output 24 of ALB 21 is sent to tag combining circuit 1 as data word 3 in FIG.

The tag word 2 and the field mask 4 are supplied to the tag combining circuit 1 from their respective sources via their own paths. The output 5 of the tag combination circuit 1 is sent out as an ALU output. ALU input A, ALU input B, ALB output 24,
The bit widths of the ALU output, tag word 2, and field mask 4 are all the same.

According to this embodiment, processing from inputting operands to outputting tagged data is accomplished in a single machine cycle by a single instruction.

The time delay caused by the insertion of the tag binding circuit is negligible. If you want to obtain the calculation result 24 of the ALB 21 as it is as the ALU output, the bit pattern of the field mask 4 should be the same as the pattern when the tag field length is 0'' (all 1°0'' in the circuit shown in Figure 1). Set.

FIG. 3 shows a second embodiment of the invention. The ALU input A is sent to the ALB 21 as the first human power 22, and
It is sent to the input terminal T of the tag combination circuit 1. ALU input B
is sent to the ALB 21 as the second human power 23 and also to the input terminal of the tag combination circuit 1. 3rd AL
The U input is a field mask 4 and is sent to the input terminal M of the tag combination circuit 1. The output 24 of the ALB 21 or the output 5 of the tag binding circuit 1 is selected by the selector 31 and
It becomes LU output. The selector 31 is switched by a signal from an instruction execution unit (IEU), not shown.

For normal two-man operation, operands are supplied from ALU input A and ALU input B, and the selector 31
Select output 24 of 21. The combination of the tag and the data body is performed in the form of a three-person operation. The tag word is supplied on the ALU input input, the data word is supplied from ALU input B, and at the same time the field mask 4 is supplied as the third ALU input. The selector 31 selects the output 5 of the tag combination circuit 1. The field mask is supplied from the ALU input input B and the tag word or data word is
To be supplied as a third manpower.

May be deformed.

FIG. 4 shows a third embodiment of the invention. The ALU input is sent to the ALB 21 as the first human power 22, and
It is sent to the input terminal T of the tag combination circuit 1. ALU input B
is sent to the ALI 321 as the second human power 23 and also to the input terminal M of the tag combination circuit 1. ALB2
The output 24 of 1 is sent to the selector 41 and also to the data latch 43 via the gate 42, and the output of the data latch 43 is given to the input terminal of the tag combination circuit 1. The output 5 of the tag combination circuit 1 is sent to the selector 41. The output of the selector 41 becomes the ALU output. Selector 41 and gate 42 are controlled by signals from an IEU (not shown).

For normal operations, selector 41 selects output 24 of ALB 21. At this time, if the instruction specifies saving of the operation result, the gate 42 opens and the output 2 of the ALB 21
4 is held in the data latch 43. When a tag binding instruction is subsequently executed, the tag word is provided on the ALU input input and the field mask is provided on the ALU input B. According to the field mask input, the tag combining circuit 1
The tag word input and the data in the data latch 43 are combined to output tagged data 5. The selector 41 is the IEU
According to the signal from the ALU, the output 5 of the tag combining circuit 1 is
Select as output.

In the second and third embodiments, after the calculation result is obtained, the combination of the calculation result and the tag is performed in a single machine cycle.

FIG. 5 shows a fourth embodiment of the invention. The ALU input signal is sent to the ALB 21 as an input 22, and is also sent to the selector 51. The selector 51 is the tag combining circuit 1
input terminal T or a signal line to the field mask register 52.

The output of the field mask register 52 is given to the input terminal M of the tag combination circuit 1. ALU input B is ALB
21 as an input 23 and also to the input terminal of the tag combination circuit 1.

The selector 53 selects the output 24 of the ALB 21 or the output 5 of the tag combination circuit 1 as the ALU output.

Selectors 51 and 53 are controlled by signals from an IEU (not shown).

For normal operations, selector 53 selects output 24 of ALB 21. The selector 51 is normally kept in the cut-off state. In this example.

An instruction is provided to set the field mask in the field mask register 52. When this command is executed,
The field mask is placed on the ALU input input and selector 5
1 selects the signal line to the field mask register 52, and as a result, the field mask is set in the field mask register 52. Thereafter, at any time when the tag binding instruction is executed, the G word is provided on the ALU input input and the data word is provided on the ALU input B. At the same time, the selector 51 selects the signal line to the input terminal T of the tag coupling circuit 1, and the selector 53 selects the signal line to the input terminal T of the tag coupling circuit 1.

Output 5 of tag combining circuit 1 is selected. As a result, the input tag word and the input data word are combined according to the field mask in the field mask register 52, and the resulting tagged data 5 is sent as the ALU output. A
It may be modified such that the LU input B is switched between the field mask register 52 and the input end of the tag combination circuit 1.

In this fourth embodiment as well, the combination of tag and data body is accomplished in a single machine cycle. However, prior to that, it is necessary to set a field mask in the field mask register 52. However, the length of the tag field, ie the dot pattern of field mask 4, is not frequently changed. therefore,
Execution of instructions that set field masks is rare;
The resulting decrease in processing efficiency is negligible.

Regarding the second to fourth embodiments, the tag coupling circuit 1 is
Although it is described as being completely separated from the LB 21, in reality, the ALB 21 and the tag binding circuit 1 may share some circuits.

〔Effect of the invention〕

According to the present invention, one of the essential functions of tag architecture, the binding of tags and data bodies, is accomplished in a single machine cycle. Moreover, the addition of the necessary hardware hardly results in an extension of the machine cycle. Therefore, it is remarkable that the present invention contributes to speeding up the tag calculator.

[Brief explanation of drawings]

FIG. 1 is a logic circuit diagram of an example of a tag combining circuit used in the present invention, and FIGS. 2 to 5 are block diagrams of different embodiments of the present invention.

Claims (1)

[Claims] 1. Receiving as input information including a tag value, information including a data body, and field designation information indicating each bit field for the tag and data body of tagged data to be generated; An arithmetic unit for tag architecture, characterized in that it includes a logic circuit that logically combines them to generate tagged data. 2. In claim 1, the field designation information includes a part indicating a bit field for a tag and a part indicating a bit field for a data body, one of which is all "1" and the other is all "0". The tagged data generation logic circuit has a bit pattern, and the tagged data generation logic circuit includes a first logic stage that generates a bit-by-bit AND of information including the tag value and one of the field designation information and its negation; a second logical stage that generates a bitwise AND of the other of the negation and the information including the data body; and a third logical stage that generates a bitwise OR of the outputs of the first and second logical stages. An arithmetic unit for tag architecture, which has: 3. In claim 1 or 2, the tagged data generation logic circuit receives as input the result of an operation other than tagged data generation, information including the tag value, and the field designation information. Computing unit for tag architecture. 4. The arithmetic unit for tag architecture according to claim 1 or 2, wherein the arithmetic unit has three inputs, and the tagged data generation logic circuit receives the three inputs as its inputs. 5. In claim 1 or 2, the arithmetic unit has two inputs, and further includes an information holding circuit for storing results of arithmetic operations other than tagged data generation, and the tagged data The generation logic circuit is an arithmetic unit for tag architecture that receives the two inputs and the output of the information holding circuit as its inputs. 6. In claim 1 or 2, the arithmetic unit has two inputs, and further includes an information holding circuit for holding the field designation information supplied from one of the two inputs. An arithmetic unit for tag architecture, wherein the tagged data generation logic circuit receives the two inputs and the output of the information holding circuit as its inputs.