JPH05143677A - Device and method for logical design - Google Patents

Abstract

PURPOSE:To improve descriptive capability and to accelerate the generation of logic by reducing the amount of description by using an abbreviated description method without describing the logic of all input conditions. CONSTITUTION:An input device 1 is a device to fetch logically designed logic information, and includes a logic input part. An arithmetic processing part 3 performs the arithmetic processing of the logic information inputted from the input device 1 by using a data description device 4, and delivers it to a logic developing part 5. Decoding processing by the abbreviated description method is performed at the logic developing part 5, and a result is delivered to a logic conversion part 6, and optimization for logic, etc., is performed, then, the logic is synthesized. In such a case, a function is divided to express the logic on a table. Thence, the logic is expressed on the table, however, abbreviated expression is used for that purpose. After that, the abbreviated expression is developed and processed. Final logic information is generated by inputting generated information, and the synthetic processing of the logic is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic designing apparatus and method, and more particularly to a logic designing apparatus and method for simplifying logic expression in a high level tabular format.

[0002]

2. Description of the Related Art Conventionally, in this type of logic design, in order to express logic by a high-level Boolean expression, etc., all the conditions that all inputs can occur are described, and an output pattern for each condition is described. Had to be expressed.

Even when a plurality of input conditions always output the same output, all the input conditions must be described and the output pattern must be shown.

In particular, in language expressions such as Boolean expressions, it is difficult to find the leaked condition immediately by hand, and due to the nature of the Boolean expression, a batch output condition for n input conditions. There was no way to express, and it was not possible to omit it to express logic.

[0005]

In the above-described high-level logic expression in the conventional logic design, all the input conditions are identified and described even if the conditions do not affect the operation, for example, when the outputs are all zero. It is necessary, and the amount of description will increase.

Similarly, in the state transition expression, it is necessary to identify all the conditions even if the conditions do not operate or the output states are the same.

Therefore, it is necessary to find a description method that expresses logic in a tabular format so that it can be expressed collectively when the outputs are the same.

An object of the present invention is to provide a logic designing apparatus and method in which a table format that can be expressed by organizing logic is used as a logic expression means, and output patterns are collectively written so that it is not necessary to identify all input conditions. To provide.

[0009]

SUMMARY OF THE INVENTION The present invention is directed to an input device for taking in logical information to be logically designed, an arithmetic processing unit for arithmetically operating the logical information input from the input device, and a data storage device for storing the arithmetic result. , A logic conversion unit that converts the logic of the state transition table, and the deciphering process of the abbreviation for the logic information from the arithmetic processing unit, and performs optimization based on the logic conversion of the state transition table in the logic conversion unit. And a logic expansion unit for synthesizing logic.

Further, according to the present invention, in a logic design method using a state transition table as a logical expression means of logic design, a function is divided for expressing on the logic and the state transition table, and the logic is omitted. It is characterized in that it is described in the state transition table, and the information created by expanding the abbreviated expression of the logic is included in the state transition table to create the final logical information and perform the logic synthesis.

[0011]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In FIG. 1, an input device 1 is a device for fetching logic information to be logically designed, and includes a logic input section.
The arithmetic processing unit 3 arithmetically processes the logical information input from the input device 1 using the data storage device 4, and passes the logical information to the logical expansion unit 5. The deciphering process of the abbreviation is performed in the logic expansion unit 5, and the result is passed to the logic conversion unit 6 to optimize the logic.
Perform logic synthesis.

FIG. 2 is a processing flow chart showing the operation.
First, the functions are divided in order to express the logic on the table (step 21). Next, the logic is described in the table (step 22). In this case, the shorthand notation as used in FIG. The process up to this point is a manual operation, and then the abbreviation is expanded (step 23). This is to save the omission of expressions as well as the abbreviated notation, whereby abnormal operation can be prevented to some extent.
Next, the created information is included, final logic information is created (step 24), and logic synthesis processing is performed (step 25).

FIG. 3 is a summary of the results of the conventional method and the present invention. FIG. 3 (a) is a Boolean expression of a certain logic (+ ... OR, * ... AND). .. If this is used as a truth table, it becomes as shown in FIG. 3B, but if the abbreviation method using don't cares (×) is used, the description amount decreases as shown in FIG. 3C. For example, if the pattern (pattern N0.1-2) of the output (0, 1) is omitted in FIG. 3C, the output will be anything. Therefore, the output other than those defined in the table as shown in FIG.
By providing the expression "s", an ambiguous definition can be avoided.

"Others" can be created without manually expanding all the patterns of the logic of FIG.
Logic for logic synthesis is created using the method of FIG. First,
The pattern NO. Of FIG. Create a pattern that does not represent the pattern of 1 by paying attention to each pin. (0,
Since the pin of (1, ×) is “×”, nothing is done and the next b pin is focused and “0” that does not include “1” is obtained. (E) of (0,0,
X) pattern is determined. Next, it is '1' that the a pin is not included. When pin a becomes '1', pin b, c
Since the pin can take any value,
The pattern of ×, ×) is obtained.

Now that the pattern 1 in FIG. 3D has been processed, the same operation is performed for the patterns 2 and 3 to create a group for each pattern. This is the table of FIG. From this, a pattern that has an inclusive relationship in the brute force of the patterns between the two groups is obtained.
For example, in group 1 and group 2, FIG.
The relationship of ∩ in (e) is established in the pattern of (0, 0, ×). The result and the inclusion pattern of group 3 are similarly obtained (FIG. 4 (g)).

The result derived here is the portion A of FIG. As can be seen from FIGS. 3C and 3D, the omitted pattern can be obtained at high speed and clearly without increasing the description amount.

Compared with the conventional logical representation shown in FIG. 3A, in FIG. 3D of the present invention, the logic is organized and clear,
There are merits such as ambiguous definitions and lack of missing patterns.

FIG. 6 shows the notation of the present invention in the state transition table, and FIG. 7 shows the logic expansion procedure of the abbreviated notation. Although it is similar to that shown in FIGS. 3, 4, and 5, the group is created in the same current state, and the inclusion relation with a group having a different current state is not obtained.

[0020]

As described above, according to the present invention, when the logical expression method of the logical design is expressed in a high-level table format, the description amount is expressed by using the abbreviated notation without describing the logic of all input conditions. By reducing the number of steps, the descriptiveness is improved and the logic is created faster, which has the effect of facilitating logic design.

[Brief description of drawings]

FIG. 1 is a block diagram showing functions of an embodiment of the present invention.

FIG. 2 is a process flow chart showing the operation of the present embodiment.

FIG. 3 is a diagram showing a conventional high-level logic design expression example and a notation example in the present invention.

FIG. 4 is a diagram showing a procedure for obtaining final logic for logic synthesis from the notation of the present invention.

5 is a diagram showing the final pattern passed to the logic synthesis of step 25 of FIG.

FIG. 6 is a diagram showing a notation of the present invention in a state transition table.

FIG. 7 is a diagram showing an expanded example of an abbreviation for the state transition table of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 input device 2 output device 3 arithmetic processing unit 4 data storage device 5 logical expansion unit 6 logical conversion unit 21 to 25 processing steps

Claims (2)

[Claims] 1. An input device for fetching logical information to be logically designed, an arithmetic processing unit for arithmetically operating the logical information input from the input device, a data storage device for storing the arithmetic result, and a logic of a state transition table. A logic conversion unit for conversion, and a logic expansion unit for performing logic deciphering processing on the logic information from the arithmetic processing unit, optimizing based on the logic conversion of the state transition table in the logic conversion unit, and synthesizing logic. A logic design device having: 2. A logic design method using a state transition table as a logical expression means of a logical design, wherein a function is divided to express a logic on the state transition table, and the logic is converted into a state transition table using an abbreviated expression. A logic design method characterized by describing, creating the final logical information by incorporating the information created by expanding the abbreviated expression of the logic into the state transition table, and performing the logical synthesis.