JPH02130645A - Truth table logical simulation method - Google Patents

Abstract

PURPOSE:To directly execute logical simulation at high speed by providing a step to convert input information to a truth table and a step to calculate a part to be the value of 0 or 1. CONSTITUTION:In the step to convert the input information to a logic circuit model expressed in the truth table, for the logical value 1 of the input information, 10 and 0 and the value of 01, 0 or 1 are converted to 00. An AND with the respective sets of certain input values is obtained and compared with the original input information. Accordingly, it can be regarded that the value of 0 or 1 can be coincident with the values of 0 and 1 and the value of 0 or 1. Next, in the step to calculate the part to go to the value of 0 or 1, when the truth table is changed, the OR is obtained for the sets of output values. Thus, the calculated result of the part, which can simultaneously obtain the logical value 1, logical value 0 and the logical value 1 or 0 and the value of the logical value 0 or 1, goes to 11 and this result can be outputted as the value of 0 or 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic design verification system, and more particularly to a logic simulation method for a logic simulator capable of simulating a truth table as a model of a logic circuit.

[Conventional technology]

In a logic simulation system, in addition to the binary value of 0.1, a value that can be either 0 or 1 (don't care value)
I searched for a method for handling truth tables containing , but I can't find anything at the moment. Regarding related methods of this type, please refer to the 23rd NCM/IEE Design Automation Conference 6.
March 29th-July 2nd, 1986, pp. 354-3
59 pages (ACM/IEEEE, DESIGN, AUT
OMATION, CONFERENCE, JUNE
29-JULY2.1986. pp354-pp35
9).

According to this method, the truth table is converted into a pooled expression for processing. In this case, it is assumed that the pool expression has already been optimized.

[Problem to be solved by the invention]

Model the matching of logic circuit functions using a truth table,
When performing a logic simulation of a logic circuit using a truth table, when the truth table includes a binary value of 0.1 or any value of 0.1, the conventional technology expands the truth table in a pooled manner. A logical simulation is performed, but it is assumed that the optimization of the pool formula has already been done manually. When creating a pool expression for a general truth table that includes values that can be either 0 or 1 in addition to 0 or 1, a process called optimization of the pool expression is essential. Since pool optimization is generally an NP-complete problem, there is no guarantee that optimization using simple rules can cover all cases.

The purpose of the present invention is to enable high-speed direct logic simulation without converting a truth table containing values that can be 0, 1, or 0.1 to other models such as pooling or gate expansion. be.

[Means to solve the problem]

The above purpose is to set a value that can be either 0, 1 or 0, 1 (do
input information to the truth table including 0, 1, don't care) prepared in advance.
converting the input information for the truth table in order to quickly check the match with the set of input values of the truth table containing re, and each set of matched input values of the truth table or This is achieved by calculating the portion that should be the don't care value for one or more output values corresponding to .

[Effect]

The step of converting the input information into a logic circuit model represented by a truth table may include, for example, converting the logical value of the input information from 1 to 10.
Convert O to 01, and convert a value that can be 0 or 1 to Oo. By doing this, in advance, the logical value 1 in the truth table is converted to 10, 0 is converted to 01, and the value that can be 0 or 1 is converted to 11, and the logical AND is performed with each set of input values and compared with the original input information. A value that can be O or 1, and 0, 1. and values that can be 0 or 1 can be considered to match 6. If there are multiple sets of input values of the truth table that are considered to match in this way, multiple output values corresponding to them. For example, if the truth table has been converted as described above, the logical value 1 can be calculated by calculating the logical sum of each set of output values. and logical value O1 The calculation result of the part that can take the logical value 1 or 0 and the logical value 0 or 1 at the same time is 11, which can be output as a value that can be 0 or 1.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. Second
The figure shows a hardware configuration for implementing the invention.

Character terminal device 21 or other suitable input device (keyboard, card reader, graphic terminal device, etc.) 22
is used to input a logic circuit model and input data to the logic circuit model. The processing device 23 processes the input data according to the function of the logic circuit model to generate logic simulation results. This logic simulation result is output by an output device (printer, plotter, etc.) 24.

Figure 3 (a) shows the truth table model. The truth table model consists of three sets of input values (input part) and the corresponding two
It consists of areas that store two sets of output values (output parts), II, I2. This is an example of a model of a logic circuit that receives three input values I3 and outputs two values 01 and 02. This model will be used in the following explanation. FIG. 1 shows o, ■ as an embodiment of the present invention.
In addition, a method for directly simulating a truth table containing values that may be 0 or 1 at high speed is shown. In step 11, input information is converted so that a match with a set of input values in the truth table can be checked. Now, Il, I2 in FIG. 3(a). I
An example of the conversion rule when a value of 1, 0.1, or 0 is input to 3 will be explained with reference to FIG. The original logical value is expressed as a 2-bit binary number, where 1 is 10. O is 0
Values that may be 1.0 or 1 are expressed as 00. Furthermore, three pieces of input information are combined into one 6-bit binary number. From now on, this 6
The number of bits is called a key, and the value, which can be O or 1, is represented by the symbol fist. Correspondingly, the actual form of the above truth table is based on the conversion rule shown in Figure 4 for each logical value, that is, the logical value 1
10.0 is applied as 01, and fist as 11. The input value set is converted into a 6-bit binary number and the output value set is converted into a 4-bit binary number in advance.

Figure 3(b) shows the truth table after conversion corresponding to Figure 3(a).
). Combining input values into one number allows for faster matching checks.

FIG. 12 shows a part that determines whether a fist is included in the set of input values. This is because if the set of input values does not include an umbrella, there will be at most one match with the area in which the set of input values of the truth table is stored, so that subsequent processing can be simplified.

If the input value includes a value that may be 0 or 1, a match check is performed in step 3 of FIG. 1. The method is shown in Figure 4 and Figure 3(b).
This will be explained using an example. The AND of each key and each bit is calculated sequentially from the top of the area storing the set of input values shown in FIG. 3(b). If the result is equal to the key, it is considered a match. In Figure 3(b), the logical product of the first and second rows and the key in Figure 4 is (1001,00)z, which is equal to the key, so it is considered a match. Here, a match is a binary number. It does not mean that the converted numbers themselves match.

Otherwise, the value that can be O or 1 here is a value that can be considered either 0 or 1, and when referring to the truth table, it must be considered to match any logical value. .

Fig. 1 14 is 0 or 1 in Of, 02 in Fig. 3 (a).
However, there is no output that takes a good value, but the step is to find out. This is done by calculating the logical sum of the output values of the first stage and second stage of FIG. 3(b), which were determined to match according to FIG. 13. That is, in FIG. 3(a), 02 can be either 0 or 1. Correspondingly, the logical sum of the output values of the first and second stages in FIG. 3(b) is (1011)! So, (10)2
1, (01)2 as Ol (11)2 or (00)Z
By considering it as a skewer, 01 = 1. ．． 02=Umbrella and the correct value is calculated. Note that the value obtained as described above is not limited to a value that may be 0 or 1, but can also be treated as an uncertain value.

Figure 1 16 shows the steps required when the truth table is not closed for all possible combinations of input values, and there is no match even after trying to check for a match across all stages of the truth table. In this case, a default value prepared in advance by 110 in FIG. 1 is set as the output value.

Next, a case where the input value does not include a value that may be 0 or 1 will be described. The steps 17 and 18 in FIG. 1 are used to check the consistency of each stage of the truth table. If there is a match even once in the process, the set of output values is output as shown in FIG. 19, and the subsequent match check is discontinued. This prevents unnecessary truth table processing.

111 in FIG. 1 is a step in which the output value is arranged in a format to be passed to a logic circuit model other than the truth table.

〔Effect of the invention〕

According to the present invention, a truth table corresponding to the functions of several to several dozen gate elements can be processed at high speed.

According to calculations, it is possible to speed up the process by about five times compared to performing a logic simulation of the number of gate element models corresponding to the functions of the truth table. Furthermore, unlike in the past, it is no longer necessary to expand to a pool formula or convert to a combination of gate element models, which helps reduce the number of man-hours required to create a model for logic simulation of a logic circuit. Furthermore, since the format of the truth table remains almost as drawn by the designer, it becomes easier to understand the logic circuit model, and it also helps to prevent erroneous descriptions.

[Brief explanation of drawings]

FIG. 1 is a flowchart showing an example of the process of logically simulating a logical circuit model expressed by a truth table that may include values of 0 or 1 using the present invention;
FIG. 2 shows an example of the hardware configuration for executing a logic simulation system including the present invention.
The figure shows an example of a logic circuit model expressed as a truth table.
The figure shows an example of a conversion rule for input values to the logic circuit, and an example of a rule for converting a truth table into a format to be actually stored in a processing device. 11... Step of converting input value into binary number, 13.
... Comparison step between input value set and truth table, 14...
Step of calculating a portion of the set of output values that can be either O or 1, 21.22... Input device, 23...
Data processing device, 24...output device. Old Prisoner Tomoe

Claims (1)

[Claims] 1. It has an input device, an output device, and a data processing device connected to the input device and the output device, and as a model of a logic circuit, in addition to the binary values of 0 and 1, the input value or the value that can be either 0 or 1. In a system that can perform logic simulation of a logic circuit that can handle a truth table that has an output value, in order to quickly check the coincidence with a set of input values in the truth table, a step of converting input information, and a portion that should be either 0 or 1 for one or more output values corresponding to each set of matched input values of one or more truth tables; A truth table logic simulation method comprising the step of calculating .