JPH04100357A - Pi/4 shift qpsk delay detection demodulator - Google Patents

Abstract

PURPOSE:To reduce the deterioration in the demodulation characteristic due to fluctuation of a local frequency by obtaining an offset of the local frequency through the 8-multiple of a base band signal, applying low pass filtering and amplification to the offset and using the result as a control variable for a local frequency generating means. CONSTITUTION:Two base band signals demodulated by a delay detection means 3 are multiplied by a multiple of 8 at an 8-multiple means 4 to obtain a phase difference (local frequency offset) information, and the information is fed back to a local frequency generating means 1 by a loop filter means 6 to form a phase locked loop thereby controlling the local frequency generated by the local frequency generating means 1. Thus, the deterioration in the demodulation characteristic due to fluctuation of the local frequency of the delay detection demodulator is reduced.

Description

[Detailed Description of the Invention] [Summary] Regarding a differential detection demodulator using a π/4 shift QPSK modulation method, the purpose of this invention is to reduce deterioration of demodulation characteristics due to fluctuations in the local frequency of a receiver. a local frequency generating means that generates a variable local frequency according to a control amount; a frequency converting means that receives a signal modulated by a predetermined code and converts the frequency by mixing it with the local frequency; and the frequency converter. π/
In the 4-shift QPSK delay detection demodulator, the baseband signal is multiplied by 8 to obtain the offset of the local frequency, and the offset is low-pass filtered and amplified, and the control amount of the local frequency generation means is controlled. and loop filter means for supplying the filter.

[Industrial Application Field] The present invention relates to a delayed detection demodulator using a π/4 shift QPSK modulation method.

With the diversification of information services in recent years, digitalization of communications has become essential, and this trend has also extended to the field of mobile communications. Digital mobile communications must function under poor propagation environments that include fading, etc.
There is a need to develop technology suitable for mobile communications.

As a demodulation method for the PSK modulation method, which is one of the modulation methods for digital communication, synchronous detection is used in fixed station communication such as Eihin communication. Synchronous detection has excellent static characteristics (when there is no fading), but in environments where reception is interrupted intermittently due to high-speed fading, carrier wave recovery becomes difficult and demodulation characteristics deteriorate significantly, making it difficult to use in mobile communications. is not suitable for Therefore, delayed detection, which does not require carrier wave recovery, is considered to be promising.

In particular, the π/4 shift QPSK modulation method improves the amplification efficiency that occurs due to the reduction of nonlinear distortion that occurs when the phases of successively received symbols differ by 180 degrees in the power amplifier circuit of the demodulator of the QPSK modulation method. It is used to solve the problem of the drop in signal strength, and the phase of the symbol in QPSK modulation is shifted by π/4 for each symbol, so that the phase of consecutively received symbols does not differ by 180 degrees. This is what I did.

[Prior art and problems to be solved by the invention] First, π/4 shift QPSK modulation will be explained. First of all,
The input code x 1 = 0.1.2.3 is subjected to Gray code conversion, which is superior in terms of error rate. Letting the signal after Gray code conversion be δ(xt), δ(xt)=0.1.3.2. Next, since it is differential detection, it is necessary to transmit the signal by adding information to the phase difference of the modulated waves, so differential encoding is performed on the modulator side. If the signal after differential encoding is yi, then Vi= Vi-++δ(xt)
(1) Then, put this y into l time slots with π
Carrier wave angular frequency ω whose phase changes by /4. When orthogonal modulation is performed, the π/4 shift QPSK modulated wave R(t) can be expressed as the following equation.

R(t)=cos(ωet−θi+Vix/2−
x /4) (2) θa=iπ/4 (i=
o~7) (3) FIG. 5 shows the configuration of a conventional delay detection demodulator using the π/4 shift QPSK modulation method. In FIG. 5, 10 is an antenna, 12, 13 . and 14 is a mixer, 15 and 16
is a low-pass filter, 17 and 18 are delay circuits (π/
19 is a timing recovery circuit (BTR, bi
20 is a code identifier, and 31 is a local oscillator. The local oscillator 31 is an oscillator that generates a local angular frequency ω, and in the mixer 12, the above π/4 shift QP
The SK modulated wave R(t) is subjected to frequency conversion using the local angular frequency ω, and the converted signal is expressed by the following equation.

L(t) −cos((ω0 ω,)t θ, +y, π/2 π/
4] The signal L(t) after conversion of equation (4) is sent to the delay circuit 17
3, i, (t, t) + CO3!, which is delayed by one symbol at 3, i, (t, t) + CO3! : (ωC-(N +→(t-T)θi-
, ++Vi-π/2-π/4) (5) East, 1;)) The phase of the L(t-T) one signal is changed to π/ in the delay circuit (π/2 phase shifter) 1!3. It is delayed by 2 and becomes as follows.

i,'(t4) =CO! Ic(ωCω,,)(t,T)θ6､Y t
-+π/ 2- , '3π743 (6) And mixer 1. ] Smell Koji, above (4) 2 and (5)
,) 2 and remove the high-angle 1-wave component at low/(Sfile location 15) 2, Δ・1.
Cl-1 demodulation base handi language D1 is obtained l♂rero3=
cos((ωc,'++ l)Tθ, Jθ.−<V
, -1/j,)π/22 cos((O) ζ-ωL>
T + δ(x,) 7J:/21r,/4'l
(7) Similarly, in MIKI+14, the above (
By multiplying the equation (4) and the equation (6) and removing the frequency component in the C, l-bus filter 16, L=Q-
,, -CH demodulated Bebepan V signal D2 is obtained, =c
os((ωe-0)t)T, θ 2+ θ,
I+cyi-y, -π/2+π/2] =cos((ωCωt)T +6(X,)π/2+π/4)=-5jn C(・yiH・υ,,, JT(δ(X
%) π/2τ/4') <8) is obtained. , 2, 2 (ω, -ωL)T・2nπ (where the number is a natural number) Set km, + door, and T to satisfy (9)lL:I”7)γ
■, Equation (8) is respectively 111, CriS (δ(X,)π/2 π/4]
(1,0)1)2-3in (δ(x
,'lx/2-π/4) (1,i
) Then, in the code discriminator 20, a timing recovery circuit (BTR, bit timing recover) is used.
ry) When the values of Dl and D2 are positive at the optimal point using the clock reproduced by 19, it is determined to be 0, and when they are negative, it is determined to be 1. In this way, the input signal X is reproduced as shown in FIG.

By the way, in the above detection method, when the local frequency of the receiver fluctuates, equations (8) and (9) are no longer satisfied, so the aperture of the demodulated eye pattern decreases and the demodulation characteristics deteriorate. 7 and 8 show a normal demodulated eye pattern and a demodulated eye pattern with a reduced aperture due to local frequency fluctuations. In this way, it can be seen that the identification margin decreases due to fluctuations in the local frequency. In particular, when the delay amount T is large (data rate is slow), it becomes critical to local frequency fluctuations and becomes a practical problem.

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a π/4 shift QPSK differential detection demodulator that reduces deterioration of demodulation characteristics due to fluctuations in the local frequency of a receiver. It is.

[Means to solve the problem]

FIG. 1 is a basic configuration diagram of a first embodiment of a shift QPSK differential detection demodulator according to the present invention. In Figure 1,
1 is a local frequency conversion means, 2 is a frequency conversion means, 3
4 is a delay detection means, 4 is an 8-multiplying means, 5 is a code identification means,
Further, 6 is a loop filter means.

The local frequency generating means 1 generates a variable local frequency according to a control amount from others.

The frequency conversion means 2 receives a signal modulated by a predetermined code, and converts the frequency by mixing the signal with the local frequency.

The delay detection means 3 performs delay detection using the frequency-converted signal and demodulates the baseband signal.

The 8-multiplying means 4 calculates the offset of the local frequency by multiplying the baseband signal by 8.

The loop filter means 6 low-pass filters and amplifies the offset and supplies it as the control amount to the local frequency generation means (1).

FIG. 2 is a basic configuration diagram of a second form of the π/4 shift QPSK differential detection demodulator of the present invention. In Figure 2, 1
' is local frequency generation means, 2 is frequency conversion means, 3
' is a delay detection means, 4 is an 8-multiplying means, 5 is a code identification means, 6' is a loop filter means, 7 is a delay means, and
8 is a sample clock generating means.

Local frequency generating means 1' generates a local frequency.

The frequency conversion means 2 receives a signal modulated by a predetermined code, and converts the frequency by mixing the signal with the local frequency.

The delay means 7 delays the frequency-converted signal.

The delay detection means 3' performs delay detection using the frequency-converted signal and the delayed signal to demodulate the baseband signal.

The sample clock generating means 8 provides the timing of delay in the delay means 7, which is variable according to the control amount from others.

The 8-multiplying means 4 calculates the offset of the local frequency by multiplying the baseband signal by 8.

The loop filter means 6' low-pass filters and amplifies the offset and supplies it as the control amount to the local frequency generation means 1.

[For production]

Letting the offset of the local angular frequency be Δω, the above (
Equations (10) and (11) are as follows.

Dl= cos (−ΔωtT+δ(xi) x /2
- x'/4] (12) D2 = -5in (-ΔωL
T+δ(xt) tt /2- x /4) (
13) Here, A=-ΔωLT+δ(xi) tt /2- x /4
(14) 8A=-8ΔωLT+4π
δ(xi)−2π”−8ΔωL, T
(15), which shows that the modulation component is removed every time the signal is multiplied by 8, and the local frequency offset can be detected. In order to multiply by 8, the following calculation is required.

B = 5in8A = 2sin4Acos4A = 4sin2Acos2A (cos2A+5ib2
/i) (cos2A-sin2A)=8sinAc
osA (cosA+5inA) (cosA-sinA
) XX [(cosA+5inA) (cosA-s
inA)+2sinAcosA) X x [(cosA+5inA)(cosA-sinA)
-2sinAcosA) In the first embodiment of the present invention, the l-CH, , Q-
By feeding back information on the phase difference (local frequency offset) obtained by multiplying the two baseband signals of CH by 8 by the 8-multiplying means 4 to the local frequency generating means 1 to form a phase-locked loop, It becomes possible to control the local frequency generated by the local frequency conversion means, obtain the optimum frequency, and always satisfy equation (9).

In the second embodiment of the present invention, the phase difference (local The sample clock frequency of the delay element is controlled by feeding back the information of the frequency offset) to the sample clock generating means 8 which provides the delay timing of the delay means 7 in the delay detection means 3 and forming a four-slot loop. , it becomes possible to obtain the optimum amount of delay and always satisfy equation (9). 1 In this way, deterioration of demodulation characteristics due to local frequency fluctuations of the differential detection demodulator can be reduced.

〔Example〕

FIG. 3 shows the configuration of an embodiment of the first form of the present invention. In FIG. 3, an antenna 10, a mixer 12
,13. and 14, delay circuits 17 and 18, low-pass filters 15 and 16, timing recovery circuit (B
T R, bit timing reovery)I9
, and the code discriminator 20 is the same as that in the configuration shown in FIG. 5 described above.

In the configuration of FIG. 3, the local oscillator it that provides the local frequency to the mixer 12 is composed of, for example, a voltage controlled oscillator such as a VCXO. 8 multiplication means 4 in Figure 1
A local frequency offset detection circuit 21 is provided correspondingly.

The local frequency offset detection circuit 21 has the above-mentioned (1
2) Output Di (I
-CH baseband signal) and the output D2 of the low-pass filter 16 (Q-CH baseband signal) represented by (13) 2 above, perform the calculations shown in equations (14) and (16) 2. It is composed of an adder 24.2B, subtracters 26, 30, and multipliers 25, 27, 29, 31, 32 corresponding to the four arithmetic operations on the right side of (16) 2. The adders and subtracters are realized by operational amplifiers, and the multipliers are realized by analog multipliers, each of which is realized by a known configuration.

The output of the local frequency offset detection circuit 21 is low-pass filtered and amplified by a configuration corresponding to the loop filter means 6 of FIG. Ru. In this way, the demodulated 1-CH, Q-CH
A phase difference signal (local frequency offset) obtained by multiplying the two baseband signals by 8 is fed back to the local frequency generating means 1 to form a phase-locked loop, thereby controlling the local frequency, It becomes possible to obtain the optimum frequency and always satisfy equation (9).

FIG. 4 shows the configuration of an embodiment of the second form of the present invention. In the configuration shown in FIG. 4, the phase difference (local frequency offset) signal obtained from the local frequency offset detection circuit 2L low-pass filter 22' and amplifier 23' similar to that in the configuration shown in FIG. 3 is sent to the delay circuit 17. The signal is supplied as a control signal to a sample clock generation circuit 11' which supplies a sample clock to the sample clock. The sample clock generation circuit 11' is also composed of a voltage controlled oscillator such as a VCXO.

Although the configuration of the delay circuit 17 is not shown, it consists of a shift register, and the output of the mixer 2 input to this shift register becomes 1 when passing through this shift register.
It is configured to undergo a symbol time T delay. Since this shift register operates according to the sample clock supplied from the sample clock generation circuit 11', the frequency of this sample clock is determined by the offset information of the local frequency detected as described above (amplifier 23'). (output of , the frequency of the sample clock, i.e.
Always by controlling the delay time T in the delay circuit 17 (9)
It becomes possible to satisfy the formula.

〔Effect of the invention〕

According to the π/4 shift QPSK differential detection demodulator of the present invention, it is possible to reduce deterioration of demodulation characteristics when the local frequency of the receiver changes. In addition, even before the phase-locked loop is pulled in, the present invention has demodulation performance equivalent to that of a conventional differential detection demodulator, so the loop time constant can be increased, and compared to synchronous detection, Deterioration of demodulation characteristics due to high-speed fading can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration diagram of the first embodiment of the present invention, FIG. 2 is a basic configuration diagram of the second embodiment of the invention, and FIG. 3 is a basic configuration diagram of the first embodiment of the invention.
FIG. 4 is a block diagram of an embodiment of the second embodiment of the present invention, and FIG. 5 is a conventional π/4 shift QP.
A diagram showing a configuration example of an SK delayed detection demodulator, FIG. 6 is a diagram showing the relationship of signals in the π/4 shift QPSK delayed detection demodulator of FIG. 5, and FIG. 7 shows a normal demodulation eye pattern. and FIG. 8 are diagrams illustrating the reduction in discrimination margin operation due to local frequency fluctuations. [Explanation of symbols] 1.1'... Local frequency generation means, 2... Frequency conversion means, 3, 3'... Delay detection means, 4...8
Multiplication means, 5... Code identification means, 6.6'...
Loop filter means, 7... Delay means, 8... Sample clock generation means, 10... Antenna, 11... Local oscillator, 11'... Sample clock generation circuit, 12.13
．． 14...Mixer, 15 16 22.22'...Low pass filter, 1
7...Delay circuit, Engineering 8...Delay circuit (π/2 phase shifter), 19-...Timing regeneration circuit (BTRlbit tis+ingre
20... code identifier, 21... local frequency offset detection circuit, 23.
23'...Amplifier, 31...Local oscillator.

Claims (1)

[Claims] 1. A local frequency generating means (1) that generates a variable local frequency according to a control amount from another; and a local frequency generating means (1) that receives a signal modulated with a predetermined code and mixes it with the local frequency. A π/4 shift comprising: a frequency conversion means (2) that performs frequency conversion by performing frequency conversion; and a delay detection means (3) that performs delay detection using the frequency converted signal to demodulate a baseband signal. In the QPSK delayed detection demodulator, the baseband signal is multiplied by 8 to obtain the offset of the local frequency, and the offset is low-pass filtered and amplified, and the local frequency generating means (1) a π/4 shift QPSK differential detection demodulator, comprising loop filter means (6) for supplying the control amount as the control amount. 2. Local frequency generating means (1') that generates a local frequency; Frequency converting means (2) that receives a signal modulated with a predetermined code and converts the frequency by mixing it with the local frequency; Delay means (7) for delaying the frequency-converted signal
and a delay detection means (3') that performs delay detection using the frequency-converted signal and the delayed signal to demodulate the baseband signal, and a delay detection means (3') that demodulates the baseband signal by using the frequency-converted signal and the delayed signal, and , and sample clock generation means (8) for providing delay timing in the delay means (7), the local frequency is determined by multiplying the baseband signal by eight. and a loop filter means (6') for low-pass filtering and amplifying the offset and supplying it as the controlled variable to the local frequency generating means (1). A π/4 shift QPSK delayed detection demodulator.