JPH0398131A - 2-byte instruction injection circuit - Google Patents

Abstract

PURPOSE:To inject an instruction code of optional 2-byte length via a designated address without affecting the operation of a microprocessor by using a specific instruction injecting mechanism. CONSTITUTION:An address coincidence detection circuit 3 detects a bus cycle and a byte position where the instruction code of a designated address are fetched by a microprocessor 1 and produces an instruction injection request signal. At the same time, a swap request latch 4 holding an instruction injection request produces an instruction injection request signal of the second byte at the byte position of the next address following the designated address. The L-byte and H-byte instruction injection means 6 and 8 transmit properly the instruction codes to the data buses 14L and 14H based on the output signals of the circuit 3 and the latch 4 respectively. A circuit consisting of an adder circuit 10, an address latch 11, and a converter 12 detects a case where the instruction code fetching cycles are not identical with continuous addresses and cancels the held instruction injection request signal of the second byte. As a result, a debugging proper instruction code of 2-byte length can be injected with no influence given to the action sequence of the microprocessor.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to improving the functionality of an instruction injection circuit for debugging an in-circuit emulator.

(Prior art) In-circuit emulators are generally equipped with a break function, which allows the central processing unit (CPU) to forcibly generate a unique bus cycle in the bus cycle in which the central processing unit (CPU) fetches an instruction at a preset address. (In many cases, an interrupt instruction is used) to start the break process. There are two methods for replacing instructions: preparing dedicated hardware, detecting a bus cycle that matches the set address, switching the data bus in that bus cycle, and forcibly fetching the break instruction code; and one method using random access memory. There is a method of directly rewriting the instruction code on (RAM).

Problems to be Solved by the Invention> However, with the former method, the instruction code to be replaced is limited to a 1-byte instruction depending on the CPU, and with the latter method, there is no limit to the number of instruction bytes, but the setting address There was a problem in that it required a precondition that the instructions existed in the RAM.

In fact, in the case of CPUs such as Intel's 8086, 2
Since a byte instruction may span two bus cycles, there is a restriction that only a 1-byte instruction can normally be used as a break instruction.

Recently, there have been attempts to detect execution triggers and task breaks by replacing instructions in addition to the break function, but if the instruction code to be replaced is limited to 1 byte, the functionality is severely limited. There are some drawbacks.

The present invention has been made in view of the above points, and its purpose is to enable the injection of 2-byte instructions in the instruction injection function realized by dedicated hardware, and to enable continuous instruction fetch bus cycles depending on the address to be set. An instruction note that allows you to inject a 2-byte instruction without affecting CPU operation, even when the instruction spans two bus cycles, or when 2 bytes are fetched as the same word in one bus cycle. The purpose is to provide an entrance route.

Means for Solving the Problems> The present invention aims to achieve the above objects by using an in-circuit emulator that uses a specified address pattern and an address on the target microprocessor's address bus when An address match detection circuit that outputs an instruction injection request signal for each byte position when the microprocessor's data bus width is divided into bytes, and a signal that indicates the read timing of the instruction code fetch cycle based on the microprocessor's status signal. a status decoder that generates a status decoder; a latch that holds an instruction injection request when instruction injection is required in the next instruction code fetch cycle among the outputs of the address match detection circuit; an adder circuit and a latch; a comparator, means for inhibiting instruction injection when the microprocessor executes a branch instruction in a continuing instruction injection cycle and fetch addresses become discontinuous, and a means for inhibiting instruction injection when the instruction injection timing is selected by a multiplexer. 1 byte of a 2-byte instruction [1
Alternatively, it includes an instruction injection means for outputting any instruction code of the second byte onto the data bus, and a buffer means for inhibiting fetching of the original instruction code output on the data bus at the instruction injection timing. It is characterized by what it did.

Function> The address coincidence detection circuit detects the bus cycle and byte position in which the instruction code at a pre-specified address is fetched by the microprocessor, and generates an instruction injection request signal.

Furthermore, a latch (swap request latch) that holds an instruction injection request generates a second byte instruction injection request signal at the byte position of the next address following the specified address.

The instruction injection means sends an appropriate instruction code to the data bus based on the output signals of the address coincidence detection circuit and the swap request latch.

A circuit consisting of an adder circuit, an address latch, and a converter detects when instruction code fetch cycles do not reach consecutive addresses due to branch instructions, etc., and releases the held second byte instruction injection request signal. do. In this way, the fixed instruction code is forced to be fetched via the instruction injection means instead of the instruction code that should originally be fetched.

This makes it possible to inject a 2-byte long debug specific instruction code without affecting the operation sequence of the microprocessor.

Example The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a 2-byte instruction injection circuit according to the present invention. In the figure, 1 is a microprocessor, and here a 16-bit microprocessor is targeted. 2 is a status decoder which outputs a signal FETCH indicating the read timing of the instruction code fetch cycle based on the status signal of the microprocessor 1.
generate.

3 is an address match detection circuit which, when the specified address pattern and the address on the target microprocessor's address bus match, sends instructions for each byte position when the data bus width of microprocessor 1 is divided into byte positions. It outputs the injection request signal, and BHHIT and B
Outputs two types of HIT signals for each byte of LHIT. For these HIT signals, BHBIT is output when there is a match on the upper address side of the instruction codes accessed in units of 16 bits, and BLHIT is output when there is a match on the lower address side.

4 is a swap (SWAP) request latch, and BHHIT of the address match detection circuit 3 is activated by the fetch signal FETCH.
Latch. This is used to hold an instruction injection request in the output of the address match detection circuit 3 when instruction injection is required to continue in the next instruction code fetch cycle.

10 is an adder circuit that increments the address on the address bus 13 and outputs the incremented address.

11 is an address latch that latches the output of the adder circuit 10 using the fetch FETCH signal, and 12 is a comparator that compares the output of the address latch 11 with the address on the address bus 13. If they match, the output signal EQ becomes HIGH. .

The portion consisting of the adder circuit 10, address latch 11, and comparator 12 is a means for prohibiting instruction injection when the microprocessor 1 executes a branch instruction and the fetch address becomes discontinuous in a continuing instruction injection cycle. be.

5 is an AND gate which ANDs the output of the swap request latch 4 and the output of the comparator 12.

6 and 8 are instruction injection means, 6 is an L-byte instruction injection circuit, and 8 is an H-byte instruction injection circuit. The instruction code of the byte is sent to the data bus 14H. 14L so that it can be output as appropriate.

In particular, to explain the structure of the L byte instruction injection circuit 6, the OR gate 61 inputs the BLHI of the address match detection circuit 3.
OR the T signal and the output of AND gate 5, FETC
If the output of the OR game 161 is active during the H period, the swap signal SWAP is activated. The multiplexer 65 is controlled by the output of the AND gate 5, and selectively outputs one of the instruction code registers 63 and 64. The 3-state buffer 66 is enabled when the swap signal SWAP is active, and transfers the instruction code selected by the multiplexer 65 to the data bus 14.
Output on L.

7 and 9 are data buses 14L. The bidirectional buffer 7 is controlled by the SWAP signal of the L-byte instruction injection circuit 6, and the bidirectional buffer 9 is controlled by the SWAP signal of the H-byte instruction injection circuit 8.

The operation in such a structure will be explained below with reference to the time chart of FIG. Note that the time chart shows waveforms of each part in the following three cases.

Case (2) is a case where address coincidence is detected at the lower address of 16-bit data, and the 2-byte instruction injection is performed in the same bus cycle.

Case (2) is a case where address matching is detected at the upper address, and instruction injection of the second byte is postponed until the next instruction fetch cycle.

In case ■, an address mismatch occurs for a program branch in the second byte instruction injection cycle.
This is a case where instruction injection is prohibited.

Now, various status signals outputted from the microprocessor 1 are input to the status decoder 2, which generates a FETCH signal indicating read timing in a bus cycle in which the microprocessor 1 fetches an instruction code. Address match detection circuit 3 outputs a BIT signal when a preset address appears on address bus 13.

Signal BL indicating a match on the lower address side (even address)
HIT is input as an instruction injection request signal to the L-byte instruction injection circuit 6 and the H-byte instruction injection circuit 8, and SWPREQL#1 requests injection of the first byte instruction code (CODE#1) to the L-byte side data bus 14L, respectively. and SWPREQH#2, which requests injection of the second byte instruction code (CoDE#2) to the H-byte side data bus 14H.
It becomes a signal.

In the instruction injection circuit 6, when either the SWPREQ #1/#2 request signal is applied, the 3-state buffer 66, which is an instruction code injection port, is enabled during the period of the FETCH signal, and the command code selected by the multiplexer 65 is enabled. Either the first byte or the second byte of the instruction code is output to the data bus 14L. The same applies to the instruction injection circuit 8, and the instruction code is output to the data bus 14H.

At this time, the SWAP signal is output while the instruction injection circuit is injecting the instruction, and this signal controls the bidirectional buffer 7.9 provided for each byte and appears on the data bus during instruction injection. Prohibit read data from devices.

On the other hand, the match detection signal BHHIT at the upper address (odd address) output from the address match detection circuit 3 is high.
It is input manually as SWPREQH#1, which requests the byte instruction injection circuit 8 to inject a 1-byte instruction code, and
The data of swap request latch 4 is given to the FE
A signal latched at the rising edge of the TCH signal is applied via the AND gate 5 to the L-byte instruction injection circuit 6 as SWPREQL#2 requesting injection of the second byte instruction code.

As a result, when BHHIT is detected, the instruction injection for the second byte is performed in the next instruction fetch bus cycle of the bus cycle in which the address match was detected.

Here, if the execution unit in the microprocessor executes a branch instruction after microprocessor 1 fetches the injection instruction of 1 byte 11, the instruction injection of the 2nd byte is performed in the instruction code fetch cycle of the branch destination address. There is a possibility that the microprocessor 1 may go into a runaway state. To avoid this problem, address bus 13
The adder circuit 10 connected to the address increments the first byte instruction injection address and provides it to the address latch 11.
Subsequently, the output of the latch 11 becomes one input of the comparator 12 as the expected value of the instruction injection address of 2 bytes 1]. Since the other input of the comparator 12 is directly connected to the address bus 13, in the above-mentioned malfunction situation, the output EQ becomes negative (LOW in this case) in the second byte instruction injection cycle, and this signal causes the AND gate to 15 is controlled, and the instruction injection operation for the second byte is immediately prohibited.

Note that although the above embodiment is directed to a 16-bit microprocessor, the same circuit structure can be used for a 32-bit microprocessor as well. However, in that case, the detection output of the address match detection circuit 3 becomes four signals for each byte, and four instruction injection circuits are also required.

In addition, the data input of the swap request latch is connected to the output of the detection signal on the most significant side, and this latch output is sent via the AND gate 5 to the instruction injection request signal for the second byte of the instruction injection same path corresponding to the lowest address. so that it is connected as .

Effects of the Invention> As explained in detail above, according to the present invention, a desired 2-byte instruction code can be injected at a specified address without affecting the operation of the microprocessor. A wide range of instructions can now be used as debugging instructions, not just interrupt instructions, and the program counter relative branch instruction can be used to implement an execution detection function and a task break function.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a 2-byte instruction injection circuit according to the present invention, and FIG. 2 is a time chart for explaining the operation. 1...Microprocessor 2...Status decoder 3...Address match detection circuit 4...Swap request latch 5...And gate 6...L byte instruction injection circuit 7.9...Bidirectional Buffer 8... H byte instruction injection circuit 10... Adder circuit 11... Address latch 12... Converter 13... Address bus 1
4H, 14L...data bus

Claims (1)

[Claims] In an in-circuit emulator, when a specified address pattern matches an address on the target microprocessor's address bus, the data bus width of the microprocessor is divided into bytes, and the byte position is an address match detection circuit that outputs an instruction injection request signal; a status decoder that generates a signal indicating read timing of an instruction code fetch cycle based on a microprocessor status signal; and an address match detection circuit that outputs an instruction injection request signal; It consists of a latch that holds an instruction injection request when instruction injection is required following an instruction code fetch cycle, an adder circuit, a latch, and a comparator, and the microprocessor executes a branch instruction during the instruction injection cycle that continues. means for inhibiting instruction injection when the fetch address becomes discontinuous, and a means for disabling the instruction code of either the 1st or 2nd byte of the 2-byte instruction selected by the multiplexer at the instruction injection timing to the data bus. and a buffer means for inhibiting the fetching of the original instruction code outputted onto the data bus at the instruction injection timing, and the instruction at the address specified by the address matching detection circuit. The code detects the bus cycle and byte position fetched by the microprocessor and generates an instruction injection request signal, and at the same time generates a second byte instruction injection request signal at the byte position of the next address following the specified address. , if the instruction injection byte position of the second byte occurs in the next instruction code fetch cycle, hold that instruction injection request signal, and if the next instruction code fetch cycle is a continuous address due to execution of a branch instruction, etc. If there is no instruction injection request signal for the second byte held above, the instruction injection request signal for the second byte is inhibited to avoid illegal instruction injection, and these instruction injection request signals cause the original fetch to be performed at the read timing of the instruction fetch cycle output by the status decoder. A fixed instruction code is forcibly fetched through the instruction injection means instead of an instruction code that should be executed, and a 2-byte long debug-specific instruction code can be fetched without affecting the operation sequence of the microprocessor. A 2-byte instruction injection circuit characterized by being capable of injection.