JPH02135547A - Task breaking circuit - Google Patents

Abstract

PURPOSE:To break a task by adding simple hardware to a breaking circuit in a monitor program system by means of a bus switching, and continuously and forcibly inserting a relatively branching instruction to the same address. CONSTITUTION:By a coincidence detecting circuit 2, a status decoder 3 and a gate signal generating circuit 4, a bus cycle, at which the instruction code of the designated address is fetched by means of a microprocessor 1, is detected, and the relatively branching instruction codes dispersed in the same address instead of the instruction code are send through an instruction inserting means 6 into the bus cycle. As a result, an operation to forcibly fetch the relatively branching instruction code is repeatedly executed. When the reference and alteration of a register or a memory are designated, the instruction code applied to the instruction inserting means 6 is switched from a multiplexer 7 to a software interruption instruction, and outputted to the bus. Thus, the breaking can be executed without prohibiting the interruption.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to an improvement in the break function of an in-circuit emulator.

<Prior Art> In general, in-circuit emulators have, as their debug function, a break function that detects the timing at which an instruction at a specified address is executed and interrupts subsequent program processing.

Conventional break 8IO'! : Forcibly replaces the instruction code at the address that causes a break with a software interrupt instruction, detects the interrupt processing activation cycle, switches the bus to the memory space for the in-circuit emulator, and executes a processing routine called a monitor program. This is achieved by creating a halt state within the system.

<Problem to be solved by the invention> However, with this method, it is difficult to start another task by interrupt while a break is occurring in a task, so most in-circuit emulators Interrupts are prohibited.

However, in terms of usage, there are applications that start specific tasks at regular intervals, and there are many situations where a function to break only specified tasks is required.
To deal with this, there is a method of executing the monitor program in the user memory space without performing bus switching, but there are restrictions in that the interrupt for starting the process and the monitor program area cannot be used by the user.

In addition, RAM (Random Access He
r#ory) can be directly replaced with a loop instruction to cause a break, but it is also possible to create a break by directly converting the instruction code of the user program placed on the program into a loop instruction. This method is difficult to implement because it is complicated.

The object of the present invention has been made in view of the above points, and is to add simple hardware to the conventional monitor program type break circuit using bus switching, thereby making it possible to prevent interrupts from being disabled at specified breakpoint addresses. An object of the present invention is to provide a task break circuit for an in-circuit emulator that realizes a break state as it is, breaks only a task that includes a breakpoint, and enables other tasks to start.

<Means for Solving the Problems> The present invention to achieve such an object compares a given comparison address with an address on the address bus of a target microprocessor, and when they match, outputs a match signal. a status decoder that generates a signal indicating the read timing of the instruction code fetch cycle based on the status signal of the microprocessor; a gate generation circuit that generates a signal indicating instruction injection timing based on a condition in which a break is specified; and a buffer means that prohibits fetching of the original instruction code output on the data bus at the instruction injection timing. and an instruction injection means for outputting an instruction code of either a relative branch instruction to the local address selected by the multiplexer or a software interrupt instruction onto the data bus at the instruction injection timing, and an instruction injection means for detecting the execution cycle of the software interrupt. It is characterized by having a monitor processing circuit that switches the data bus and includes a memory that stores a processing program for referencing and changing the registers prepared in advance and the user memory.

In the present invention, a coincidence detection circuit, a status decoder, and a gate signal generation circuit detect a bus cycle in which an instruction code at a specified address is fetched by the microprocessor, and the same instruction code is inserted instead of the instruction code that should originally be fetched. A relative branch instruction code for branching to the address is sent out during the bus cycle via the instruction injection means.

As a result, the operation of forcibly fetching the relative branch instruction code is repeatedly performed. This realizes a software break.

When referencing or changing a register or memory is specified, the instruction code given to the instruction injection means is switched to a software interrupt instruction by a multiplexer and output to the bus.

The monitor processing circuit starts the monitor program, and immediately returns from the interrupt routine after completing the necessary processing, and restarts the injection of relative branch instruction codes.

When break release is specified, the instruction injection means is controlled to stop forced injection of the instruction code.

This allows a break to be achieved without disabling interrupts.

Note that tasks other than the task that includes the address that caused the break can always be started.

<Example> The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing a main part of a large-scale embodiment of a task break circuit according to the present invention. In the figure, 1 is the target microprocessor, 2 is a match detection circuit, 3 is a status decoder, 4 is a gate signal generation circuit, 5 is a first 3-state buffer, 6 is an instruction injection port, 7 is a multiplexer, 8 1 is a monitor processing circuit, 9 is a second state buffer, 10 is an address bus, and 11 is a data bus.

The match detection circuit 2 compares the given comparison address with the address on the address bus 10 of the microprocessor 1, and outputs a match signal HIT when the two match.

The gate signal generation circuit 4 generates the output of the status decoder 3, that is, the signal FETCH which provides a read strobe in the instruction code fetch cycle under the condition that the signal 5WAPEN indicating that a break is to be made at a specified address is active, and the HIT signal. A 5WAP signal indicating the data read timing in the instruction injection cycle is generated based on the 5WAP signal.

The first 3-state buffer 5 is connected to the microprocessor 1
It operates to disconnect from the target data bus and prohibit fetching of instruction codes on the target memory in response to the 5WAP signal or the MONIT signal, which will be described later.

The input of multiplexer 7 contains the JUMP instruction code and S
A relative JUMP instruction (denoted as JUMP, N) or a software interrupt instruction (denoted as 5WI) with a displacement such that the WI instruction code pattern is given and returns to the same address as the fetched address.
One of the instruction codes is selected by the externally applied C0DESF and L signals, and is outputted onto the data bus via the instruction injection port 6 at the timing of the 5WAP signal.

The monitor processing circuit 8 is a general processing circuit in an in-circuit emulator, and detects the execution state of the SWI instruction, generates a signal MONIT indicating that monitor processing is being started, turns off the first three-state buffer 5, and turns off the first three-state buffer 5. 2. The nine three-state buffers are turned on and the monitor program in the monitor circuit is controlled to be executed.

The operation in such a configuration will be explained next with reference to the time chart shown in FIG. Here, we will take as an example a case where the method is applied to a microprocessor that performs instruction briefetch. When the breakpoint address is set to N, the comparison address of the match detection circuit 2 becomes N, and the HIT signal is output as shown in FIG. As shown in Figure 5, the 5WAP EN signal becomes active as shown in Figure 2).
The FETCH signal in the cycle in which the HIT signal becomes active is output as the instruction injection signal 5WAP (timings A and B in FIG. 2).

This realizes a software break function in a state where interrupts are accepted.

Here, if it is necessary to refer to or change a register or user memory during a break in a certain task, the injection instruction code can be easily changed to the SWI instruction by switching the C0DESEL signal shown in (to) in Figure 2. be done (
At timing C) in Figure 2, when the SWI instruction is executed, M
The ONIT signal ((h) in the figure) becomes active, and the normal monitor processing program executes necessary processing. After executing the monitor process, inject the JMP and N instructions again (timing D), and when the break is released, the 5WAPE
By negating the N signal, forced instruction injection processing at address N is prohibited.

<Effects of the Invention> As explained in detail above, according to the present invention, the break function is realized by continuously forcibly injecting an instruction for relative branching to the same address, which is superior to conventional in-circuit emulators. There is no restriction such that interrupts are disabled during a break, so even if a break is in progress within a task, it is possible to start another task using an interrupt. Therefore, when debugging using an in-circuit emulator, it is possible to enter a break state only for the target system without interrupting the entire target system, which has the effect of improving the debugging efficiency of the system.

[Brief explanation of drawings]

FIG. 1 is a main part configuration diagram showing an embodiment of a task break circuit according to the present invention, and FIG. 2 is a time chart for explaining the operation. 1...Microprocessor, 2...-Several circuits,
3... Status decoder, 4... Gate signal generation circuit, 5... First 3-state buffer, 6... Instruction injection port, 7... Multiplexer, 8... Monitor processing circuit, 9... second state buffer, 10...
...Address bus, 11...Data bus.

Claims (1)

[Claims] In an in-circuit emulator, an address match detection circuit that compares a given comparison address with an address on an address bus of a target microprocessor and outputs a match signal when they match, and a microprocessor. a status decoder that generates a signal indicating the read timing of the instruction code fetch cycle based on the status signal of the status decoder, and a break based on the output of the status decoder and the output of the address match detection circuit under the specified condition. a gate generation circuit for generating a signal indicating instruction injection timing; a buffer means for inhibiting fetching of the original instruction code outputted onto the data bus at the instruction injection timing; an instruction injection means that outputs an instruction code of either a relative branch instruction to its own address or a software interrupt instruction onto the data bus; a register that detects the execution cycle of the software interrupt and switches the data bus; and a monitor processing circuit including a memory containing a processing program for referencing and changing user memory. An operation in which a relative branch instruction code that branches to the same address is sent during that bus cycle through an instruction injection means, instead of the instruction code that should be originally fetched, and the fetch is forcibly performed. A software break is achieved by repeating the above steps, and when a register or memory reference or change is specified, the instruction code to be injected is switched to a software interrupt instruction using a multiplexer, the monitor program of the monitor processing circuit is started, and the necessary processing is completed. Then, immediately return from the interrupt routine and resume injection of the relative branch instruction code, and if break release is specified, control the instruction injection means to stop forced injection of the instruction code to break without inhibiting interrupts. A task break circuit is characterized in that it is possible to always start tasks other than the task containing the broken address.