JPH0397701U - - Google Patents

Info

Publication number
JPH0397701U
JPH0397701U JP357890U JP357890U JPH0397701U JP H0397701 U JPH0397701 U JP H0397701U JP 357890 U JP357890 U JP 357890U JP 357890 U JP357890 U JP 357890U JP H0397701 U JPH0397701 U JP H0397701U
Authority
JP
Japan
Prior art keywords
error
cpu
restarted
control device
sequence control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP357890U
Other languages
Japanese (ja)
Other versions
JP2523515Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990003578U priority Critical patent/JP2523515Y2/en
Publication of JPH0397701U publication Critical patent/JPH0397701U/ja
Application granted granted Critical
Publication of JP2523515Y2 publication Critical patent/JP2523515Y2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Safety Devices In Control Systems (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の一実施例によるシーケンス
制御装置のブロツク図、第2図はメモリスイツチ
3の構成を示す図、第3図は再スタート時のフロ
ーチヤートを示す図、第4図は他の実施例を示す
ブロツク図、第5図は従来のシーケンス制御装置
のブロツク図、第6図、第7図は従来のシーケン
ス制御装置の再スタート時のフローチヤートを示
す図である。 3……メモリスイツチ、4……ROM、6……
RAM、8……CPU、30……デイツプスイツ
チ。
FIG. 1 is a block diagram of a sequence control device according to an embodiment of this invention, FIG. 2 is a diagram showing the configuration of the memory switch 3, FIG. 3 is a flowchart at the time of restart, and FIG. FIG. 5 is a block diagram of a conventional sequence control device, and FIGS. 6 and 7 are flowcharts of the conventional sequence control device at the time of restart. 3...Memory switch, 4...ROM, 6...
RAM, 8...CPU, 30...Deep switch.

Claims (1)

【実用新案登録請求の範囲】 (1) 信号を入力するための入力端子、 入力端子からの入力信号に基づいて演算処理を
行い、出力信号を出力するCPU、 外部の制御対象機器に出力信号を与えるための
出力端子を備え、 異常状態を検知してエラー停止したCPUに対
し、再スタートした時、エラーがまだ残つている
か否かを判断し、エラーが残つていなければ運転
を再開するように構成されたシーケンス制御装置
において、 再スタート時にエラーが残つている場合には、
エラー解除選択手段の出力により、当該エラーを
リセツトして運転を再開するモードとエラー表示
をして停止するモードのいずれかを選択して実行
することを特徴とするシーケンス制御装置。 (2) 請求項1のシーケンス制御装置において、 メモリスイツチによりエラー解除選択手段を構
成したことを特徴とするもの。
[Scope of claim for utility model registration] (1) An input terminal for inputting signals, a CPU that performs arithmetic processing based on the input signal from the input terminal and outputs an output signal, and an output signal to an external device to be controlled. It is equipped with an output terminal to supply a signal to a CPU that has stopped due to an error when an abnormal condition is detected, and when the CPU is restarted, it is determined whether or not the error still remains, and if no error remains, the CPU is restarted. In a sequence control device configured as follows, if an error remains when restarting,
A sequence control device characterized by selecting and executing either a mode in which the error is reset and the operation is restarted or a mode in which the operation is stopped after displaying the error, based on the output of the error release selection means. (2) The sequence control device according to claim 1, characterized in that the error release selection means is constituted by a memory switch.
JP1990003578U 1990-01-18 1990-01-18 Sequence controller Expired - Fee Related JP2523515Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990003578U JP2523515Y2 (en) 1990-01-18 1990-01-18 Sequence controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990003578U JP2523515Y2 (en) 1990-01-18 1990-01-18 Sequence controller

Publications (2)

Publication Number Publication Date
JPH0397701U true JPH0397701U (en) 1991-10-08
JP2523515Y2 JP2523515Y2 (en) 1997-01-29

Family

ID=31507391

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990003578U Expired - Fee Related JP2523515Y2 (en) 1990-01-18 1990-01-18 Sequence controller

Country Status (1)

Country Link
JP (1) JP2523515Y2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101063217B1 (en) 2008-12-05 2011-09-07 기아자동차주식회사 How to prevent restart error after shutting off hybrid vehicle controller

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01175303U (en) * 1988-05-30 1989-12-13

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01175303U (en) * 1988-05-30 1989-12-13

Also Published As

Publication number Publication date
JP2523515Y2 (en) 1997-01-29

Similar Documents

Publication Publication Date Title
JPH0397701U (en)
JPS5336438A (en) Input/output control unit
JPS6219040U (en)
JPH0292535U (en)
JPH0447701U (en)
JPH01175301U (en)
JPS62121527U (en)
JPH0187450U (en)
JPS63175245U (en)
JPH02149419U (en)
JPS5988704U (en) programmable controller
JPS63157639U (en)
JPH0366483U (en)
JPS602110U (en) steam oven
JPH0396399U (en)
JPS6343245U (en)
JPH0227219U (en)
JPH01151307U (en)
JPH01138102U (en)
JPS6322627U (en)
JPH0182630U (en)
JPS6329145U (en)
JPS63107028U (en)
JPS59134802U (en) single loop controller
JPH0314815U (en)

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees