JPH0396075U - - Google Patents

Info

Publication number
JPH0396075U
JPH0396075U JP470190U JP470190U JPH0396075U JP H0396075 U JPH0396075 U JP H0396075U JP 470190 U JP470190 U JP 470190U JP 470190 U JP470190 U JP 470190U JP H0396075 U JPH0396075 U JP H0396075U
Authority
JP
Japan
Prior art keywords
integrated circuit
surface pattern
multilayer printed
back surface
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP470190U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP470190U priority Critical patent/JPH0396075U/ja
Publication of JPH0396075U publication Critical patent/JPH0396075U/ja
Pending legal-status Critical Current

Links

JP470190U 1990-01-22 1990-01-22 Pending JPH0396075U (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP470190U JPH0396075U (zh) 1990-01-22 1990-01-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP470190U JPH0396075U (zh) 1990-01-22 1990-01-22

Publications (1)

Publication Number Publication Date
JPH0396075U true JPH0396075U (zh) 1991-10-01

Family

ID=31508435

Family Applications (1)

Application Number Title Priority Date Filing Date
JP470190U Pending JPH0396075U (zh) 1990-01-22 1990-01-22

Country Status (1)

Country Link
JP (1) JPH0396075U (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994023556A1 (en) * 1993-03-31 1994-10-13 Fanuc Ltd Multilayer printed board
JPH08148839A (ja) * 1994-11-21 1996-06-07 Nippondenso Co Ltd 混成集積回路装置
JP2007036050A (ja) * 2005-07-28 2007-02-08 Shin Kobe Electric Mach Co Ltd 積層回路基板の製造方法
JP2013518443A (ja) * 2010-01-26 2013-05-20 クアルコム，インコーポレイテッド 熱管理のための微細加工されたピラーフィン

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6158297A (ja) * 1984-08-29 1986-03-25 沖電気工業株式会社 多層印刷配線板
JPS63314858A (ja) * 1987-06-18 1988-12-22 Ibiden Co Ltd 表面実装部品用パッケ−ジ

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6158297A (ja) * 1984-08-29 1986-03-25 沖電気工業株式会社 多層印刷配線板
JPS63314858A (ja) * 1987-06-18 1988-12-22 Ibiden Co Ltd 表面実装部品用パッケ−ジ

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994023556A1 (en) * 1993-03-31 1994-10-13 Fanuc Ltd Multilayer printed board
JPH08148839A (ja) * 1994-11-21 1996-06-07 Nippondenso Co Ltd 混成集積回路装置
JP2007036050A (ja) * 2005-07-28 2007-02-08 Shin Kobe Electric Mach Co Ltd 積層回路基板の製造方法
JP2013518443A (ja) * 2010-01-26 2013-05-20 クアルコム，インコーポレイテッド 熱管理のための微細加工されたピラーフィン
US8877563B2 (en) 2010-01-26 2014-11-04 Qualcomm Incorporated Microfabricated pillar fins for thermal management

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