JPH039427B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for measuring electrical characteristics of digital integrated circuit devices requiring multiphase clocks.

When measuring a digital integrated circuit, it requires a great deal of effort, including simulation, to completely determine the expected output pattern for all input patterns given to the digital integrated circuit. It also requires a great deal of effort to program a neat output pattern.
In order to avoid this, a method is used in which a standard element output pattern and a device under test output pattern are compared to make a measurement to determine the quality. According to this method, it is only necessary to program the input pattern and there is no need to program the expected output value.

In this comparison method, the most important point is so-called synchronization, which matches the output timings of the standard element output pattern and the measured element output pattern.
Ordinary relatively simple logic devices, such as JK flip-flops, have a reset input terminal, and synchronization can be easily achieved by operating this terminal. By the way, the multiphase clock element (for example, a microcomputer, etc.) that is to be measured with the device of the present invention has a reset input terminal, but there are few cases in which all internal circuits are reset, and therefore, Synchronization cannot be achieved only by operating the reset terminal.

The present invention was made in order to eliminate the above-mentioned disadvantages of synchronizing the multiphase clock elements, and it provides a command to generate an output at a specific output terminal for the input of the multiphase clock element. To provide a measurement method that can improve the efficiency of multiphase clock element measurement by controlling a polyphase clock according to output generation conditions to synchronize standard and measured elements, and performing measurement using a comparison method. It is something.

First part about the general operation of multiphase clock elements.
This will be explained with reference to the drawings and FIG. In FIG. 1, when the clock CK is applied, the multiphase clock generation circuit 1 dedicated to the multiphase clock element 2 operates,
The polyphase clock voltages CP ₁ to CP _N shown in Fig. 2 are generated, and this is applied to a polyphase clock element (hereinafter referred to as DUT).
Add to 2. The input pattern generation circuit 4 is operated by the switch 3, and input patterns A ₀ to A _o are generated.
Add to DUT2 input. The operation of DUT2 is controlled by this input pattern, and the output of DUT2 is
DUT ₀ to DUT _N will appear. The output signal is applied to the output circuit 5. Note that the output circuit 5 is
Refers to the other party that is interfaced with DUT2. In general, the output signal of a multi-phase clock element such as a microcomputer etc. contains complex synchronisms or asynchronisms such as single or irregular occurrences.

For simplicity, the case of a three-phase clock will be explained below.

FIG. 3 is a diagram showing the relationship between input and output in the case of a three-phase clock.

The DUT operation used in the explanation is input as an example.
Immediate output by setting A ₀ to “H”
This is performed as an instruction execution operation that sets DUT ₀ to a high level “H”. When a command is given, the command is
DUT2 reads at the timing of CP-1,
It decodes at the timing of CP-2 and then sets the output DUT ₀ to "H" at the timing of CP-3. Next, the execution operation of an instruction that immediately sets the output DUT ₀ to a low level "L" by setting the input A ₀ to "L" will be explained. When a command is given, the DUT reads with CP-1, decodes with CP-2, and
It operates by setting the output DUT ₀ to “L” with CP-3. In other words, it can be said that the output of a polyphase clock element does not immediately respond to an input command, but executes the command after a certain clock delay. Polyphase clock elements, such as microcomputers, include devices in which the time (number of clocks CK) from when an instruction is received until it is executed internally and appears on the output (for example, PUT ₀ ) is not constant.

Although the explanation has been given above using an example of a three-phase clock, the operation is similar in the case of a multi-phase clock. The following explanation is entered for the case of a 3-phase clock in the same way as the above explanation.
The operation of the polyphase clock element regarding A ₀ is the same as above, and CP-1 is used for reading input data, CP
-2 is the decoding, and CP-3 outputs "H" or "L" depending on the instruction, and the timing for executing the instruction will be explained.

FIG. 4 shows an example of the operating situation of a multiphase clock element. As one of the measurement methods for determining the quality of multiphase clock elements (hereinafter referred to as elements), standard elements (hereinafter referred to as elements) are used as standard elements (hereinafter referred to as elements).
A measurement method that uses so-called comparison (hereinafter referred to as the comparison method) to determine whether the same result is obtained by temporally comparing the output signals of the output of the device under test (hereinafter referred to as DUT) and the output of the device under test (hereinafter referred to as DUT). There is. As previously explained, the problem with this comparison method is the synchronization (hereinafter referred to as synchronization) that matches the output timing (phase) between the DUT and STD. The phases of the multiphase clocks in the STD example and the DUT example change randomly each time the power is turned on, as shown in FIG. In this situation, the output of output DUT ₀ is not determined and measurement using the comparison method is not possible. Therefore, some kind of synchronization is required before starting measurement.

In Figure 4, VDD is the device power supply voltage, CK
is a clock signal for generating a multiphase clock (three phases in the figure), and CP-A, CP-B, and CP-C are outputs from the multiphase clock generation circuit. STD ₀ is STD
DUT ₀ is also one output of DUT 1.
There are two outputs. STDCP-3 and DUTCP-
3 is the clock timing received inside the device when STD and DUT are at VDD1 and VDD2, respectively. As you can see from this figure, when VDD is 1, STD is
CP-C feels like CP-3, and the DUT feels CP-B as CP-.
I feel it is 3. Next, when VDD2, STD is CP-
B feels like CP-3, and DUT feels like CP3. Therefore, there is a timing difference between STD ₀ and PUT ₀ as shown in the figure.

FIG. 5 is a diagram showing the configuration of a measuring device that enables the measuring method according to the present invention, and will be described as an example in which the execution operation of A ₀ described above is used for synchronization. In the figure, 6 is the DUT, 7 is the STD, 8 is the polyphase clock generation circuit that the DUT6 has, 9 is the polyphase clock generation circuit that the STD has, and 10 is the output of the DUT6.
Output comparison circuit for comparing with the output of STD7, 11,
12 and 13 are NAND gates, 14 and 1
5 is an AND gate, 16 is a clock pulse CK application terminal, 17 is a synchronization control signal E ₀ application terminal,
Reference numeral 18 denotes a terminal to which a match signal is output when the comparison results match, and 19 a terminal to which a mismatch signal is output when the comparison results do not match.

Synchronization by the measuring device having the above configuration will be explained. When the start switch 3 is closed,
The input pattern generation circuit 4 operates, and its output A ₀ ,
A ₁ ...A _N is supplied to the input terminals of DUT6 and STD7. The input pattern generating circuit 4 first generates a synchronization pattern in which only A ₀ is at a high level H, and subsequently generates input patterns A ₀ , A _{1 , .} . . , A _N for determination. DUT
The polyphase clock generation circuit 8 for STD and the polyphase clock generation circuit 9 for STD are driven by clock signals CK(D) and CK(S) outputted from AND gates 14 and 15, respectively.For example, the three-phase clock signal CP
-1(D), CP-2(D), CP-3(D) and CP-1
(S), CP-2 (S), and CP-3 (S), and supply these three-phase clock signals to DUT6 and STD7. The DUT6 and STD7 become operational when the power supply voltage _VDD is applied.

The DUT 6, which has become operational in this way, receives the three-phase clock signal from the multi-phase clock generation circuit 8.
CP-1(D) to CP-3(D) and input patterns A ₀ to _{A N} ,
In addition, STD7 is a multiphase clock generator 9 to 3
It receives phase clock signals CP-1 (S) to CP-3 (S) and input patterns A ₀ to _{A N} , respectively, and simultaneously decodes the command contents based on the input patterns and outputs the output command results DUT ₀ to _{DUT N} and STD ₀ ～
Output STD _N respectively. The output comparison circuit is
The logical levels "H" and "L" of DUT ₀ to DUT _N and STD ₀ to STD _N are compared in time series, and if they match, a match signal is sent to terminal 18, while if they do not match, a match signal is sent to terminal 19. outputs a discrepancy signal and displays the measurement results. FIG. 6 shows how the synchronization is executed.

CK, CP-1, CP-2, and CP-3 in Figure 6A show the same three-phase clock generation situation as in Figure 3, and _E0 is the synchronization control applied to terminal 17 in Figure 5. When the signal is "H", synchronization starts, and when it is "L", synchronization is completed. A ₀ is the output of DUT6 and STD7
Command signal that controls DUT ₀ and STD ₀ .
STD ₀ and DUT ₀ are “H”, STD ₀ is “L”,
Set DUT ₀ to “L”. Also, Figure 6 B and C are
It shows the operation of STD7 and DUT6, CK(S),
CK(D) is a clock signal applied to multiphase clock generation circuits 9 and 8, CP-1(S), CP-2(S), CP
-3(S) is the output of the multiphase clock generation circuit 9, and CP-1(D), CP-2(D), and CP-3(D) are the outputs of the multiphase clock generation circuit 8. STD ₀ , DUT ₀
is one of the outputs of STD7 and DUT6,
It operates according to the command of input A ₀ .

Next, the execution of synchronization will be explained. The synchronization circuit becomes operational with the E ₀ signal (H), and first,
STD7 accepts the _A0 signal at the timing of CP-1(S), and sets _STD0 to "H" at CP-3(S).
At this time, the input _IN1 of the NAND gate 13 in FIG. 5 becomes "H". The input IN ₂ of the NAND gate 13 is
The E ₀ signal is already “H” and the input IN ₃ is
It is connected to the output of NAND gate 11,
The input IN ₂ of the NAND gate 11 is "L" at DUT ₀ (at this point, "L" as shown in FIG. 6C),
And since input IN ₁ (STD ₀ ) is “H”, “H”
It is. Therefore, when STD ₀ becomes “H”,
The output of NAND gate 13 becomes “L”, and CK
Stop the (S) signal. PUT6 sends _A0 signal to CP-
At timing 1(D), DUT ₀ is set to "H" at reception CP-3(D). During this time, a phase difference of td occurs between STD ₀ and the DUT. When PUT ₀ becomes “H”
The input IN ₂ of the NAND gate 11 becomes "H" and its output becomes "L", so the NAND gate 1
The output of 3 becomes "H" and the CK (S) signal is recovered. Due to this operation, two clocks are missed from the clock signal CK(S) as shown in FIG. 6B. In the example shown in FIG. 6, the omission of these two clocks causes a difference in the timing of the output STD ₀ of STD 7 before and after synchronization.

That is, before CP-1(S) is synchronized, it is CP-2.
The output timing was the same as (D), but after synchronization, the timing becomes the same as that of CP-1 (D), and synchronization will be performed. Synchronization signal E ₀ is “L”
By doing so, NAND gate 1 in FIG.
The outputs of 2 and 13 are set to "H", and the inputs IN ₁ , IN ₂ of the NAND gate 11 forming the synchronization circuit are
Input IN ₁ , input IN ₃ of NAND gate 12 and
Input IN ₁ and input IN ₃ of NAND gate 13 are disabled to complete synchronization. After this, I will be a clotsuku.
CK(S) and CK(D) are exactly the same signals as the clock signal CK applied to the terminal 16. Next, the case where STD ₀ and DUT ₀ are set to “H” again with A ₀ input is also shown in Figure 6 B and C, but at this point synchronization is completed and the output of STD ₀ and DUT ₀ is The timing is perfect.

Above, the STD side receives the input pattern first,
We explained that the CK(S) clock is stopped by the output STD ₀ , and the CK(S) is restored by operating the output DUT ₀ on the DUT side to achieve synchronization. CK also in case of combination
Although the way the (S) or CK(D) signal is thinned out is different, synchronization can be achieved in the same way.

By the way, in order to improve measurement efficiency, it is common practice to speed up the clock CK.
Generally, the output signal appears later than CP-3.
The degree of delay is unique to each multiphase clock element and does not depend on the period of the clock CK. In this case, the polyphase clock CP-1,
The above synchronization method cannot be applied because of delays that occur between CP-2 and CP-3 and the STD and DUT outputs, which vary from element to element. This situation can be seen in the seventh
As shown in the figure.

In Figure 7B, the DUT side output is a multiphase clock CP-3.
It shows how tcp-A rises later than in (D).
Next, the STD side output is multiphase clock CP-3(S)
FIG. 7A shows how TCP-C rises later than TCP-C.
In this explanation, tcp-A, tcp-C and clock
Between the frequency of CK and fck, tcp-A>1/fck, tcp
-C<1/fck, i.e. tcp-A is the clock
The following description will be made on the assumption that the relationship holds that tcp-C is longer than one clock time of clock CK and shorter than one clock time of clock CK.

First, let's explain from the DUT side. If the synchronization circuit has the configuration shown in Figure 5, the tcp-A time is large, so
The operation of the NAND gate 12 is delayed by that amount, and part b of the CK(D) signal in Figure 7B cannot be thinned out.
Thin out only the number of minutes. For this reason, the polyphase clock CP−
The phase of the output of 1(D) is shifted by one clock. At this point, there is almost no phase difference between the STD and DUT outputs, but after synchronization the next outputs will be “H” and “L”.
When receiving the input signal, a delay td occurs, making it impossible to perform the synchronization required for measurement using the comparison method. This means that as the frequency increases, clocks CP-1 to CP-3 and STD,
The delay between the DUT outputs becomes relatively noticeable, and eventually this delay exceeds one clock time of clock CK, indicating that synchronization using the method described above is no longer possible.

FIG. 8 is a diagram showing the configuration of a measuring device having a synchronization circuit that can eliminate the above-mentioned disadvantages that occur when the clock CK is increased in speed in this manner. This measuring device is a D flip-flop 20
The configuration differs from the measuring device shown in FIG. 5 in that a circuit section 23 consisting of AND gates 21 and 22 is added.

The circuit section 23 in FIG. 8 is a 1/2 frequency divider circuit, and is an example in which the clock CK is set to 1/2. If the clock CK is set to 1/n, a 1/n frequency dividing circuit is naturally required.

This will be explained below with reference to the timing diagram of FIG. In the measuring device shown in FIG. 8, the D input terminal of the D flip-flop 20, which is a component of the circuit section 23, is connected to the output terminal of an AND gate 21, which receives the synchronization signal _E0 and the output of the D flip-flop 20. ing. E ₀ at the start of synchronization
When the signal becomes "H", the output of the D flip-flop 20 is "L", so the input to the D input terminal becomes "L". Therefore, its output Q changes from "H" to "L" upon receiving the next clock CK.
Therefore, the output changes from "L" to "H".

In this way, the signal generated at the output terminal of the AND gate 22 while the synchronization signal _E0 is "H"
CKX has half the frequency of clock CK. 9th
Figure B shows this situation.

Next, the execution of synchronization will be explained. STD
The side first receives the A ₀ signal at the timing of CP-1 (S), and is delayed by tcp-C1 from CP-3 (S).
Output to STD ₀ . At the same time, stop CK(S). Next, the DUT side similarly receives the _A0 signal at the timing of CP-1(D), outputs it to DUT ₀ with a delay of tcp-A1 from CP-3(D), and at the same time releases the clock stop of CK(S). , complete the synchronization. clock
Since CK(S) and CK(D) have half the frequency of clock CK during this time, even if the delay time tcp-C1 is greater than one clock time of clock CK,
As explained with reference to Figure 7, the clock CK
There is no mistake in thinning out (S), and the multiphase clocks CP-1(S) to CP-3(S) and CP-1(D) input to DUT6 and STD7 at the time of synchronization completion
The phases of ~CP-3(D) match perfectly.

Next, after the synchronization is completed, when the output is controlled again by the A ₀ signal, a delay time difference of Td ₁ occurs between DUT ₀ and STD ₀ as shown in FIG. 9C. This delay time difference is expressed by the following equation.

td=|tcp−C1|−|tcp−A1| Therefore, td ₁ is expressed as the difference between the output delay amounts of STD 7 and DUT 6. This delay time difference cannot be eliminated in principle because it is a difference in the inherent delay of each multiphase clock.Therefore, when comparing STD and DUT outputs, CP-3 is used as a judgment signal.
Pass/fail judgments can be made by finding the timing at which equally stable judgments can be made.

In this way, when the speed of the clock CK is increased, the problem of not being able to synchronize due to the delay in output timing is solved, and the speed of measurement can be increased.

As is clear from the above explanation, according to the measurement method of the present invention, it is extremely easy to synchronize using the measurement method by comparing the standard element and the device under test in a multiphase clock element, and it is possible to perform measurements using the comparison method. This increases the measurable frequency range and improves accuracy. It is also possible to reduce the cost and measurement time of a multiphase clock element measuring device. Furthermore, it goes without saying that the present invention is also applicable to synchronization of two or more.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an example of an operating circuit of a multi-phase clock element, Fig. 2 is a diagram showing the situation of multi-phase (N-phase) clock generation, and Fig. 3 is a diagram showing the input/output signals of a three-phase clock element and the three-phase clock. a timing diagram showing the relationship;
Fig. 4 is a timing diagram illustrating the operating status of a three-phase clock element, Fig. 5 is a block diagram showing the configuration of a measuring device that enables the measurement method of the present invention, and Fig. 6 shows how synchronization is executed. Timing diagram, 7th
The figure is a timing diagram showing a situation in which synchronization becomes impossible under a high-speed clock, Figure 8 is a block diagram showing the configuration of a measuring device that allows synchronization under a high-speed clock, and Figure 9 is a diagram showing the configuration of a measuring device that can perform synchronization under a high-speed clock. FIG. 1, 8, 9...multiphase clock generation circuit, 2,
6, 7... polyphase clock element, 3... switch,
4...Input pattern generation circuit, 5...Output circuit,
10... Output comparison circuit, 11, 12, 13...
NAND gate, 14, 15, 21, 22...
AND gate, 16...clock pulse application terminal,
17... Application terminal for synchronization control signal, 18...
Match signal output terminal, 19... Mismatch signal output terminal, 22... D flip-flop.

Claims (1)

[Claims] 1. A first polyphase clock element as a standard product and a second polyphase clock element to be measured are prepared, and an output generation pattern generated by a pattern generation circuit is applied to the input terminals of both. and the output of the first polyphase clock signal generation circuit which is driven by clock pulses of the same phase of both clock pulses and generates a polyphase clock signal for a standard polyphase clock element, and the polyphase clock element under test. A multiphase clock signal generation circuit that generates an output by separately supplying the output of a second multiphase clock signal generation circuit that generates a multiphase clock for each clock, and also drives the multiphase clock element on the side where the same output is generated earlier. The clock pulses supplied to the circuit are thinned out until the output is generated from the multi-phase clock element on the side that generates the output slowly, and when the outputs from both multi-phase clock elements are aligned, the first and second multi-phase clock signals are processed. A method for measuring a polyphase clock element, which comprises returning the clock pulses supplied to a generating circuit to normal, and then comparing the outputs from both polyphase clock elements. 2. When the phase difference between the multiphase clock element output and the multiphase clock is one cycle or more of the clock signal, the clock signal frequency is reduced by 1/2 only during the synchronization period.
2. The method for measuring a multiphase clock element according to claim 1, wherein the measuring method is performed by reducing the clock frequency to n (n=1, 2, 3, . . . ).