JPH0392085A - Synchronizing separator circuit - Google Patents

Abstract

PURPOSE:To attain stable synchronizing separation with high accuracy even when a video signal having fluctuation of APL(Average picture level) or noise is inputted by extracting an edge part of a synchronizing signal with a filter and using a pulse corresponding to the edge to form the synchronizing signal again. CONSTITUTION:The circuit is provided with an amplifier 8, a clamp circuit 9, a clip circuit 10, a high pass filter 11, a low pass filter 12, a slice circuit 13, a waveform shaping circuit 14 and a bistable multivibrator circuit 15. Then a video signal portion is clipped and the high pass filter 11 and the low pass filter 12 extracts the edge of the synchronizing signal and the slice circuit 13 eliminate noise and the pulse corresponding to the edge reconstitutes the synchronizing signal. Thus, accurate synchronizing separation is attained even when the APL is fluctuated and the synchronizing signal separator circuit stable against noise is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronization signal separation circuit that separates a synchronization signal from a composite video signal. [Prior Art] Generally, when mixing and combining two video signals, it is necessary to synchronize the two video signals. In this way, to determine whether or not the phases match, the synchronization signal is separated from the video signal and phase comparison is performed, but in order to speed up the phase comparison, the video signal supplied to the synchronization signal separation section is The response speed of the DC clamp must be fast.
Especially AP L (Average picture l
If video signals with different levels (evel) are switched, misclamping will occur for several H, making it impossible to separate the synchronization signals. Figure 4 shows a conventional device of this type. In the figure, 1 is the input terminal for the video/false signal;
A video signal without DC clamping as shown in FIG. 5(a) is supplied, and the capacitor CI% resistor R. R
The video signal is DC clamped by a peak clamp circuit consisting of a TS diode 2 and a constant voltage source 6, resulting in the waveform shown in FIG. 5(b). 4 is a DC clamped video signal and a variable resistor VR. This is a differential amplifier that compares the potentials and separates the synchronization signal using the potential determined by
Reference numeral 5 denotes an output terminal to which the synchronizing signal separated from the video signal by the differential amplifier 4 is output, and generates the output shown in FIG. 5(C). Next, we will explain the operation. In a state where the video signal shown in FIG. 5(a) is supplied to the input terminal l,
T, the peak potential of the video signal is approximately equal to the sum of the electromotive force of the constant voltage source 6 and the forward potential of the diode 2 (hereinafter referred to as clamp potential). Next, AP
When the T1 part of the low L signal is switched to the Tt part of the APL high signal, the input terminal 3 of the differential amplifier 4 temporarily becomes a potential higher than the clamp potential, and a forward potential is applied to the diode 2. Therefore, the diode 2 has a low impedance. Resistance R, is diode 2 at that time
The impedance of the resistor R8 is R, and Rx<R+, and the charging voltage at this time is the impedance of the resistor R!
The peak potential of the video signal gradually becomes the clamp potential. Next, when the APL high signal T is switched to the AFL low signal T, the input terminal 3 of the differential amplifier 4 temporarily becomes a potential lower than the clamp potential, and the diode 2 has a reverse potential. is added, so Mohai diode 2 becomes high impedance.
This low potential is charged to the capacitor CI via the resistor R1 connected to the power supply VCe, and the peak potential of the video signal gradually becomes the clamp potential, but the R. )R. Therefore, it takes more time for the peak potential of the video signal to become equal to the clamp potential when switching from T to T than when switching from T1 to T2.

Therefore, when the synchronizing signal is separated by the differential amplifier 4, there is a drawback that it takes a long time to overcome the influence. Furthermore, if the resistor R1 is made smaller, the clamping speed becomes faster, but as is well known, the impedance of the resistor R to the capacitor C1 becomes lower, causing a sag in the video signal and deteriorating the synchronization signal separation performance. It is. When the video signal subjected to the DC clamp described above is added to the differential amplifier 4, the voltage is compared with the potential determined by the variable resistor VR, and the synchronization signal is separated and extracted, the result is as shown in Fig. 5, with different APLs. There are parts where the sync signal cannot be separated and extracted where the video signal is switched. Sometimes AFL
This phenomenon becomes more apparent when switching from the high T signal portion to the low APL signal T portion. [Problems to be Solved by the Invention] Since the conventional synchronization signal separation circuit is configured as described above, there are problems such as the inability to accurately extract the synchronization signal from a video signal whose APL changes. Ta. This invention was made to solve the above-mentioned problems, and aims to provide a synchronization signal separation circuit that can accurately separate synchronization signals even when the APL fluctuates, and is stable against noise. Suppose that [Means for Solving the Problems] The synchronization signal separation circuit according to the present invention clips the video signal portion, extracts the edge portion of the synchronization signal, removes noise, and then extracts the synchronization signal with a pulse corresponding to the edge portion. This made me reconsider my precepts. [Operation] The synchronization signal separation circuit of the present invention extracts the edge portion of the synchronization signal by the filter, and generates a synchronization signal again using pulses corresponding to this edge portion. [Example] An example of the present invention will be described below with reference to the drawings. In FIG. 1, 7 is the same composite video signal input terminal as 1 shown in FIG. 4, 8 is an amplifier, 9 is a clamp circuit, and 10
is a clip circuit, and 11 is a Takagi pass filter (hereinafter referred to as HPF).
), 12 is a low-pass filter (hereinafter referred to as LPF), 13 is a slice circuit, 14 is a waveform shaping circuit, and 15 is a bistable multi-vibrator circuit (Bistable Multi-V
ibrator (hereinafter referred to as BMV), 16 is a synchronization signal separation output terminal. Figure 2 shows A-G in Figure 1.
This is a diagram showing the waveforms of each part up to. When a composite video signal like A in FIG. 2 (same as a in FIG. 5) is input to the composite video signal input terminal 7 in FIG. 1,
The amplifier 8 amplifies the synchronizing signal part to a level greater than the required level, and inputs it to the next stage clamp circuit 9 (see Fig. 2A).
). This clamp circuit 9 is, for example, a circuit as shown in FIG. The clamp time constant consisting of is selected to be short enough to follow APL fluctuations for each horizontal period (hereinafter referred to as IH). Therefore, the video signal passing through this clamp circuit has sag (low-frequency distortion) as shown in FIG. 2B. However, since the time constant is small, the synchronization tip is clamped without causing extreme DC fluctuations due to APL fluctuations as in the conventional example (Fig. 5b). Next, for a signal with a sag as shown in FIG.
0 (this can be done using the differential amplifier 4 in Figure 4) to remove unnecessary video signals. This output signal waveform is shown in Figure 2C.
An enlarged view of the horizontal synchronization signal part is shown in C'. When this C or C' signal is input to }IPFII,
The low-frequency component is removed, and the high-frequency component of the residual video signal, the edge portion of the synchronization signal, and the noise component are output (Figure 2D). In Fig. 2D, the rising edge (α) of the synchronization signal
, the amplitude of the pulse corresponding to the falling edge (β) is larger than the high-frequency component and random noise component of the video signal because the clip circuit 10 suppresses the video signal to be smaller than the synchronization signal amplitude. ．． When this D signal passes through LPF 1 2, some of the noise distributed in the high range is further attenuated, and E
Since the signal waveform is as follows, if the slice level of the slice circuit 13 is set as E, only the pulses corresponding to the rising and falling portions of the synchronization signal will be output (F). This slice circuit has a hysteresis (dead zone) characteristic, for example, as shown in Figure 3(a), and can be specifically avoided using an anti-parallel diode circuit as shown in Figure 3(b). Next, the signal F is input to the waveform shaping circuit 14. The waveform shaping circuit 14 includes a Schmitt circuit (not shown) that shapes an input signal into a rectangular wave, and a positive . It is composed of an absolute value circuit (not shown) that makes negative signals have the same polarity, and F
becomes a square wave pulse corresponding to the edge part of a synchronization signal like G. The bistable multivibrator 15 (flip-flop circuit) is driven by the pulse shown in G, and the interval between the pulses in G (corresponding to the width of the synchronization signal) is 16 in the same figure.
It generates a pulse like this. This becomes the synchronization signal separated from input signal 7. In addition, in the above embodiment, HPF
and LPF, but these may be replaced by bandpass filters.

Further, in the above embodiment, the slice level is applied to the video signal portion, but if the amount of sag is small, the slice level may be increased to the extent that the synchronization signal is reduced. [Effects of the Invention] As described above, according to the present invention, only the edge portion of the synchronization signal is extracted by the filter, so even if a video signal containing APL fluctuations or noise is input, highly accurate This has the effect of providing a stable synchronization signal separation circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a synchronization signal separation circuit according to an embodiment of the present invention, FIG. 2 is a waveform diagram at each part of FIG. 1, and FIG. 3 is a diagram showing a slice circuit according to an embodiment of the present invention. Figure 4 shows an example of a conventional synchronization signal separation circuit.
Figure 5 is an operating waveform diagram of the circuit shown in Figure 4. 9 is a clamp circuit, 10 is a clip circuit, 11 is a Takagi pass filter, 12 is a low pass filter, 13 is a slice circuit, and 5 is a bistable multivib break circuit.

Claims (1)

[Claims] (1) A clamp circuit that fixes the tip or pedestal portion of the synchronization signal in the composite video signal to a constant DC potential, and clips the video signal at a potential on the video signal side by a constant potential from the clamp potential of the clamp circuit. a clipping circuit; a filter means for removing low-frequency components and high-frequency components from the output signal of the clipping circuit; a slicing circuit for removing a signal with a small signal amplitude from the output signal of the filtering means; and the slicing circuit. 1. A synchronous signal separation circuit comprising: a bistable multivibrator circuit using an output signal as a trigger pulse.