JPH0392053U - - Google Patents

Info

Publication number
JPH0392053U
JPH0392053U JP71990U JP71990U JPH0392053U JP H0392053 U JPH0392053 U JP H0392053U JP 71990 U JP71990 U JP 71990U JP 71990 U JP71990 U JP 71990U JP H0392053 U JPH0392053 U JP H0392053U
Authority
JP
Japan
Prior art keywords
metal plate
chip
stage
resin
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP71990U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP71990U priority Critical patent/JPH0392053U/ja
Publication of JPH0392053U publication Critical patent/JPH0392053U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第1図は本考案の第1の実施例を示す図、第2
図は本考案の第2の実施例を示す図、第3図は従
来例の問題点を示す断面図、である。 図において、1……ICチツプ、2……ステー
ジ、2a……上部金属板、2b……下部金属板、
3……リード、4……ボンデイングワイヤ、5…
…モールド樹脂、6……パツケージクラツク、で
ある。

Claims (1)

  1. 【実用新案登録請求の範囲】 (1) ステージ2に固着されたICチツプ1を樹
    脂封止してなるICパツケージにおいて、 該ステージ2は、樹脂の充填された間隙を有し
    て対向する上部金属板2aおよび下部金属板2b
    からなることを特徴とするICパツケージ。 (2) 該下部金属板2bに複数の孔を設け該上部
    金属板2aにICチツプ1を固着したことを特徴
    とする請求項(1)記載のICパツケージ。
JP71990U 1990-01-09 1990-01-09 Pending JPH0392053U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP71990U JPH0392053U (ja) 1990-01-09 1990-01-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP71990U JPH0392053U (ja) 1990-01-09 1990-01-09

Publications (1)

Publication Number Publication Date
JPH0392053U true JPH0392053U (ja) 1991-09-19

Family

ID=31504660

Family Applications (1)

Application Number Title Priority Date Filing Date
JP71990U Pending JPH0392053U (ja) 1990-01-09 1990-01-09

Country Status (1)

Country Link
JP (1) JPH0392053U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007164741A (ja) * 2005-12-12 2007-06-28 Figla Co Ltd 建築現場の管理システム

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6482554A (en) * 1987-09-24 1989-03-28 Mitsubishi Electric Corp Resin-sealed semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6482554A (en) * 1987-09-24 1989-03-28 Mitsubishi Electric Corp Resin-sealed semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007164741A (ja) * 2005-12-12 2007-06-28 Figla Co Ltd 建築現場の管理システム

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