JPH0391257A - Semiconductor package - Google Patents
Semiconductor packageInfo
- Publication number
- JPH0391257A JPH0391257A JP1227521A JP22752189A JPH0391257A JP H0391257 A JPH0391257 A JP H0391257A JP 1227521 A JP1227521 A JP 1227521A JP 22752189 A JP22752189 A JP 22752189A JP H0391257 A JPH0391257 A JP H0391257A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- board
- thin film
- semiconductor
- ceramic substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 75
- 239000000919 ceramic Substances 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims description 31
- 239000010409 thin film Substances 0.000 claims description 29
- 230000017525 heat dissipation Effects 0.000 claims description 15
- 230000005855 radiation Effects 0.000 abstract description 10
- 238000007789 sealing Methods 0.000 abstract description 7
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 abstract description 4
- 239000000463 material Substances 0.000 abstract description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052721 tungsten Inorganic materials 0.000 abstract description 3
- 239000010937 tungsten Substances 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 238000005498 polishing Methods 0.000 abstract description 2
- 239000011347 resin Substances 0.000 abstract description 2
- 229920005989 resin Polymers 0.000 abstract description 2
- 229910000679 solder Inorganic materials 0.000 abstract description 2
- 238000005516 engineering process Methods 0.000 description 8
- 239000010408 film Substances 0.000 description 7
- 230000000694 effects Effects 0.000 description 3
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Abstract
Description
【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） 本発明は、半導体パッケージに関する。[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to semiconductor packages.
（従来の技術）
情報量の増大、需要の多様化に伴い、半導体装置の高密
度配線を行うためにパターン寸法が微細化し、さらに部
品の小型化が要求されている。(Prior Art) As the amount of information increases and demands diversify, pattern dimensions are becoming finer in order to perform high-density wiring of semiconductor devices, and further miniaturization of components is required.
パターン寸法が微細になると、僅かなじんあいでも半導
体チップに与える影響は大きく、このような外部環境か
らの保護や、取扱い上の安全のために、半導体チップを
封止部材で封止したパッケージとして用いることが多い
。As the pattern size becomes finer, even the slightest amount of dust has a greater effect on the semiconductor chip.In order to protect the semiconductor chip from the external environment and ensure safe handling, the semiconductor chip is sealed with a sealing material and used as a package. There are many things.
半導体パッケージの構造には種々のものが知られており
、たとえば配線基板の配線を薄膜技術によって形成した
ものと、あるいは厚膜技術によって形成したものとに分
けることができる。Various semiconductor package structures are known, and for example, the wiring of a wiring board can be divided into those formed using thin film technology and those formed using thick film technology.
第２図は、薄膜技術を用いた従来の半導体パッケージで
ある。FIG. 2 shows a conventional semiconductor package using thin film technology.
同図において、セラミックス基板１には、半導体チップ
２が塔載され、半導体チップ２の周囲には薄膜技術によ
って配線パターン３が形成されている。この配線パター
ン３と半導体チップ２とはワイヤ４で結ばれ、両者が電
気的に接続されている。In the figure, a semiconductor chip 2 is mounted on a ceramic substrate 1, and a wiring pattern 3 is formed around the semiconductor chip 2 by thin film technology. The wiring pattern 3 and the semiconductor chip 2 are connected by a wire 4, and the two are electrically connected.
また、半導体チップ２が有する機能に応じて外部への接
続用リード５がセラミックス基板１の半導体チップ塔載
面に対する裏面に接合されている。Further, depending on the function of the semiconductor chip 2, external connection leads 5 are bonded to the back surface of the ceramic substrate 1 relative to the surface on which the semiconductor chip is mounted.
これらの接続用リード５がセラミックス基板１内部の内
部配線６を介して半導体チップ２と電気的に接続される
ことにより、甲導体チップの機能が発揮される。When these connection leads 5 are electrically connected to the semiconductor chip 2 via the internal wiring 6 inside the ceramic substrate 1, the function of the conductor chip A is exhibited.
そして、配線パターン３の外側すなわちセラミックス基
板１の最外周付近に、気密封止のための蓋部材７が接合
され、この蓋部材７上に放熱フィン８が取付けられてい
る。A lid member 7 for airtight sealing is bonded to the outside of the wiring pattern 3, that is, near the outermost periphery of the ceramic substrate 1, and a radiation fin 8 is attached to the lid member 7.
この放熱フィン８は、高密度化に伴って増大するチップ
部品からの発熱を放散させるためのものである。The heat dissipation fins 8 are for dissipating heat generated from chip components, which increases with increasing density.
薄膜技術によれば、１０〜２０μｍ程度の微細な配線を
パターニングできるため、１００μｍ程度のパターニン
グが限度である厚膜技術に比べて、高密度配線ができる
。According to thin film technology, fine wiring of about 10 to 20 μm can be patterned, so it is possible to achieve higher density wiring than thick film technology, which has a limit of patterning of about 100 μm.
このほか、従来の半導体パッケージとして厚膜技術を用
いた例を第３図に示す。In addition, FIG. 3 shows an example of a conventional semiconductor package using thick film technology.
第３図において、セラミックス基板１１上にはタングス
テン、モリブデンなどの厚膜導体ペーストをスクリーン
印刷によって形成した配線パターン１２が形成され、半
導体チップ１３と、接続用リード１４とが、配線パター
ン１２上の所定位置に接合塔載されている。In FIG. 3, a wiring pattern 12 is formed on a ceramic substrate 11 by screen printing a thick film conductive paste such as tungsten or molybdenum, and a semiconductor chip 13 and connection leads 14 are connected to each other on the wiring pattern 12. The joint is mounted in place.
配線パターン１２と半導体チップ１３とはワイヤ１５で
結ばれ、両者が電気的に接続されている。The wiring pattern 12 and the semiconductor chip 13 are connected by a wire 15, and the two are electrically connected.
さらに、半導体チップ１３は厚膜による配線パターン１
２を介して接続用リード１４と電気的に接続されている
。Further, the semiconductor chip 13 has a wiring pattern 1 made of a thick film.
It is electrically connected to the connection lead 14 via 2.
そして、この第３図の半導体パッケージでは、気密封止
用の蓋部材１６がはんだ付けなどでセラミックス基板１
１の半導体チップ１３塔載側の面に接合されている。In the semiconductor package shown in FIG. 3, the hermetic sealing lid member 16 is attached to the ceramic substrate by soldering or the like.
It is bonded to the surface on the side where the semiconductor chip 13 of No. 1 is mounted.
また、放熱フィン１７がセラミックス基板１１の裏面に
取付けられ、配線基板の温度上昇を防止している。Furthermore, a heat dissipation fin 17 is attached to the back surface of the ceramic substrate 11 to prevent the temperature of the wiring board from rising.
（発明が解決しようとする課題）
ところで、高密度化の進んだ半導体パッケージでは、チ
ップ部品からの発熱をいかに効率良く放散させるかとい
うことが、重要課題であり、これによって信頼性にも影
響が及ぶのである。(Problem to be solved by the invention) By the way, in semiconductor packages that have become highly dense, an important issue is how to efficiently dissipate heat generated from chip components, which also affects reliability. It extends.
このような熱放散のための放熱フィンの取付けは、本来
ならば半導体チップからの熱が伝わる最短距離である、
配線基板の半導体チップ塔載部に対する裏面に接合する
のが効率的である。The installation of heat dissipation fins for heat dissipation is normally the shortest distance for heat to travel from the semiconductor chip.
It is efficient to bond to the back surface of the wiring board with respect to the semiconductor chip mounting portion.
しかしながら、第２図のような半導体パッケージでは、
半導体チップとリードとが配線基板の表面と裏面とに別
々に存在するため、半導体チップ塔載部に対する裏面に
はリードとのぶつかりによって放熱フィンを取付けるこ
とが困難である。However, in a semiconductor package like the one shown in Figure 2,
Since the semiconductor chip and the leads are separately present on the front and back surfaces of the wiring board, it is difficult to attach a heat dissipation fin to the back surface relative to the semiconductor chip mounting portion due to collision with the leads.
また、半導体チップ塔載側の面は、蓋部材で覆われでい
るため、この蓋部材の上に放熱フィンを接合しなければ
ならないのである。Furthermore, since the surface on the side where the semiconductor chip is mounted is covered with a lid member, it is necessary to bond the heat dissipation fins onto the lid member.
すると、半導体チップからの熱は配線基板表面に沿った
横方向に拡散して、この配線基板外周に接合されている
蓋部材の脚部を通り、放熱フィンから放散されることに
なる。Then, the heat from the semiconductor chip is diffused in the lateral direction along the surface of the wiring board, passes through the legs of the lid member joined to the outer periphery of the wiring board, and is radiated from the heat radiation fins.
このような放散経路では、伝搬距離が長いうえに、蓋部
材の脚部は通常細いため、熱放散の効率が良くないとい
う問題がある。In such a dissipation path, there is a problem that the propagation distance is long and the legs of the lid member are usually thin, so that heat dissipation efficiency is not good.
また、第３図のような厚膜を用いた半導体パッケージで
は、放熱性は優れている反面、微細な配線パターンを形
成することができず、高密度化には適していない。Furthermore, although a semiconductor package using a thick film as shown in FIG. 3 has excellent heat dissipation, it cannot form fine wiring patterns and is not suitable for high density packaging.
さらに、配線が誘電率の高いセラミックス内部に多く形
成されているため、信号遅延が大きいという問題がある
。Furthermore, since many wiring lines are formed inside ceramics having a high dielectric constant, there is a problem that signal delay is large.
この信号遅延は、導電層によって形成される配線パター
ンに電流を流した場合、この電流は絶縁基板側に蓄えら
れた電荷を順次打消しながら流れて行くこととなり、こ
の打消しを行う充放電に余分な時間と電流が消費される
ために生じるものであり、回路全体としての作動速度の
高速化を妨げることになる。This signal delay is caused by the fact that when a current is passed through the wiring pattern formed by the conductive layer, the current flows while sequentially canceling out the charge stored on the insulating substrate side, and the charge/discharge process that cancels out the charge This occurs because extra time and current are consumed, and this prevents the entire circuit from increasing its operating speed.
つまり、半導体パッケージにおける高密度配線、高速化
、そして高放熱性をいかに同時に実現させるかというこ
とが課題となっている。In other words, the challenge is how to simultaneously achieve high density wiring, high speed, and high heat dissipation in semiconductor packages.
本発明はこのような課題を解決するためになされたもの
で、より高密度配線パターンの形成が可能で、かつ、熱
放散性が高く、信号遅延が小さい半導体パッケージを提
供することを目的とする。The present invention was made to solve these problems, and an object of the present invention is to provide a semiconductor package that allows the formation of higher density wiring patterns, has high heat dissipation, and has low signal delay. .
［発明の構成］
（課題を解決するための手段）
本発明の半導体パッケージは、表裏両面に薄膜で配線パ
ターンが形成され、これら両面の配線パターンがスルー
ホールで電気的に接続されているセラミックス基板と、
このセラミックス基板の一方の配線面に塔載され、前記
薄膜配線パターンと電気的に接続されている半導体チッ
プと、この半導体チップとこの半導体チップ塔載面に形
成されている薄膜配線パターンとを気密封止する蓋部材
と、この蓋部材を除いた前記半導体チップ塔載面に前記
スルーホールと電気的に接続されるよう接合されたリー
ドと、前記セラミックス基板の他方の配線面に接合され
た放熱部月とを備えたことを特徴とするものである。[Structure of the Invention] (Means for Solving the Problems) The semiconductor package of the present invention comprises a ceramic substrate on which thin film wiring patterns are formed on both the front and back surfaces, and the wiring patterns on both sides are electrically connected through through holes. and,
The semiconductor chip mounted on one wiring surface of the ceramic substrate and electrically connected to the thin film wiring pattern, and the semiconductor chip and the thin film wiring pattern formed on the semiconductor chip mounting surface. A lid member for sealing, a lead joined to the semiconductor chip mounting surface excluding the lid member so as to be electrically connected to the through hole, and a heat dissipation jointed to the other wiring surface of the ceramic substrate. It is characterized by having a part and moon.
（作 用）
本発明の半導体パッケージは、セラミックス基板の両面
に薄膜で回路パターンを形成しているため、より高密度
回路パターンを形成することができる。(Function) Since the semiconductor package of the present invention has circuit patterns formed with thin films on both sides of the ceramic substrate, a higher density circuit pattern can be formed.
特に、塔載した半導体チップの周囲に狭ピッチの配線パ
ターンを形成することができ、多ピン化を図ることがで
きる。In particular, it is possible to form a wiring pattern with a narrow pitch around the mounted semiconductor chip, and it is possible to increase the number of pins.
また、この両面のうち、半導体チップ塔載面倒の薄膜パ
ターンを半導体チップの周囲部分のみに形成して、半導
体チップ塔載面とは反対の面に形成された薄膜パターン
とスルーホールによって電気的接続を行っているため、
厚膜回路に比べて静電容量が小さくなり、不必要な充放
電が減少するため、信号遅延を大きく減少させさること
ができる。In addition, a thin film pattern that is troublesome for mounting the semiconductor chip on both sides is formed only on the peripheral portion of the semiconductor chip, and electrical connection is made with the thin film pattern formed on the opposite side from the surface on which the semiconductor chip is mounted through the through hole. Because we are doing
Compared to thick film circuits, the capacitance is smaller and unnecessary charging and discharging is reduced, so signal delay can be greatly reduced.
そして、この半導体チップ周囲に形成された薄膜回路パ
ターンの外側に蓋部材を接合して気密封止を行い、同一
面における蓋部材の外側にリードを接合することによっ
て、半導体チップ塔載面の反対側の面がフリーとなり、
ここに放熱フィンを取付けることが可能となる。Then, by bonding a lid member to the outside of the thin film circuit pattern formed around the semiconductor chip to perform airtight sealing, and by joining leads to the outside of the lid member on the same surface, The side surface becomes free,
It is possible to attach heat dissipation fins here.
つまり、半導体チップからの発熱が効率良く放熱フィン
に伝達されるため、熱抵抗を低減することができる。In other words, heat generated from the semiconductor chip is efficiently transferred to the heat radiation fins, so that thermal resistance can be reduced.
（実施例） 次に、本発明の実施例について図面を用いて説明する。(Example) Next, embodiments of the present invention will be described using the drawings.
第１図は本発明による一実施例の半導体パッケージの断
面図である。FIG. 1 is a sectional view of a semiconductor package according to an embodiment of the present invention.
同図において、窒化アルミニウムからなるセラミックス
基板３１の一方の表面３１ａ側には、表面中央部に半導
体チップ３２が固定接合され、半導体チップ３２の周囲
には薄膜回路３３ａが形成されている。In the figure, a semiconductor chip 32 is fixedly bonded to one surface 31a side of a ceramic substrate 31 made of aluminum nitride at the center of the surface, and a thin film circuit 33a is formed around the semiconductor chip 32.
これら半導体チップ３２と、薄膜回路３３ａとは、ＴＡ
Ｂ技術を用いてＴＡＢ用リード３４により接続されてい
る。These semiconductor chips 32 and thin film circuits 33a are
They are connected by TAB leads 34 using B technology.
また、この表面３１ａの薄膜回路３３ａの外側には、半
導体チップ３２と薄膜回路３３ａとを覆うように蓋部材
３５が接合され、これらを気密封止している。Further, a lid member 35 is bonded to the outside of the thin film circuit 33a on the surface 31a so as to cover the semiconductor chip 32 and the thin film circuit 33a, thereby hermetically sealing them.
さらに、セラミックス基板３１の裏面３１ｂ側には、裏
面中央部に放熱フィン３６が、表面３１ａ側の半導体チ
ップ３２の真下に位置するよう取付けられている。Furthermore, a radiation fin 36 is attached to the back surface 31b side of the ceramic substrate 31 at the center of the back surface so as to be located directly below the semiconductor chip 32 on the front surface 31a side.
放熱フィン３６の周囲には、裏面３１ｂ全面にわたって
薄膜回路３３ｂが形成され、セラミックス基板３１を貫
通するスルーホール３７を介して表面３１ａ側の薄膜回
路３３ａと、電気的に接続されている。A thin film circuit 33b is formed around the radiation fin 36 over the entire back surface 31b, and is electrically connected to the thin film circuit 33a on the front surface 31a side through a through hole 37 penetrating the ceramic substrate 31.
そして、表面３１ａにおいては、蓋部材３５の外側周囲
には、セラミックス基板３１の裏面３１ｂ側の薄膜回路
３３ｂへと続くスルーホール３７のそれぞれの位置に、
外部接続用リード３８が接合されている。On the front surface 31a, on the outer periphery of the lid member 35, at each position of the through hole 37 that continues to the thin film circuit 33b on the back surface 31b side of the ceramic substrate 31,
An external connection lead 38 is joined.
すなわち、まとめて言うと、セラミックス基板の一方の
表面には、半導体チップと薄膜回路が気０
密封化され、かつ、気密封止されていない部分に外部接
続用リードが接合されている。そして、このセラミック
ス基板の裏面には、半導体チップの真下部分に放熱フィ
ンが接合され、残りの部分には薄膜回路が形成されてい
る。これらセラミックス基板両面の薄膜回路同士はスル
ーホールで電気的に接続されている。That is, to summarize, a semiconductor chip and a thin film circuit are air-tightly sealed on one surface of the ceramic substrate, and external connection leads are bonded to the portion that is not air-tightly sealed. Then, on the back surface of this ceramic substrate, a radiation fin is bonded directly below the semiconductor chip, and a thin film circuit is formed in the remaining part. The thin film circuits on both sides of these ceramic substrates are electrically connected to each other through through holes.
このような半導体パッケージはたとえば次のようにして
作製される。Such a semiconductor package is manufactured, for example, as follows.
はじめに、窒化アルミニウムのグリーンシートにスルー
ホールを穿設し、スルーホール内にタングステンペース
トを充填する。First, a through hole is drilled in an aluminum nitride green sheet, and the through hole is filled with tungsten paste.
グリーンシートには、電源、接地層用の所定のパターン
を形成して、これらを積層、焼成し、セラミックス基板
を得る。Predetermined patterns for power supply and ground layers are formed on the green sheet, and these are laminated and fired to obtain a ceramic substrate.
このセラミックス基板の表面を研磨加工した後、スパッ
タリングによって薄膜を形成し、フォトレジストを用い
てエツチングを行い、所定の回路パターンを形成する。After polishing the surface of this ceramic substrate, a thin film is formed by sputtering, and etching is performed using a photoresist to form a predetermined circuit pattern.
薄膜の材料としては、信号伝搬速度を考慮すると、セラ
ミックスより誘電率の１
小さいものが好ましく、たとえばポリイミドなどを用い
る。Considering the signal propagation speed, the material for the thin film is preferably one having a dielectric constant 1 smaller than ceramics, such as polyimide.
また、半導体チップをセラミックス基板の中央部分に共
晶などにより固定接合する。Further, the semiconductor chip is fixedly bonded to the center portion of the ceramic substrate using eutectic or the like.
そして、半導体チップと、その周囲の薄膜回路パターン
とを、ＴＡＢにより接続し、この周囲の薄膜回路パター
ンの外側には、蓋部祠をシーム溶接やガラスシールなど
でセラミックス基板と接合して、半導体チップの気密封
止を行う。Then, the semiconductor chip and the surrounding thin film circuit pattern are connected by TAB, and on the outside of this surrounding thin film circuit pattern, a lid part is joined to the ceramic substrate by seam welding or glass sealing, etc. The chip is hermetically sealed.
さらに、半導体チップ塔載面において、上述した蓋部材
の外側には、リードを銀ろうなとで接続する。Further, on the semiconductor chip mounting surface, leads are connected to the outside of the above-mentioned lid member using silver solder.
一方、半導体チップ塔載面の裏側の面には、半導体チッ
プ塔載位置から最も短い距離となるように取付は位置を
設定して、放熱フィンを熱伝導性樹脂を用いてセラミッ
クス基板上に接合する。On the other hand, on the back side of the semiconductor chip mounting surface, the mounting position is set so that it is the shortest distance from the semiconductor chip mounting position, and the radiation fin is bonded to the ceramic substrate using thermally conductive resin. do.
こうして、第１図に示すような半導体パッケージが作製
される。In this way, a semiconductor package as shown in FIG. 1 is manufactured.
この実施例による半導体パッケージでは、高密度配線、
多数のピンの接合を行うことができると２
同時に、放熱フィンを最も効率の良い位置に取付けるこ
とができた。In the semiconductor package according to this embodiment, high-density wiring,
By being able to join a large number of pins, we were also able to install the heat dissipation fins in the most efficient position.
なお、上述した半導体パッケージは、使用するセラミッ
クス基板として窒化アルミニウムに限らず、アルミナな
どを用いても同様の効果が得られることはもちろんであ
る。Note that, in the above-described semiconductor package, the ceramic substrate used is not limited to aluminum nitride, and the same effect can be obtained even if alumina or the like is used.
［発明の効果コ
以上説明したように、本発明の半導体パッヶジは、セラ
ミックス及板の両面に薄膜回路を形成し、両面間をスル
ーホールで電気的に接続しているため、信号遅延を防止
し、高速化を図ることができる。[Effects of the Invention] As explained above, the semiconductor package of the present invention has thin film circuits formed on both sides of a ceramic plate and electrically connects the two sides with through holes, thereby preventing signal delays. , speeding up can be achieved.
さらに、半導体チップとリードとを基板の同一面上に接
合することによって、放熱フィンを最も効率の良い位置
に取付けることができる。Furthermore, by bonding the semiconductor chip and the leads on the same surface of the substrate, the radiation fins can be attached at the most efficient position.
したがって、高密度配線、高速性、高放熱性を兼備えた
半導体パッケージを得ることができる。Therefore, it is possible to obtain a semiconductor package that has high density wiring, high speed, and high heat dissipation.
第１図は本発明の一実施例の半導体パッケージを示す図
、第２図および第３図は従来の半導体バ ３
ッケージを示す図である。
３１・・・・・・・・・セラミックス基板３１ａ・・・
・・・セラミックス基板表面３１ｂ・・・・・・セラミ
ックス基板裏面３２・・・・・・・・・半導体チップ
３３ａ−，３３ｂ・・・・・・薄膜回路３４・・・・・
・・・・ＴＡＢ用リード３５・・・・・・・・・蓋部材
３６・・・・・・・・・放熱フィン
３７・・・・・・・・・スルーホールFIG. 1 shows a semiconductor package according to an embodiment of the present invention, and FIGS. 2 and 3 show conventional semiconductor packages. 31...Ceramics substrate 31a...
Ceramic substrate front surface 31b Ceramic substrate back surface 32 Semiconductor chips 33a-, 33b Thin film circuit 34
..... TAB lead 35 ..... Lid member 36 ..... Radiation fin 37 ..... Through hole
Claims (1)
ら両面の配線パターンがスルーホールで電気的に接続さ
れているセラミックス基板と、 このセラミックス基板の一方の配線面に塔載され、前記
薄膜配線パターンと電気的に接続されている半導体チッ
プと、 この半導体チップとこの半導体チップ塔載面に形成され
ている薄膜配線パターンとを気密封止する蓋部材と、 この蓋部材を除いた前記半導体チップ塔載面に前記スル
ーホールと電気的に接続されるよう接合されたリードと
、 前記セラミックス基板の他方の配線面に接合された放熱
部材と を備えたことを特徴とする半導体パッケージ。(1) A ceramic substrate on which thin film wiring patterns are formed on both the front and back surfaces, and the wiring patterns on both sides are electrically connected through through holes; a semiconductor chip that is electrically connected to the pattern; a lid member that hermetically seals the semiconductor chip and a thin film wiring pattern formed on a surface on which the semiconductor chip is mounted; and the semiconductor chip excluding the lid member. A semiconductor package comprising: a lead bonded to a mounting surface so as to be electrically connected to the through hole; and a heat dissipation member bonded to the other wiring surface of the ceramic substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1227521A JPH0391257A (en) | 1989-09-04 | 1989-09-04 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1227521A JPH0391257A (en) | 1989-09-04 | 1989-09-04 | Semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0391257A true JPH0391257A (en) | 1991-04-16 |
Family
ID=16862208
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1227521A Pending JPH0391257A (en) | 1989-09-04 | 1989-09-04 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0391257A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5543663A (en) * | 1993-12-27 | 1996-08-06 | Kabushiki Kaisha Toshiba | Semiconductor device and BGA package |
| US5805427A (en) * | 1996-02-14 | 1998-09-08 | Olin Corporation | Ball grid array electronic package standoff design |
-
1989
- 1989-09-04 JP JP1227521A patent/JPH0391257A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5543663A (en) * | 1993-12-27 | 1996-08-06 | Kabushiki Kaisha Toshiba | Semiconductor device and BGA package |
| US5805427A (en) * | 1996-02-14 | 1998-09-08 | Olin Corporation | Ball grid array electronic package standoff design |
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