JPH0390930A - Digital comparator - Google Patents

Abstract

PURPOSE:To obtain a digital comparator which has a small circuit scale and the short deciding time by deciding two optional data lengths without converting the difference of value and the coincidence between the same serial bit data into the parallel bit data. CONSTITUTION:A digital comparator consists of a discordance detection means 1, a large decision means 2, a small decision means 3, the decision signal pass inhibition means 4 and 5, the latch means 6 and 8, the self-latch means 7 and 9, and a coincidence detection means 10. Then the difference of value and the coincidence are decided for each it between two serial n-bit data D1 (IN) and D2 (IN). Thus no conversion is required into the parallel bit data. Thus the circuit scale can be reduced and at the same time the data can be decided at a high speed.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention is a digital technology that determines the magnitude and coincidence of two arbitrary serial n-bit data of the same data length that are input sequentially starting from the MSB (most significant bit). It concerns expression comparators.

(Prior Art) Conventionally, in this type of digital converter, in order to determine the magnitude and coincidence of two serial n-bit data of the same data length, the serial n-bit data is first converted into parallel n-bit data. It is common to then determine their size and match.

(Problem to be solved by the invention) However, in the conventional digital comparator as described above, serial n-bit data is converted into parallel n-bit data.
Since the parallel n-bit data is converted into bit data and the magnitude and coincidence of the parallel n-bit data is determined, the circuit scale becomes large and the time required to determine the magnitude and coincidence is also long.

The present invention has been made in view of these problems, and an object of the present invention is to provide a digital comparator with a small circuit scale and a short determination time.

[Means for Solving the Problems] The digital comparator of the present invention is configured as follows.

a. Discrepancy detection that detects discrepancies between the two serial bit data bit by bit in a digital comparator that determines the magnitude and coincidence of two arbitrary serial bit data of the same data length that are input sequentially starting from the most significant bit. a dog determining means for outputting a large determination signal when one bit data is larger than the other bit data based on the output of the mismatch detecting means; a small determination means for outputting a determination signal; a determination signal passage prohibition means for prohibiting the passage of the determination signals after determination of the magnitude thereof; and a latch means for holding the magnitude determination signal from the determination signal passage prohibition means. and a coincidence detection means for detecting coincidence of the bit data from the output of the latch means, and a signal for determining the magnitude and coincidence of the two serial bit data is outputted through the latch means and the coincidence detection means. .

b. In the digital comparator of a above, the large/small judgment signal passage inhibiting means is provided between the large judgment means, the small judgment means, and the latch means for holding each judgment signal.

C0 In the digital comparator of a or b above, the coincidence detection means is an AND gate that uses the negative output of the latch means that holds the large judgment signal and the negative output of the latch means that holds the small judgment signal as human signals. did.

(Function) In the digital comparator of the present invention, the magnitude and coincidence of two serial bit data are determined and detected for each bit, and there is no need to convert it into parallel bit data.

〔Example〕

FIG. 1 is a block diagram showing the configuration of a digital comparator according to an embodiment of the present invention, in which DI (IN) and D2 (IN) are any serial numbers with the same data length input sequentially from the MSB. It shows n-bit data.

In the figure, 1 indicates these serial n-bit data Di (
IN), D2 (IN) manually and detects the mismatch between the serial n-bit data Di (IN) and D2 (IN) bit by bit; 2.3 is based on the output of the mismatch detection means; In the large judgment means and small judgment means for judging the magnitude of the above two data, the large judgment means 2 compares the serial n-bit data DI(IN) and D2(IN) and selects one bit data DI(IN). ) is larger than the other bit data D2 (IN), a large judgment signal is output, and the small judgment means 3 outputs the -・ bit data D1 (I
When the bit data D2 (IN) is smaller than the other bit data D2 (IN), a small determination signal is output. 4 inputs the judgment signal from the above-mentioned large judgment means 2, and - if the heating judgment means 2 outputs a judgment result of large or the small judgment means 3 outputs a judgment result of small, the subsequent large or small Judgment signal passage prohibition means for prohibiting the passage of the judgment signal of 5, 5 is the judgment from the judgment means 3 of small Judgment signal passage prohibition means for prohibiting the passage of subsequent large and small judgment signals when the judgment means 2 outputs a judgment result of large; 7 is a self-latch means for re-inputting the output of the latch means 6 into the latch means 6; 8 is a latch for manually inputting a small judgment signal from the judgment signal passage inhibiting means 5 and holding the data; The means 9 outputs the output of the latch means 8 to the latch means 8.
self-latching means 10 for re-inputting the latching means 6;
and the output of the latch means 8 (3, M- to two serial n
Coincidence detection means detects coincidence between bit data D1 (IN) and 02 (IN), and outputs a judgment signal of magnitude and coincidence of two serial n-bit data through the latch means 6, 8 and this coincidence detection means 10. Ru.

Moreover, apl is the output of the latch means 6, and the serial n
H when bit data is Di (IN) > Dl (IN)
(high) level. o p 2' is the output of the latch means 8, and the serial n-bit data is DI (IN) <
When Dl (IN), it becomes H level. Further, op3 is the output of the coincidence detection means 10, and becomes H level when serial n-bit data Dl(IN)=D2(IN).

As shown in the figure, judgment signal passage inhibiting means 4.5 are provided between the magnitude judgment means 2.3 and the latch means 6, 8 for holding the respective judgment signals.

FIG. 2 is a circuit diagram showing a specific example of the circuit shown in FIG. 1. In the figure, Gi is a two-man exclusive OR gate constituting the discrepancy detection means 1, and the serial n-bit data D (IN) and D
2CIN) manually, and the serial n-bit data DI
When (IN) and Dl (IN) do not match, an H level signal is output. G2 is a two-manual AND gate that constitutes the dog determination means 2, which manually inputs the output of the two-man exclusive OR gate G1 and the serial n-bit data DI (IN), and MS
Di (IN) for each bit data manually inputted sequentially from B.
>Dl (IN), an H level signal is output. G3 is a two-man-powered AND gate that constitutes the small determination means 3, which inputs the output of the two-man-powered exclusive OR gate G1 and serial n-bit data D2 (rN), and inputs the MSB
DI (IN) <
When the relationship Dl(IN) is established, an H level signal is output. G4 is a three-man-powered AND gate that constitutes the judgment signal passage prohibition means 4, which outputs the output of the two-man-powered AND gate G2, the Q output of a D-type FF (flip-flop) circuit FFI, which will be described later, and the Q output of the D-type FF circuit FF2. Once the magnitude relationship between the serial n-bit data Di(IN) and Dl(IN) is determined, the output of the two-manual AND gate G2 is prohibited from passing through. G5 is a three-man-powered AND gate that constitutes the judgment signal passage prohibition means 5, and a two-man-powered AND gate G3.
Output of Q output of D-type FF circuit FFI and D-type FF circuit F
Input the Q output of F2, and then input the serial n-bit data DI
Once the magnitude relationship between (IN) and Dl(IN) is determined, subsequent passage of the output of the two-manual AND gate G3 is prohibited. G
Reference numeral 6 denotes a two-manpower OR gate constituting the self-latch means 7, which connects the output of the three-manpower AND gate G4 and the D-type FF circuit FFI.
The Q output of is input manually to perform self-latching of the D-type FF circuit FFI. G7 is a two-man-operated OR gate constituting the self-latch means 9, which manually inputs the output of the three-man OR gate G5 and the Q output of the D-type FF circuit FF2, and performs self-latching of the D-type FF circuit FF2. In addition, the above-mentioned D-type FF circuits FFI and F
F2 is reset by the reset signal R, reads the state of the D input on the rising edge of the clock signal CK, and latches the result. G8 is a two-manual logical product constructing the coincidence detection means 10, and is the Q of the D-type FF circuits FFI and FF2.
When the output is manually performed and the serial n-bit data DI (IN) and 02 (IN) have a relationship of DI < IN) = D2 (IN), the output 0ρ3 becomes H level.

Also, serial n-bit data DI (IN) and Dl (
IN) or DI (IN) > Dl (IN), the output opl of the D-type FF circuit FFI becomes H level, and the serial n-bit data DI (IN) and Dl (IN)
is in the relationship Di (IN) < D2 (IN), then D
The output op2 of the type FF circuit FF2 becomes H level.

As shown in the figure, the two-manual AND gate G8 is connected to the FF circuits FFI and FF2 that constitute the latch means 6 and 8 in FIG.
A match is detected by inputting the negative output (Q output) of .

FIG. 3 is a timing diagram showing the operation of the circuit of FIG. 2. FIG. 3(a) shows that in two serial 10-bit data Di (IN) and 02 (IN) of data length A that are input sequentially from the MSB, from the third most significant bit to DI (
The relationship of IN)>D2 (IN) indicates that the Q output of the above-mentioned FF circuit FFI is maintained at either 0ρ1 or H level. FIG. 3(b) shows that in two serial 10-bit data Di (IN) and D2 (IN) that are input sequentially starting from the MSB, DI (I
N)<D2 (IN) indicates a state in which the Q output op2 of the above-described FF circuit FFI maintains the H level. Moreover, FIG. 3(C) shows two serial 10-bit data Di (I
N) and D2(IN), each bit is all DI(IN
)=D2 (IN) indicates that the output Oρ3 of the two-manual AND gate G8 maintains the H level.

In this way, in this embodiment, the magnitude and coincidence of the two serial n-bit data DI (IN) and 02 (IN) are determined and detected for each bit, so it is not necessary to convert them into parallel bit data. do not have. Therefore, it is possible to reduce the circuit scale, and also to perform high-speed determination, thereby shortening the determination time.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to determine the magnitude and coincidence of two serial bit data with the same arbitrary data length without converting them into parallel bit data, and the circuit configuration also allows two arbitrary data lengths to be determined. Since it can be configured with a latch circuit and a small number of logic gates, the circuit scale can be reduced, and size and match determinations can be made at high speed, resulting in the effect of shortening the determination time.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of the circuit in FIG. 1, and FIGS.
b) and (c) are timing diagrams showing the operation of the circuit of FIG. 2; DI (IN)... Serial n-bit data D2 (IN)... Serial n-bit data
... Discrepancy detection means 2 ... Dog judgment means 3 ... Small judgment means 45 ... Judgment signal passage prohibition lE means 6.8 ...
... Latch means 79 ... Self-latch means 10 ... Coincidence detection means

Claims (3)

[Claims] (1) In a digital comparator that determines the magnitude and match of two arbitrary serial bit data of the same data length that are input sequentially starting from the most significant bit, a mismatch is detected bit by bit between the two serial bit data. a detection means, a large judgment means for outputting a large judgment signal when one bit data is larger than the other bit data based on the output of the mismatch detection means, and a small judgment signal when one bit data is smaller than the other bit data. a small determination means for outputting a determination signal; a determination signal passage prohibition means for prohibiting the passage of the determination signals after determination of the magnitude; and a latch for holding the magnitude determination signal from the determination signal passage prohibition means. and a coincidence detection means for detecting coincidence of the bit data from the output of the latch means, and outputs a signal for determining the size and coincidence of the two serial bit data through the latch means and the coincidence detection means. A digital comparator with the following features. (2) The large/small judgment signal passing prohibition means is provided between the large judgment means, the small judgment means, and the latch means for holding each judgment signal.
Digital comparator as described. (3) The coincidence detection means is an AND gate whose input signals are a negative output of a latch means that holds a large judgment signal and a negative output of a latch means that holds a small judgment signal. The digital comparator according to item 1 or 2.