JPH11154868A - A/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform sorting processing at the same time as A/D conversion, without a dedicated sort circuit by storing the count value of a counter, when a comparator output is changed. SOLUTION: When a conversion start signal TS is inputted to a counter 4, the counter 4 starts to count up a clock, and a D/A converter 3 converts count up value into an analog value at each moment. Each comparator 11 to 14 compares each analog signal A1 to A4 with a conversion output of the converter 3 and when the output of the converter 3 exceeds each analog signal and comparator outputs change, it controls respective data latches 21 to 24 and latches the count up value of a counter 4 at that time. A microprocessor and software realize the functions of the counter 4 and the data latches 21 to 24, sorting is carried out at the same time as A/D conversion, and a conversion range and a sorting range can also be limited.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AD converter for converting an analog signal into a digital signal, and simultaneously converts a plurality of analog signals into a digital signal.
The present invention relates to an AD converter having a sorting function for sorting these signals according to the magnitude of amplitude, and a computer-readable recording medium on which software for realizing the converter is recorded.

[0002]

2. Description of the Related Art Conventionally, a plurality of analog signals are simultaneously AD-converted.
As a device for conversion, for example, Japanese Patent Application Laid-Open No.
There is one described in Japanese Patent No. 52762. This AD converter is a successive approximation AD converter having a plurality of analog input channels (four channels in FIG. 7). The configuration of the AD converter includes a DA converter 230 (a conversion bit number N, N is a natural number) for providing a reference value, an analog signal provided for each input channel, and an analog signal input to its own input channel and the DA signal. Comparators 201 to 204 which compare the output of converter 230 and output the comparison result as 1,0 signals
And the output of the corresponding comparator is set at any time.
Bit data registers 211 to 214, N-ary counters 221 to 224 counting by one each time a bit of a digital output is determined based on the comparison result, data registers 211 to 214 and counters 221 to 2 corresponding to respective inputs
The control circuit 240 changes the digital signal for giving the reference value according to the value of 24 as needed.

The operation of this AD converter is as follows. It is assumed that the counter has been reset before the start of conversion (the inside of the counter is 0). First, the DA converter 230 outputs an analog signal having a half amplitude of the full scale of the input. The output signals and the analog signals A1 to A4 of the respective input channels are compared with the respective comparators 201 to 204.
By comparing the analog input signals, the analog input signals are classified into which of the ranges obtained by dividing the input full scale into two. As a result, the value (0 or 1) of the MSB (most significant bit) of each digital output signal is determined, and the determined value is stored in the MSB inside the data registers 211 to 214. Each of the counters 221 to 224 is also counted from 0 to 1. The value inside the counter indicates the number of determined bits in the data register. Next, for example, a channel (for example, AC
In the case of 2), the D / A converter converts the range to which the input channel AC1 belongs (for example, the range equal to or less than 1/2 of the input full scale) into two to further divide the range.
An analog signal having four amplitudes is output. Then, by proceeding in the same manner as described above, the next bit of the MSB of the digital output signal corresponding to the input channels AC1 and AC2 is determined, and the values of the counters 221 and 222 are also incremented by one.
Thereafter, when the same successive approximation AD conversion process is performed and all the bits of the digital output signal of the input channel AC1 are determined, the value of the counter 221 becomes 0. Next, the successive approximation A / D conversion is performed based on the input channel AC2 having the largest counter value (that is, the number of determined bits of the digital output signal is the second largest after the input channel AC1). In this way, when the digital output signals of all the input channels are determined, the AD conversion is completed. In other words, since the bit state of another analog input is determined in the process of determining the bit state of the converted signal of a certain analog input, the number of successive approximations is reduced, so that the entire conversion time can be reduced.

[0004]

However, the AD converter shown in FIG. 7 uses a counter for each input channel number in order to grasp the conversion status of each input channel (how many bits of the digital output signal are determined). And the successive approximation AD corresponding to the conversion status of each input channel
Since the conversion process must be performed, there is a problem that the control circuit is complicated. Accordingly, a first object of the present invention is to realize a multiple-input A / D converter having a smaller circuit scale by not using a counter for each channel and simplifying the control circuit. In addition, when a sort process is performed by comparing the magnitudes of a plurality of analog signals and the like, it is generally difficult to process the analog signals as they are, so that it is common to sort them after converting them into digital values. For this reason, it is useful to use the AD converter shown in FIG. 7, but in this case, a circuit for performing a sort process after converting to a digital value is required. Moreover, even when the number of data required after sorting is smaller than the number of input channels, there is a problem that the sorting process cannot be performed unless all channels are AD-converted. Accordingly, a second object of the present invention is to provide a multi-input A / D converter capable of performing a sort process simultaneously with an A / D conversion without a circuit dedicated to the sort process and performing a sort process with a minimum necessary amount of A / D converted data. It is to realize.

[0005]

According to the first aspect of the present invention, there is provided an AD converter having a plurality of analog input channels.
One DA converter for converting a digital signal of N bits (N is a natural number) into an analog signal, one counter for counting up or down to generate a digital signal for inputting the DA converter, and each analog input channel A comparator that compares the output of the D / A converter with the analog input signal and outputs the comparison result as a 1,0 signal, and a comparator that is provided for each analog input channel and the output of the comparator changes. The content of the data storage device of each channel is an AD converter which is a digital signal obtained by converting an input analog signal. By employing this AD converter, digital values corresponding to analog signals of all channels can be stored in the storage device.

According to a second aspect of the present invention, in an AD converter having a plurality of analog input channels, one DA converter for converting a digital signal of N bits (N is a natural number) into an analog signal is sorted in ascending order. Count up if you want, count down if you want to sort in descending order,
One counter for generating a digital signal for inputting the DA converter and a counter provided for each analog input channel. The output of the DA converter is compared with the analog input signal. A comparator to output,
A data storage device that stores the same number of digital signals as the number of analog input channels, and detects that any one of the comparator outputs of each analog input channel has changed. A control circuit for performing an operation of storing data in a storage device,
The data storage device is an AD converter having a sorting function of sorting and storing digital signals corresponding to analog signals of each input channel. Since the AD converter is configured as described above, in addition to storing digital values corresponding to analog signals of all input channels in a data storage device provided for each input channel, one of the comparator outputs of each input channel is used. The change can be detected by the control circuit, and the count value can be stored in the data storage device in the order of detection. That is, since the count value simply increases or decreases, the digital signal is stored in the data storage device in ascending order (descending order).

According to a third aspect of the present invention, in the AD converter according to the second aspect, the digital signal stored in the data storage device is transmitted to the data storage device of the analog signal so that it can be determined which analog input channel the digital signal belongs to. And an AD converter having a storage device for storing information indicating the analog input channel at the same time. With this configuration, when the digital signal is stored in the data storage device, the AD converter can simultaneously store information indicating the input channel.

According to a fourth aspect of the present invention, in the A / D converter according to the second or third aspect, when the number of data stored in the data storage device after the A / D conversion and sorting is smaller than the number of analog input channels, An A / D converter using the control device having the number of internal circuits corresponding to the number. As a result, only the sorted data can be A / D converted.

According to a fifth aspect of the present invention, in the AD converter according to any one of the second to fourth aspects, the upper and lower limits of the sorting range are set as an initial value and an end value of a counter, This is an AD converter that performs A / D conversion by sequentially counting up or down, and ends the A / D conversion when the count value of the counter becomes equal to the end value. The value of the counter, that is, the output of the DA converter can be limited by the AD converter.
No D conversion is performed, so that the sort range can be limited.

According to a sixth aspect of the present invention, in the AD converter according to any one of the first to fifth aspects, during the AD conversion,
An AD converter that terminates AD conversion when the number of data stored in the data storage device reaches a desired value. With this configuration, the AD conversion can be automatically terminated.

According to a seventh aspect of the present invention, in the AD converter according to any one of the first to sixth aspects, the operation of the control circuit and the counter and the gate operation of the data latch are realized by software. It is.
With this configuration, the configuration of the AD circuit can be made smaller and simpler, and a multiple-input AD converter can be easily realized.

According to an eighth aspect of the present invention, there is provided a computer-readable recording medium storing the software according to the seventh aspect.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a first embodiment of an AD converter according to the present invention.
The following shows an example. In this embodiment, the number of input channels is 4, and the number of conversion bits is 4. However, the number of input channels and the number of conversion bits of the AD converter of the present invention are not limited to these. Hereinafter, the configuration of the present invention will be described with reference to FIG. Analog signals A1 to A4 are input to the input channels. The analog signal A1 input to this input channel
A4 are connected to the positive inputs of the comparators 11 to 14, respectively. The negative input of the comparators 11 to 14 is D
The output of the A converter 3 (conversion bit number 4) is connected. The output of the comparators 11 to 14 is the data latch 2
1 to 24 strobe signals are respectively connected to the gate terminals. Each of the data latches 21 to 24 can store 4-bit data. All inputs of the data latches 21 to 24 are connected to the output of the counter 4. The data latches 21 to 24 have a gate terminal of 1
, The input data is output as is, and the gate terminal
From 0 to 0, the input data at that time is stored and output. The outputs of the data latches 21 to 24 are digital signals O1 to O4 obtained by AD-converting the analog signals A1 to A4, respectively. The counter 4 is a 16 (= 2 ⁴ ) decimal up counter, and the counter outputs are data latches 21 to 21.
24 as well as the input of the DA converter 3.

Next, the operation of the embodiment of FIG. 1 will be described with reference to FIG. Here, during the AD conversion, the analog signals A1 to A4 of the input channel are constant. When the conversion start signal TS is input to the counter 4 at time t1, the counter 4 counts up from 0 in order. The DA converter 3 converts the count value into an analog value. At that time, DA
The converter 3 outputs an analog signal proportional to the magnitude of the input digital signal value. That is, as the counter 4 counts up, the amplitude of the analog output signal of the DA converter 3 increases. Comparator 1
In 1 to 14, analog signals A1 to A4 of the input channel
And the analog signals output from the DA converter 3 are compared, and the analog signals A1 to A4 of the input channels are
When the output is larger than the output of the A converter 3, the comparators 11 to
The output of 14 is 1. Therefore, the data latches 21 to 2
4 receives the output value of the counter 4 as it is. Then, at time t2, when the output of the DA converter 3 becomes larger than the analog signal A1 of the input channel (in FIG.
It takes some time until the output of the DA converter 3 changes after the output of the comparator 1 changes).
The output of 1 becomes 0, at which point the output of the data latch 21 (having a value of 3) is fixed. At this time, the output of the data latch 21 becomes the value of the digital signal O1 obtained by AD-converting the analog signal A1. Hereinafter, the output of the DA converter 3 becomes larger than the analog signal A3 at the time t3, larger than the analog signal A2 at the time t4, and larger than the analog signal A4 at the time t5, and the corresponding digital signals are O3, O2 and O4, respectively. Confirm the value. The method of terminating the conversion depends on a method of detecting that all the analog signals have been converted. The simplest method is that the conversion time is always long, but when the counter 4 counts the maximum value (here, 15). The end of the count. In this embodiment, the counter 4 is an up counter, but a down counter can also be used. However, in this case, the gate terminals of the data latches 21 to 24 are set to 0.
It is necessary to make the latch when it becomes 1 or to exchange the positive and negative terminals of the inputs of the comparators 11 to 14. The initial value of the counter 4 (the value at the time when the conversion start signal is input) is set to 15 (2 ⁴ -1). As described above, in this embodiment, since a control circuit and a counter for each channel are not required, the circuit scale can be reduced.

Next, as a second embodiment of the present invention, the A of the present invention having a function of performing the sorting process simultaneously with the AD conversion is described.
FIG. 3 shows one embodiment of the D converter. Here, the number of input channels is four, but the number of input channels of the AD converter of the present invention is not limited to this number. Hereinafter, the configuration of the present invention will be described with reference to the embodiment shown in FIG. The comparators 51 to 54, the DA converter 8, and the counter 9 have the same functions as the comparators 11 to 14, the DA converter 3, and the counter 4 in FIG. Each of the data latches 71 to 74 is capable of storing N-bit data, where the number of conversion bits is N (natural number). The inputs of the data latches 71 to 74 are all connected to the output of the counter 9. The gate terminals of the data latches 71 to 74 are connected to the output of the control circuit 6. It is assumed that data is latched when the gate terminals of the data latches 71 to 74 change from 1 to 0. The control circuit 6 detects that any of the outputs of the comparators 51 to 54 has changed, and the data latches 71 to 74 latch the output of the counter 9 at that time one by one in each time. The gate terminals 71 to 74 are controlled.
FIG. 4 shows an example of the simplest configuration of the control circuit 6. When an A / D conversion start signal (not shown) is input, the 4-bit shift register 66 is reset. The output is set to 1 by the inverters 67 to 70, the signal is connected to the gate terminals of the data latches 71 to 74, and the data latches 71 to 74 take in the output of the counter 9. XOR circuits 61 to 64 are comparators 51 to 54
Of each output is detected. The output of the XOR circuit becomes 0 if the change is not detected, and becomes 1 for a moment when the change is detected, and returns to 0. The OR circuit 65 combines the outputs of the XOR circuits 61 to 64 and serves as a clock for the shift register 66. The input of the shift register 66 is always 1. As a result, each output of the comparators 11 to 14 changes, and each time the clock of the shift register 66 is input, the internal register on the left side becomes 1 sequentially, and the gate terminals of the data latches 71 to 74 sequentially become 0. Go. That is, data is sequentially latched.

Next, the operation of the second embodiment will be described. The basic operation is almost the same as that of the first embodiment. However, if the sort is performed in ascending order, the counter 9 must be an up counter, and if the sort is performed in descending order, the counter 9 must be a down counter. Here, the case of ascending sort will be described as an example. When the conversion start signal is input, the control circuit 6 and the counter 9 are initialized, and the counter 9 starts counting up from 0. When the output of the DA converter 8 becomes larger than one of the analog signals A1 to A4 of the input channel, the corresponding comparator output of the comparators 51 to 54 becomes 1 to 0.
The control circuit 6 detects this, and latches the output value of the counter 9 input to the data latch 71. This is an AD converted digital value of the analog signal having the smallest amplitude among the analog signals A1 to A4. Subsequently, the counter 9 continues to count up, and stores the digital value obtained by AD conversion of the analog signal having a small amplitude in the data latches 72 to 74 in order. That is, the digital signals sorted in ascending order are the data latches 71-74.
Will be stored. The descending sort can be realized by making the counter 9 a down counter. Note that if the control circuit shown in FIG. 4 is used, only the changes in the outputs of the comparators 51 to 54 are observed, so that it is not necessary to exchange the logic of the gate terminals of the data latches 71 to 74 and the inputs of the comparators 51 to 54. The counter 9 counts down from 2 ^N -1.

The simplest way to end the conversion is to end counting when the counter 4 has counted the maximum value (here, 15 in ascending order and 0 in descending order).
As a method corresponding to the method of detecting that all analog signals have been converted as described in the first embodiment, only the gate signal of the data latch 74 in which data is finally stored is monitored, and this gate signal is set to 0. The count of the counter may be terminated when the following condition is satisfied. As apparent from the above description, according to the present invention, AD conversion and sorting can be performed simultaneously only by using a simple control circuit. In the normal sort, the processing time explosively increases as the number of inputs increases, but in the present invention, the sorting can be performed simultaneously with the AD conversion regardless of the number of inputs, so that the processing time for sorting can be saved. .

As a third embodiment of the present invention, an embodiment in which input channels for sorted digital signals and analog signals corresponding thereto are specified will be described. In this case, since the sort order of the input channel numbers must be preserved, the control circuit 6 having the configuration shown in FIG. 5 is used.
The control circuit 6 of FIG. 5 is obtained by adding a dashed line to the control circuit 6 of FIG. The encoder 75 outputs, as 2-bit data, the position of only one of the four input data, which is 1; in this case, the 2-bit data is 1 of the outputs of the XOR circuits 61 to 64. Indicate the input channel number. For example, the numbers of the input channels AC1 to AC4 in FIG. 3 are set to 0 to 3 in order from the top, and the binary numbers 00 to 11 are used as encoder outputs. The encoder outputs are sequentially sent to 2-bit data latches 76 to 7
9 is stored. Here, the same strobe (gate) signal as that of the data latches 71 to 74 storing the AD conversion values is used. As a result, the input channel number corresponding to the AD conversion value stored in the data latch 71 is stored in the data latch 76.
The input channel number corresponding to the AD conversion value stored in the data latch 72 is stored in the data latch 77.
9 can be stored. When only the sort order information is necessary and the AD conversion value is not necessary, the data latches 71 to 7 storing the AD conversion values in FIG.
4 may be omitted.

In the second and third embodiments, the number of necessary data after sorting may be smaller than the number of input channels. In this case, the data latch for storing the AD conversion value and the internal circuit of the control circuit 6 for generating the gate signal thereof need only have the required number of data. At this time, if the A / D conversion is terminated when the gate signal of the data latch in which data is stored finally becomes 0, unnecessary A / D conversion of input channel data can be avoided. Second,
In the third embodiment, when it is desired to set a threshold value for sorting or to limit the range of sorting in amplitude,
If the AD conversion value is not equal to or more than a certain value or less than a certain value, it can be easily excluded from sorting by setting the threshold value and the upper and lower limit values in the initial value and the end value of the counter. Specifically, for example, the DA of FIG.
In the converter 8, the lower limit is set to the initial value of the counter in the case of ascending sort, and the upper limit of the sort range is set to the same initial value in the case of descending sort, and the counter is operated. Then, when the counter value is equal to the upper limit value of the sort range in the case of the ascending sort, and in the case of the descending sort, the count ends when the counter value becomes equal to the lower limit value. As a result, when the AD conversion value falls within the sort range, the data is stored in the data latches 71 to 74.
The count end value (upper limit value / lower limit value) of the counter is stored in the remaining data latches in which the sort range data is not stored.

In each of the embodiments described above, the control circuit 6, the counters 4, 9 and the data latches 21 to 24, 7
The gate operations of 1 to 74 can be realized as software, and the data latches 21 to 24 and 71 to 74 can be stored as memories. That is, a D / A converter and a comparator are connected to a microprocessor such as a DSP or a CPU, and the software for implementing the present invention is installed, so that a multiple-input A / D converter can be easily realized. This is shown in FIG. 6 as a fourth embodiment. The microprocessor 120 includes the control circuit 6, the counter 4,
9 and the gates of the data latches 21 to 24 and 71 to 74, and the registers in the memory 130 or the microprocessor 120 store the data latches 21 to 24, 7
1 to 74 are stored. The DA converter 110 and the comparators 101 to 104 operate in the same manner as the DA converter and the comparator of the other embodiments.

[0021]

According to the present invention, there is no need to provide a counter for each channel, and there is no need to use a control circuit for controlling a DA conversion circuit as in the prior art. AD with analog input channel
The converter can be realized by a simple circuit, and the circuit can be downsized.

According to the second aspect of the present invention, the processing time of the normal sorting explosively increases as the number of inputs increases. However, according to the present invention, AD processing can be performed only by using a simple control circuit.
Conversion and sorting can be performed at the same time, and sorting can be performed simultaneously with AD conversion regardless of the number of inputs, so that processing time for sorting can be saved.

According to the third aspect, it is possible to easily determine which analog input channel the converted digital signal belongs to.

According to the fourth aspect of the present invention, since the internal circuits of the control circuit correspond to the required number of data, unnecessary conversion and sorting are not performed.

Advantages corresponding to claim 5: the value of the counter,
That is, by limiting the output of the DA converter, the conversion and sorting range can be limited.

According to the sixth aspect of the present invention, when the number of data stored in the data storage device reaches a predetermined number, the A / D conversion can be automatically terminated, so that unnecessary conversion is not performed.

Effects corresponding to claim 7: claims 1 to 6
In the A / D converter described in the above, the components other than the comparator, the D / A converter and the storage device are realized by software, so that an A / D converter with a plurality of inputs can be easily obtained, and the circuit configuration is simplified and the size is further reduced. Can be

Effect corresponding to claim 8: AD of plural inputs
Convert the converter to a microprocessor such as a DSP or CPU.
It can be easily realized by connecting an A converter, a comparator and the like.

[Brief description of the drawings]

FIG. 1 is a diagram schematically showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a diagram showing a timing chart of each part of the first embodiment.

FIG. 3 is a diagram schematically showing a configuration of a second exemplary embodiment of the present invention.

FIG. 4 is a configuration diagram of a control circuit according to a second embodiment.

FIG. 5 is a diagram schematically showing a configuration of a third exemplary embodiment of the present invention.

FIG. 6 is a diagram schematically showing a configuration of a fourth embodiment of the present invention.

FIG. 7 is a diagram schematically showing a configuration of a conventional multi-input AD converter.

[Explanation of symbols]

3, 8, 110 ... DA converter, 4, 9 ... counter, 6 ...
Control circuits, 11 to 14, 51 to 54, 101 to 104 ...
Comparators, 21 to 24, 71 to 74, 76 to 79 ...
Data latches, 61 to 64: XOR circuit, 65: OR circuit, 66: shift register, 67 to 70: inverter,
75 encoder, 120 microprocessor, 13
0 ... Memory.

Claims (8)

[Claims] 1. An A having a plurality of analog input channels
A D converter for converting a digital signal of N bits (N is a natural number) into an analog signal;
One counter for counting up or down to generate a digital signal for inputting the D / A converter, and a counter provided for each analog input channel.
A comparator that compares the output of the converter with the analog input signal and outputs the comparison result as a 1,0 signal, and a counter provided for each analog input channel and stores the count value of the counter when the comparator output changes. An A / D converter comprising a data storage device for storing data for each channel, wherein the content of the data storage device for each channel is a digital signal obtained by converting an input analog signal. 2. An A having a plurality of analog input channels.
A D converter for converting a digital signal of N bits (N is a natural number) into an analog signal;
One counter for generating a digital signal for inputting the D / A converter is provided for each analog input channel, and a counter is provided for each analog input channel. The output of the converter is compared with the analog input signal.
A comparator that outputs a 0 signal, a data storage device that stores the same number of digital signals as the number of analog input channels, and a change in one of the comparator outputs of each analog input channel. A control circuit for sequentially storing the count values of the counters in a data storage device, wherein the data storage device has a sorting function of sorting and storing digital signals corresponding to analog signals of respective input channels; An AD converter characterized by the above-mentioned. 3. The A / D converter according to claim 2, wherein the digital signal stored in the data storage device is stored in the data storage device at the same time as storing the digital signal in the data storage device so as to know which analog input channel the digital signal belongs to. An AD converter having a storage device for storing information indicating the analog input channel. 4. The AD converter according to claim 2, wherein when the number of data stored in the data storage device after AD conversion and sorting is smaller than the number of analog input channels, the number corresponding to the number of data. An AD converter using the control device having the internal circuit of (1). 5. The A / D converter according to claim 2, wherein upper and lower limit values of a sorting range are set as an initial value and an end value of the counter, and the count is incremented or decremented in order from the initial value. An AD converter that performs AD conversion and terminates the AD conversion when the count value of the counter becomes equal to the end value. 6. The AD converter according to claim 1, wherein the AD conversion is terminated when the number of data stored in the data storage device reaches a desired value during the AD conversion. AD converter. 7. The AD converter according to claim 1, wherein the operation of the control circuit and the counter and the gate operation of the data latch are realized by software. . 8. A computer-readable recording medium on which the software according to claim 7 is recorded.