JPH0389552A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To improve a writing efficiency and to provide an EPROM memory cell array having improved program characteristic by wiring a plurality of source diffused regions by metal interconnections, commonly using the diffused region only between a pair of adjacent memory cells, and forming the common region in a rectangular pattern. CONSTITUTION:A source diffused region 8 and a drain diffused region 6 are formed on a silicon substrate 16, and a floating gate 2 is formed on a channel region through a floating gate 2. A control gate 4 is formed thereon through an interlayer insulating film 3. A contact 13 is provided on the region 8, common source diffused regions are wired therebetween by first layer metal interconnection 14 through the contact 13, and lad to a ground terminal. The regions 6 are wired therebetween by second layer metal interconnection 12 through a contact 10. Since the source diffused region is wired by the metal interconnection, a source resistance is so reduced in the degree as to be ignored, rise of a source potential is prevented, and an EPROM having satisfactory program characteristic can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an EFROM which is a semiconductor memory device.

(Conventional technology) An example of a FAMO8 type EPROM is shown in FIG.

Regarding the FAMO5 type memory cell, a floating gate 2 is provided on the channel region with a gate oxide film interposed therebetween, and a control gate 4 is provided thereon with an interlayer insulating film interposed therebetween. 6 is a drain region, and 8 is a source region, which are usually formed by N-type impurity diffusion regions.

To increase the degree of integration in memory cell arrays.

Between adjacent memory cells, for example, in the case of the figure, Tri and Tr2
, Tr3 and Tr4 have a common source region 8, and the common source regions are connected by a diffusion region and connected to ground. A contact 10 is provided in the drain region 6, and each drain region 6 is connected by an aluminum wiring 12.

(Problems to be Solved by the Invention) The following problem arises because the common source regions between adjacent memory cells are connected by diffusion regions and guided to the ground.

(1) When programming a memory cell, a large current flows from the drain region 6 to the source region 8.

The source regions are connected by a diffusion region.

The resistance of the diffusion region is high (approximately 30Ω/hole), and the source voltage increases due to the large current during programming.

As the source voltage increases, the potential difference Vgs between the control gate 4 and the source region 8 decreases, and the writing efficiency decreases. Therefore, it is not possible to obtain a sufficient shift amount of the threshold voltage vth by programming, and
Since the program speed becomes slow, program characteristics deteriorate.

(2) Since the source region 8 is common between adjacent memory cells and multiple source regions are connected by a diffusion region, a part of the corner of the diffusion region is exist. Since the layout pattern of the source region 8 is formed by photolithography, some corners are rounded. A floating gate 2 is formed on the substrate, and since the pattern of the floating gate 2 is also formed by photolithography, the source region 8 and the floating gate 2 are
The distance from the memory cell varies depending on the memory cell. In other words, the overlap between the source region 8 and the floating gate 2 at a part of the corner of the memory cells Tri and T r 2 differs, and the programming characteristics differ depending on the memory cell.

Furthermore, when programming the memory cell Tri,
The leakage current of Tr2, which is a non-selected transistor, increases, and the leakage current of a large number of memory cell transistors that have the same layout as Tr2 reduces the drain voltage for writing to the memory cell Tri, and the programming characteristics of Tri deteriorates. do.

Therefore, the present invention improves writing efficiency by lowering the resistance value of the source region and improves program characteristics.
The object is to provide a PROM memory cell array.

The present invention also includes: The purpose of this invention is to eliminate unevenness in leakage characteristics between memory cell transistors by eliminating a corner portion C of the source region 8 as shown in FIG. 4, thereby providing a memory cell array with uniform programming characteristics. be.

(Means for solving problems).

In order to reduce the resistance value from the source diffusion region of the memory cell transistor to the ground terminal, a plurality of source diffusion regions are connected by metal wiring.

In a preferred embodiment, the source diffusion region is made common only between a pair of adjacent memory cells, and the common diffusion region is formed into a rectangular pattern in order to eliminate corner portions of the source diffusion region and obtain a memory cell array with uniform programming characteristics. do.

(Function) Since the source diffusion region is connected by metal wiring, the resistance value is lower than when the source diffusion region is connected by the diffusion region and led to the ground terminal, and the source voltage increases due to the large current during writing. can be prevented from rising.

If the source diffusion regions are connected with metal wiring, the common source diffusion region is arranged only between a pair of adjacent memory cells, and the source diffusion region is formed into a rectangular pattern, the source diffusion region has a corner part. Therefore, even if the position of the floating gate is shifted, the overlap between the floating gate and the source region is uniform for all memory cell transistors.
Program characteristics also become uniform.

(Example) FIG. 1 shows one embodiment, and (A) is a plan view.

(B) is a sectional view taken along line A-A' in (A).

The same symbols are used for the same parts as in Figure 4.

A source diffusion region 8 and a drain diffusion region 6 are formed in a silicon substrate 16, a floating gate 2 is formed on the channel region with a gate oxide film 1 interposed therebetween, and a control gate 4 is formed on the floating gate 2 with an interlayer insulating film 3 interposed therebetween. It is formed. 5 and 7 are glabellar insulating films.

As in the case of FIG. 4, the source diffusion region 8 is formed commonly between adjacent memory cell transistors, and a plurality of common source diffusion regions are connected by the diffusion region. Contacts 13 are provided in the source diffusion region 8, and the plurality of common source diffusion regions are connected through the contacts 13 by a first layer metal wiring 14.

It is led to the ground terminal.

The drain diffusion regions 6 are interconnected by a second layer metal wiring 12 via a contact 10.

First layer metal wiring 14 and second layer metal wiring 1
Examples of 2 include AQ, which has traditionally been used as a wiring material for semiconductor integrated circuit devices, and AQ containing a small amount of silicon.
-8i, AQ-Cu-8i containing a small amount of Cu and Si
etc.

FIG. 2 represents another embodiment. BB' in Figure 2
The cross-sectional view taken along the line is the same as that shown in FIG. 1(B).

Compared to the embodiment shown in FIG. 1, the source diffusion region 8a is formed in common only between a pair of adjacent memory cell transistors. The common source diffusion region 8a is formed in a rectangular pattern. Each common source diffusion region 8
A is provided with a contact 13, and through each contact 13, a plurality of source diffusion regions 8a are connected by a first layer metal wiring 14 and led to a ground terminal. The other configurations are the same as the memory cell shown in FIG. 1 except for the difference in the shape of source diffusion region 8a.

FIG. 3 shows the equivalent circuits of the present invention and the conventional case. In the case of the present invention (A), the source is led to the ground terminal by the metal wiring 14, so its resistance can be ignored. In the conventional case (B), the diffusion region 8
The source resistance increases because it is guided to the ground terminal.

(Effects of the Invention) In the present invention, since the source diffusion region is connected with metal wiring, the source resistance is reduced to a negligible level, an increase in the source potential can be prevented, and the EFR has good programming characteristics.
OM can be realized.

If the source diffusion region is made common only between a pair of adjacent memory cell transistors and has a rectangular pattern,
The phenomenon of partially rounded corners during photolithography no longer occurs, non-uniformity of memory characteristics is eliminated, and programming characteristics of memory cells are made uniform. It also prevents the leakage current of unselected transistors from increasing due to the pattern of the source diffusion region, and provides good program characteristics.
PROM memory cell arrays can now be produced stably.

[Brief Description of the Drawings] The first construction drawing represents one embodiment, and (A) is a plan view. (B) is a sectional view taken along line AA' in (A). FIG. 2 is a plan view showing another embodiment, and FIG. 3 is an equivalent circuit diagram comparing the present invention and a conventional memory cell array. FIG. 4 is a plan view showing a conventional memory cell array. 2...Floating gate, 4...
Control gate, 6...Drain diffusion region, 8, 8a...Source diffusion region, 14...
...Metal wiring for source connection.

Claims (2)

[Claims] (1) A semiconductor memory device in which the source diffusion regions of a plurality of EPROM memory cells are connected by a metal wiring, and the drain diffusion regions of a plurality of EPROM memory cells are connected by another metal wiring. (2) The semiconductor memory device according to claim 1, wherein the EPROM memory cells are arranged so that each pair of adjacent EPROM memory cells share a common source diffusion region, and the common source diffusion region is formed in a rectangular pattern.