KR19980014258A - The memory cell array - Google Patents

Abstract

The present invention relates to a memory cell array, and more particularly, to a memory cell array in which the degree of integration can be improved by allowing four memory cells to share one source region or a drain region in order to reduce the area occupied by the contact holes.

Description

The memory cell array

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a memory cell array, and more particularly to a memory cell array capable of improving the degree of integration of elements.

In general, a flash memory device having an electric program and an erasure function is composed of a peripheral circuit and a memory cell array. The memory cell array is composed of a plurality of memory cells each selected by a word line (Word Line) and a bit line (Bit Line) signal. The programming operation for storing information in the memory cell is performed by a floating Gate, and hot electrons are injected. An erase operation for erasing the stored information is performed by causing electrons injected into the floating gate to be discharged. Such a memory cell is divided into a stacked gate type and a split gate type according to the shape of the gate electrode. A conventional memory cell array including a stacked gate type memory cell will be described with reference to FIG. Then,

FIG. 1 is a layout diagram for explaining a conventional memory cell array, which will be described with reference to FIG. 2. FIG.

A field oxide film (1) is formed on a device isolation region of a silicon substrate, and a floating gate (1) is formed on the channel region of the silicon substrate and electrically isolated from each other by the silicon substrate and the tunnel oxide film, (2) are formed. A control gate 3 electrically separated from the floating gate 2 by a dielectric film is formed on an upper portion including the floating gate 2 formed in a direction crossing the field oxide film 1. A drain region 5 is formed on the silicon substrate on the inner side of the control gate 3 which intersects both sides of the field oxide film 1, (3) A source region (6) is formed on the silicon substrate on the outer side. A contact portion 4 is formed in the drain region 5 for connection with a bit line (not shown) formed to cross the control gate 3. 2, the tunnel oxide film 8, the floating gate 2, the dielectric film 9 and the control gate 3 are formed on the channel region of the silicon substrate 7 A stacked gate electrode is formed and a source region 6 and a drain region 5 are formed on the silicon substrate 7 on both sides of the gate electrode.

In the memory cell array constructed as described above, two bits are formed in the contact portion 4 of the drain region 5 connected in common and the drain regions 5 of the two memory cells are connected in common And the drain region 5 is connected to the bit line through a contact hole. However, since the size of the device is determined by the size of the contact hole and the area occupied by the contact hole, it is difficult to improve the degree of integration of the device when the layout is used, 4) and the distance Y1 between the contact portion 4 and the field oxide film 1 are appropriately maintained.

Accordingly, it is an object of the present invention to provide a memory cell array capable of solving the above-mentioned disadvantages by allowing four memory cells to share one source region or a drain region.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a field oxide film formed in a device isolation region of a silicon substrate; a field oxide film formed on the silicon substrate between adjacent field oxide films; A floating gate which is electrically separated from the silicon substrate by an oxide film, and a floating gate formed adjacent to the floating gate in one direction, the field oxide film being formed to have the same width as the floating gate and electrically connected to the floating gate by a dielectric film A source region formed in the source region and a source region formed in the source region, the source region being formed in the source region, the source region being formed in the drain region, Drain contact And the like.

1 is a layout view of a conventional memory cell array;

Fig. 2 is a sectional view taken along line A1-A2 in Fig. 1; Fig.

3 is a layout diagram of a memory cell array according to a first embodiment of the present invention;

FIG. 4A is a cross-sectional view taken along line B1-B2 shown in FIG. 3; FIG.

FIG. 4B is a sectional view taken along the line C1-C2 shown in FIG. 3; FIG.

FIG. 4C is a sectional view taken along the line D1-D2 shown in FIG. 3; FIG.

5 is a layout diagram of a memory cell array according to a second embodiment of the present invention;

6 is a circuit diagram of a memory cell array according to the present invention.

Description of the Related Art [0002]

1 and 11: field oxide films 2 and 12; floating gate

3 and 13: control gate 4:

5 and 15: drain region 6 and 16: source region

7 and 17: silicon substrates 8 and 18: tunnel oxide film

9 and 19: Dielectric film 14A: drain contact part

14B: source contact portion

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a layout view of a memory cell array according to a first embodiment of the present invention, and will be described with reference to FIGS. 4A to 4C. FIG.

A field oxide film 11 is formed on a device isolation region of a silicon substrate and each of the field oxide films 11 is arranged to be staggered with another adjacent field oxide film 11 and both end portions of the field oxide films 11 are adjacent to each other Are formed so as to overlap with a part of the other field oxide film (11). Both ends of the field oxide film 11 are partially overlapped with the field oxide film 11 between the field oxide film 11 and the other field oxide film 11 adjacent to the field oxide film 11, A control gate 13 is formed on the field oxide film 11 including the floating gate 12 formed in one direction adjacent to the floating gate 12 to be electrically isolated from the floating gate 12 The floating gate 12 and the control gate 13 are electrically separated by a dielectric film. The source region 13 or the drain contact portion 14A having the source contact portion 14B is formed in the silicon substrate surrounded by the adjacent four field oxide films 11 and the floating gate 12 Drain regions 15 are formed. Hereinafter, to facilitate understanding of the present invention, each part of the memory cell array will be described with reference to 4A to 4C.

4A is a cross-sectional view taken along the line B1-B2 shown in FIG. 3, showing a state in which the control gate 13 passes over the field oxide film 11. In the lower portion of the control gate 13, And a drain region 15 is formed in the silicon substrate 17 on one side of the field oxide film 11. [

FIG. 4B is a cross-sectional view taken along the line C1-C2 shown in FIG. 3, in which the control gate 13 is formed on the other field oxide film 11 formed adjacent to the field oxide film 11 shown in FIG. The dielectric film 19 is formed under the control gate 13 and a source region 16 is formed in the silicon substrate 17 on one side of the field oxide film 11 . 4A and 4B, the control gate 13 is formed so as to intersect with one side end of each field oxide film 11, and the control gate 13 is formed on the silicon substrate 17 on both sides of the control gate 13 A source region 16 and a drain region 15 are formed respectively.

FIG. 4C is a cross-sectional view taken along the line D 1 -D 2 shown in FIG. 3, in which a tunnel oxide film 18, a floating gate 16, and a drain region 15 are formed on the silicon substrate 17 between the source region 16 and the drain region 15. The gate electrode 12, the dielectric film 19, and the control gate 13 are stacked.

5, the control gate 13 formed on the field oxide film 11 may be formed at a predetermined distance inward of the field oxide film 11 as a second embodiment of the present invention The distance X3 between the drain contact portion 14A or the source contact portion 14B and the control gate 13 is increased so that the manufacturing margin can be increased and the manufacturing process can be facilitated .

The memory cell array as described above is configured so that four bits or four memory cells share one source region 16 or the drain region 15 and the drain contact portion 14A and the source contact portion 14B Respectively. Therefore, the area occupied by the contact holes as a whole is reduced as compared with the prior art. The distance X2 between the drain contact portion 14A or the source contact portion 14B and the control gate 13 can be reduced by the field oxide film 11 and the field oxide film 11, The distance Y2 between the drain contact portion 14A or the source contact portion 14B and the field oxide film 11 can be sufficiently maintained. Therefore, the size of the device is effectively reduced, the electrical insulation between the devices and the operating characteristics are improved.

6, the operation of programming, erasing, and reading predetermined data in the memory cell of the portion K shown in FIG. 6 will be described as follows .

First, the program operation of the memory cell is performed by a channel hot electron injection method. For this purpose, the third word line WL3, the first bit line BL1, and the second source line S1, And the other source lines S0, S2, S3,... Sm are grounded or floated. In other words, the bias voltages are applied to the word lines and the bit lines.

Secondly, the erase operation of the memory cell is performed by the F-N tunneling method. For this purpose, an erase bias voltage is applied to all word lines and bit lines (or source lines).

Third, each read bias voltage is applied to the third word line WL3, the first bit line BL1, and the second source line S1 in order to read information stored in the selected memory cell K And ground lines are applied to the remaining word lines and bit lines, respectively, and the other source lines S0, 21, S3 ... Sm are grounded or floated.

If a decoder is connected to each of the source lines S0, S1, S2 ... Sm, or a decoder is connected to odd-numbered source lines and even-numbered source lines, a decoder circuit formed in the peripheral circuit area can be simplified And can improve the operation speed.

As described above, according to the present invention, since four memory cells share one source region or drain region, the area occupied by the contact holes as a whole is reduced, and the separation distance between the contact holes, the control gate, and the contact holes and the field oxide film is reduced . Therefore, there is an excellent effect that the integration and operation characteristics of the device can be effectively improved by using such a layout.

Claims (4)

In the memory cell array, A field oxide film each formed in an element isolation region of a silicon substrate, A floating gate formed on the silicon substrate between the field oxide films adjacent to each other and having opposite ends overlapping with a part of the field oxide film and being electrically separated from the silicon substrate by a tunnel oxide film; A control gate formed on the field oxide film including the floating gate adjacent to the floating gate and formed in the same width as the floating gate and electrically separated from the floating gate by a dielectric film; A source region and a drain region respectively formed on the silicon substrate surrounded by the four adjacent field oxide films and the floating gate, A source contact formed in the source region, And a drain contact portion formed in the drain region. The method according to claim 1, Wherein the field oxide film is arranged to be staggered from other adjacent field oxide films. The method according to claim 1 or 2, And both ends of each of the field oxide films are overlapped with a part of the adjacent other field oxide films. The method according to claim 1, Wherein the control gate formed on the field oxide film is formed at a predetermined distance inward of the field oxide film.