JPH0387052A - Pga type semiconductor device and manufacture thereof - Google Patents
Pga type semiconductor device and manufacture thereofInfo
- Publication number
- JPH0387052A JPH0387052A JP1226083A JP22608389A JPH0387052A JP H0387052 A JPH0387052 A JP H0387052A JP 1226083 A JP1226083 A JP 1226083A JP 22608389 A JP22608389 A JP 22608389A JP H0387052 A JPH0387052 A JP H0387052A
- Authority
- JP
- Japan
- Prior art keywords
- pin
- semiconductor device
- external
- ceramic package
- fixing plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000000919 ceramic Substances 0.000 claims abstract description 42
- 229920005989 resin Polymers 0.000 claims abstract description 16
- 239000011347 resin Substances 0.000 claims abstract description 16
- 241000587161 Gomphocarpus Species 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 10
- 239000000945 filler Substances 0.000 claims abstract description 4
- 238000007789 sealing Methods 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 abstract description 16
- 238000005219 brazing Methods 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000005476 soldering Methods 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 238000010304 firing Methods 0.000 description 3
- 239000002241 glass-ceramic Substances 0.000 description 3
- 229910017944 Ag—Cu Inorganic materials 0.000 description 2
- 238000005253 cladding Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、外部リードが底部に直立して設けられたＰＧ
Ａ （ピン・グリッド・アレイ）型半導体装置、特にセ
ラミックパッケージ型のＰＧＡ型半導体装置及びその製
造方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a PG in which external leads are provided upright on the bottom.
A (Pin Grid Array) type semiconductor device, particularly a ceramic package type PGA type semiconductor device, and a manufacturing method thereof.
従来のＰＧＡ型半導体装置の外部リードは、第３図に示
すように、セラミックシートを何層かに重ね合わされ焼
成されたセラミック基体底部のランド部にＡｇ−Ｃｕろ
う材を用いて７００〜８００℃の高温下でろう付けされ
ていた。このリードろう付けは、ＩＣを搭載する前のセ
ラミックパッケージ部材としての工程の一つであり、Ｉ
Ｃメーカーは外部リードが取り付けられているセラミッ
クパッケージを入手し、これを用いてＩＣチップを搭載
組立てることによりＩＣ製品を製造していた。As shown in Figure 3, the external leads of a conventional PGA type semiconductor device are made by stacking ceramic sheets in several layers and firing them at a temperature of 700 to 800°C using an Ag-Cu brazing material on the land at the bottom of the ceramic base. It was brazed at high temperatures. This lead brazing is one of the processes for ceramic package members before mounting an IC.
C manufacturers have been manufacturing IC products by obtaining ceramic packages with external leads attached and using them to mount and assemble IC chips.
ところが、上述した従来のＰＧＡ型半導体装置は、基体
となるラミネートセラミックパッケージが非常に高価な
上、ＩＣ組立て工程において、パッケージ基体底部に設
けられた外Ｒ＋Ｊ−ドか細く、長くかつ多数に及ぶ為、
ハンドリング及び設備の自動化に対して多大な障壁を与
えている。また、外部リードそのものも変形、損傷をこ
うむるという欠点がある。そこで、第４図及び第５図に
示すような半導体装置が近年開発されている。しかし、
これらは、共に大きな欠点を有し、先のラミネートセラ
ミックパッケージに置き替わることができない。両者は
共に、外部リードをＩＣ組立後に取り付けるタイプのも
のである。第４図の半導体装置はネイルヘッドタイプの
外部リードを高温半田（２００〜２５０℃）等で、ビン
立てを行った半田ピン立てタイプである。第５図の半導
体装置は、セラミックパッケージ基体に予め設けてあっ
たピン用スルーホールに外部リードを差し込みピン上部
を加圧してかしめた後、半田留めしたピンかしめタイプ
である。半田ピン立てタイプは、半田付けの強度そのも
のが弱いという欠点を有し、横からの曲げ強度に非常に
弱いばかりか、選別、実装用のソケットの抜き差しに対
しても半田の接着、強度が不十分である。また、装着を
直接半田実装する場合には、実装用の半田温度に対し、
ピン取り付は用の半田が再溶融して外部リードピンがと
れてしまうことも起こり得る。また、ピンかしめタイプ
の場合は、外部リードをセラミック基体のスルーホール
に差し込み、かしめる為、位置、精度及びかしめ時のセ
ラミックへの応力集中及び多ピン化不適合という、欠点
を有している。これは、まずセラミック基体に設けなく
てはならないスルーホールがセラミック焼成前に金型で
抜く為、焼成後のセラミックの収縮変形によりスルーホ
ールの位置精度が出ないためである。よってピン取り付
は後の精度も出ない。また、ピンかしめ時、ピン上部よ
り、荷重を衝撃力を伴って加える為、ピンをセラミック
のスルーホール部に大きな力が加わり、ピンはセラミッ
ク及びスルーホール内に埋設されたメタウィズにくい込
むことが出来る反面、それと同時にこの境界部のセラミ
ックに多大な応力集中が生じ、その後に加わる熱及び他
の自家荷重に耐えられず、クラックを生じることになる
。However, in the conventional PGA type semiconductor device described above, the laminated ceramic package that serves as the base is very expensive, and in the IC assembly process, the outer R+J-domains provided at the bottom of the package base are thin, long, and numerous.
This poses a significant barrier to handling and equipment automation. Another disadvantage is that the external leads themselves are subject to deformation and damage. Therefore, semiconductor devices as shown in FIGS. 4 and 5 have been developed in recent years. but,
Both of these have major drawbacks and cannot replace the previous laminated ceramic packages. Both are of the type in which external leads are attached after the IC is assembled. The semiconductor device shown in FIG. 4 is of a solder pin stand type in which nail head type external leads are held up with high temperature solder (200 to 250 DEG C.) or the like. The semiconductor device shown in FIG. 5 is a pin caulking type in which external leads are inserted into pin through holes previously provided in the ceramic package base, the upper portions of the pins are pressurized and caulked, and then soldered. The solder pin stand type has the disadvantage that the soldering strength itself is weak, and not only is it extremely weak in bending strength from the side, but also has insufficient solder adhesion and strength when inserting and removing sockets for sorting and mounting. It is enough. In addition, when mounting is directly soldered, the solder temperature for mounting should be
When attaching the pin, the solder used may remelt and the external lead pin may come off. In addition, in the case of the pin caulking type, since the external lead is inserted into a through hole in the ceramic base and caulked, it has disadvantages such as stress concentration on the ceramic during caulking due to positional accuracy, and incompatibility with a large number of pins. This is because the through-holes that must be formed in the ceramic base are first punched out using a mold before firing the ceramic, and the positioning accuracy of the through-holes cannot be achieved due to shrinkage and deformation of the ceramic after firing. Therefore, the accuracy after pin installation is not achieved. In addition, when the pin is caulked, the load is applied from the top of the pin with impact force, so a large force is applied to the ceramic through-hole part of the pin, allowing the pin to sink into the ceramic and the metawidth embedded in the through-hole. On the other hand, at the same time, a large stress concentration occurs in the ceramic at this boundary, which cannot withstand the heat and other self-loads that are subsequently applied, resulting in cracks.
さらには、ピンとピンの間にはＩＣからの情報を外部リ
ードへ導く内部配線が多数走査している為ピン間のピッ
チ寸法は、多ピン化する上で内部配線の本数に大きく左
右してしまう。ピン用のスルーホール径をビン径以上に
大きくとることは、配線数、幅の減少を呼び、配線の導
通抵抗増加に到る為、多ピン化対応のＰＧＡ型半導体装
置の目的から逸脱するものである。Furthermore, since there are many internal wirings that guide information from the IC to external leads between the pins, the pitch between the pins has a large effect on the number of internal wirings when increasing the number of pins. . Making the pin through-hole diameter larger than the bottle diameter will lead to a decrease in the number and width of wires, and will lead to an increase in the conduction resistance of the wires, which deviates from the purpose of a PGA type semiconductor device that supports a large number of pins. It is.
本発明のＰＧＡ型半導体装置は、セラミック基体底部に
設けられた外部端子用ランド部に、ネイルヘッドタイプ
の外部リードピンが半田付けされ、さらに、該外部リー
ドピンを貫通し得るスルーホール部が外部リードピンに
対応して形成され、宜つセラミック基体と外部寸法を同
じくするピン固定用板が具備され、該ピン固定用板はセ
ラミック基体と樹脂等より成る充填材により固着されて
いる。また、本発明のＰＧＡ型半導体装置は、組立後に
簡易に外部リードピンを取り付けることができることを
特徴としており、それにはネイルヘッド部に予め半田ク
ラッドした外部リードピンを片面に樹脂プレートを融着
したピン固定用板にセットした状態の部材を組み上げて
おき組立ての完了したＩＣＣ搭載上セラミックパッケー
ジ基体を用いて、外部リードピン立てを行えば良い。よ
ってピン立て工程においては、外部リードピンのネイル
部をセラミックパッケージ基体のランド部に位置合わせ
した後、溶融圧着するための温度を与え、さらに樹脂＝
ル−トの樹脂を溶融する温度を与えて、ピン固定を完了
する工程を含んでいる。In the PGA type semiconductor device of the present invention, a nail head type external lead pin is soldered to an external terminal land provided at the bottom of the ceramic base, and a through hole portion that can penetrate the external lead pin is provided on the external lead pin. A correspondingly formed pin fixing plate having the same external dimensions as the ceramic base is provided, and the pin fixing plate is fixed to the ceramic base by a filler made of resin or the like. Furthermore, the PGA type semiconductor device of the present invention is characterized in that an external lead pin can be easily attached after assembly. It is sufficient to assemble the members set on the work plate and then use the assembled ICC-mounted ceramic package base to attach external lead pins. Therefore, in the pin setting process, after aligning the nail part of the external lead pin with the land part of the ceramic package base, the temperature for melting and pressing is applied, and then the resin is heated.
It includes the step of applying a temperature to melt the resin in the root to complete the pin fixing.
次に、本発明の実施例について図面を参照して説明する
。第１図（ａ）は本発明の一実施例の断面図である。Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1(a) is a sectional view of an embodiment of the present invention.
セラミックパッケージ基体１は、ＩＣチップ２を搭載し
、このＩＣチップ２は内部配線３とワイヤボンディング
により導通されスルーホール４を介して基体底部のラン
ド部５に電気的に接続される。そして、キャップ６によ
り気密封止される。A ceramic package base 1 mounts an IC chip 2, which is electrically connected to an internal wiring 3 by wire bonding and electrically connected to a land portion 5 at the bottom of the base via a through hole 4. Then, it is hermetically sealed by the cap 6.
こうして組立ての終了した半導体装置は、その後外部リ
ードピン７が取り付けられる。これにはガララエポキシ
、ガラスセラミック等より戊るピン固定用板９がスルー
ホール部１０を通して外部リードピンに挿入され、セラ
ミック基体底部と、樹脂１２により、固着されることで
完了する。但し、外部リードピンはネイルヘッド部８と
セラミック基体底部のランド部と半田１１により電気的
、機械的に接続される。第１図（ｂ）は外部リードピン
立て部の部分断面図である。External lead pins 7 are then attached to the semiconductor device that has been assembled in this way. This is completed by inserting a pin fixing plate 9 made of Galara epoxy, glass ceramic, etc. into the external lead pin through the through-hole portion 10, and fixing it to the bottom of the ceramic base with the resin 12. However, the external lead pin is electrically and mechanically connected to the nail head portion 8 and the land portion on the bottom of the ceramic base by solder 11. FIG. 1(b) is a partial sectional view of the external lead pin stand.
第２図は本発明のＰＧＡ型半導体装置の外部リードピン
取り付は部材であるピン付きピン固定用板の断面図であ
る。FIG. 2 is a sectional view of a pin fixing plate with pins, which is a member for attaching external lead pins to a PGA type semiconductor device of the present invention.
外部リードピン７はネイルヘッド部８に半田クラッド１
１°が施しである。ピン固定用板９には片面に樹脂プレ
ート１２゛が重ねられ、ピン挿入用のスルーホール１０
が設けである。そして、外部リードピンはネイルヘッド
部が樹脂プレート板側に来るようにマルーホールを介し
てピン固定用板に具備される。このピン付きピン固定板
を用いれば、ピンの取り付けがピン立て治具を用いず、
簡易な合わせ治具のみで行え、ピンの半田付けと、ピン
の固定が同時に行うことができる。まず、セラミック基
体底部のランドとピンのネイルヘッド部が合わさるよう
に重ね合わせ、一定の負荷が掛かるように荷重等を掛け
た状態で恒温槽に入れる。The external lead pin 7 connects the solder cladding 1 to the nail head part 8.
1° is alms. A resin plate 12 is superimposed on one side of the pin fixing plate 9, and a through hole 10 for inserting the pin is formed.
is the provision. The external lead pin is mounted on the pin fixing plate through the maruhole so that the nail head portion is on the resin plate side. If you use this pin fixing plate with pins, you can install pins without using a pin stand jig.
This can be done using only a simple matching jig, and pin soldering and pin fixing can be done at the same time. First, the lands on the bottom of the ceramic base and the nail heads of the pins are stacked one on top of the other, and placed in a constant temperature bath under a constant load.
まず、第一温度にてピンにクラッドされていた半田を溶
融させ、ピン立てを行う。次に、第二温度でピン固定用
の樹脂を溶融させて、ピン固定板を固着させピン固定を
行う。ピン固定用板は加工の容易で、かつ安価なガラス
エポキシ板か、ガラスセラミック等を、また充填樹脂は
エポキシ樹脂を用いると良い。First, the solder clad on the pin is melted at a first temperature, and the pin is set up. Next, the resin for pin fixing is melted at a second temperature to fix the pin fixing plate and fix the pins. It is preferable to use a glass epoxy plate or glass ceramic, which is easy to process and inexpensive, as the pin fixing plate, and to use an epoxy resin as the filling resin.
以上説明したように、本発明は、半田により外部リード
ピンを半田付けした後、ピン固定用板を外部リード取り
付は部に重ね樹脂で固着することにより、外部リードピ
ンの付いていないセラミックパッケージを組立工程内で
使用することができるばかりか、加工寸法精度の出るガ
ラスエポキシ板、ガラスセラミック板等を用いてピン固
定を行えばピン取り付は精度が高く得られる。また、ピ
ンを突き当て式にて取り付ける為、ピン用のスルーホー
ルも基体に設ける必要がなく、単に導通を取る目的のス
ルーホール径で良く、内部配線の引き回わしの本数、幅
に支障を与えることなく多ピン化多応が可能となる。ま
た、ピンの半田取り付は部をピン固定用板、及び、樹脂
により固着してしまう為ピン取り付は強度は、コファイ
アタイプのラミネートセラミックタイプと同等なばかり
か、半田実装時の温度下でも、ピン取り付は半田の溶融
を回避することができる。さらには、セラミック基体底
部のスルーホール部の気密がピン取り付けの半田では十
分とは言えず、ハーヌテックシール用のキャップは外部
リードピンの内側にしか設けられなかったのに対し、ピ
ン取り付は部を樹脂モールドしたことで格上に気密性を
も向上させることができる。以上により本発明のＰＧＡ
型半導体装置は、Ａｇ−Ｃｕろう材等により、セラミッ
クパッケージメーカーが高温、還元雰囲気で、外部リー
ドを取り付けていたのに対し、低温で簡易にＩＣの組立
工程の一部として外部リードピンを従来のラミネート型
セラミックパッケージの強度と損傷なく取り付けること
を可能にすることができる。よって組立工程においては
ピン立てを最後に行えば、その前の工程は外部リードピ
ン無くしてパッケージ基体を扱えるので、ハンドリング
、設備対応が容易になる。また、ラミネートタイプのセ
ラミックパッケージを使わずに、単板の絶縁基板に厚膜
印刷した低価格パッケージも可能にすることが出来、信
頼性を低下させることなく低価格のＰＧＡ型半導体装置
を供給することが可能となる。As explained above, the present invention assembles a ceramic package without external lead pins by soldering the external lead pins and then stacking the pin fixing plate on the external lead mounting area and fixing it with resin. Not only can it be used in the process, but pin fixing can be achieved with high accuracy by using a glass epoxy plate, glass ceramic plate, etc., which can produce dimensional accuracy. In addition, since the pins are attached by butting, there is no need to provide a through hole for the pin on the base, and the diameter of the through hole for the purpose of simply establishing continuity is sufficient, and there is no problem with the number and width of internal wiring. It is possible to increase the number of pins and respond without having to provide additional pins. In addition, since the soldered pin part is fixed by the pin fixing plate and resin, the strength of the pin installation is not only equivalent to that of the cofire type laminated ceramic type, but also under the temperature during solder mounting. However, pin attachment can avoid melting the solder. Furthermore, pin-mounted solder was not sufficient to ensure airtightness of the through-hole at the bottom of the ceramic base, and caps for HARNUTECH seals were only provided on the inside of external lead pins, whereas pin-mounted By molding the parts with resin, airtightness can be greatly improved. As described above, the PGA of the present invention
In contrast to ceramic package manufacturers that used Ag-Cu brazing material to attach external leads at high temperatures and in a reducing atmosphere, external lead pins can be easily attached at low temperatures as part of the IC assembly process. It can increase the strength of laminated ceramic packages and allow them to be installed without damage. Therefore, if the pin setting is performed last in the assembly process, the package base can be handled in the previous process without external lead pins, making handling and equipment compatibility easier. In addition, it is possible to create a low-cost package printed with a thick film on a single insulating substrate without using a laminate-type ceramic package, and supply low-cost PGA type semiconductor devices without reducing reliability. becomes possible.
第１図は本発明のＰＧＡ型半導体装置の断面図、第２図
は本発明のピン付きピン固定用板の断面図、第３図は従
来のラミネートセラミックタイプのＰＧＡ型半導体装置
の断面図、第４図は従来の半田ピン立てタイプＰＧＡ型
半導体装置の断面図、第５図は従来のピンかしめタイプ
ＰＧＡ型半導体装置の断面図である。
１・・・・・・セラミックパッケージ基体、２・・・・
・・ＩＣチップ、３・・・・・・内部配線、４・・・・
・・スルーホール、５・・・・・・ランド、６・・・・
・・キャップ、７・・・・・・外部リードピン、８・・
・・・・ネイルヘッド、９・・・・・・ピン固定用板、
１０・・・・・・ピン用スルーホール、１１・・・・・
・半田、１１′・・・・・・半田クラッド、１２・・・
・・・充填樹脂、１２・・・・・・樹脂プレ７ト、１３
・・・・・・ラミネートセラミック基体、１４・・・・
・・ピンかしめ部、１５・・・・・・半田留め、１６・
・・・・・ピンスルーホール部。FIG. 1 is a sectional view of a PGA type semiconductor device of the present invention, FIG. 2 is a sectional view of a pin fixing plate with pins of the present invention, and FIG. 3 is a sectional view of a conventional laminate ceramic type PGA type semiconductor device. FIG. 4 is a sectional view of a conventional solder pin stand type PGA type semiconductor device, and FIG. 5 is a sectional view of a conventional pin caulking type PGA type semiconductor device. 1...Ceramic package base, 2...
...IC chip, 3...Internal wiring, 4...
...Through hole, 5...Land, 6...
...Cap, 7...External lead pin, 8...
... Nail head, 9 ... Pin fixing plate,
10...Through hole for pin, 11...
・Solder, 11'...Solder cladding, 12...
...Filled resin, 12...Resin plate 7, 13
...... Laminated ceramic base, 14...
... Pin caulking part, 15 ... Soldering, 16.
...Pin through hole section.
Claims (1)
子用ランド部にネイルヘッド型の外部リードピンが半田
付けされ、前記外部リードピンを貫通し得スルーホール
部が、前記外部リードピンに対応して形成され、かつ前
記セラミックパッケージ基体と外部寸法を同じくするピ
ン固定用板が具備され、前記ピン固定用板はセラミック
パッケージ基体と樹脂等より成る充填材により固着され
ていることを特徴とするＰＧＡ型半導体装置。 ２、外部端子用の電極パッドを有するセラミックパッケ
ージ基体にＩＣを搭載した後、該外部端子と電気的導通
をとり気密封止する第１工程と、外部端子用リードピン
をピン固定用板に具備する第２工程と、第１工程で組立
てられたセラミックパッケージ基体と第２工程のピン固
定用板を固着しセラミックパッケージ基体の外部端子用
電極パッドと外部端子用リードピンを半田付けする第３
工程とを含むことを特徴とする、ＰＧＡ型半導体装置の
製造方法。[Claims] 1. A nail head type external lead pin is soldered to an external terminal land provided at the lower part of the ceramic package base, and a through hole portion that can pass through the external lead pin is provided in the external lead pin. A pin fixing plate is provided which is formed correspondingly and has the same external dimensions as the ceramic package base, and the pin fixing plate is fixed to the ceramic package base by a filler made of resin or the like. PGA type semiconductor device. 2. After mounting the IC on a ceramic package base having electrode pads for external terminals, a first step of establishing electrical continuity with the external terminals and hermetically sealing the IC, and providing lead pins for external terminals on a pin fixing plate. A second step, and a third step in which the ceramic package base assembled in the first step and the pin fixing plate of the second step are fixed, and the external terminal electrode pads of the ceramic package base and the external terminal lead pins are soldered.
1. A method for manufacturing a PGA type semiconductor device, comprising the steps of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1226083A JPH0387052A (en) | 1989-08-30 | 1989-08-30 | Pga type semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1226083A JPH0387052A (en) | 1989-08-30 | 1989-08-30 | Pga type semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0387052A true JPH0387052A (en) | 1991-04-11 |
Family
ID=16839558
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1226083A Pending JPH0387052A (en) | 1989-08-30 | 1989-08-30 | Pga type semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0387052A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101802988A (en) * | 2007-05-18 | 2010-08-11 | 格罗方德半导体公司 | Chip package with pin stabilization layer |
-
1989
- 1989-08-30 JP JP1226083A patent/JPH0387052A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101802988A (en) * | 2007-05-18 | 2010-08-11 | 格罗方德半导体公司 | Chip package with pin stabilization layer |
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