JPH0385919A - Logic circuit - Google Patents

Abstract

PURPOSE:To decrease a difference between an output rise time and an output fall time by connecting a transistor(TR) of the same kind in series or parallel with each TR in a logic circuit. CONSTITUTION:Same P-channel TRs 24-26 are connected in parallel with P- channel TRs 21-23 respectively and same N-channel TRs 34-36 are connected in series with N-channel TRs 31-33. That is, the same kinds of TRs are connected in parallel or in parallel and since a time constant when an input terminal 1 changes from '0' to '1' is 3RC/2 because of parallel connection and the time constant when the input terminal 1 changes from '1' to '0' is 2RC because of the series connection, then a difference of a maximum of RC/2 is caused. Thus, the difference between an output rise time and an output fall time is decreased.

Description

TECHNICAL FIELD The present invention relates to a logic circuit, and more particularly to a combinational logic circuit configured to include a P-channel type MOS transistor and an N-channel type MO5 transistor.

Conventionally, this type of logic circuit has been constructed by applying the same signal to the gate of a single transistor or to the gates of each of multiple transistors connected in parallel, and applying different signals to the bases of multiple transistors. They were configured to be connected in series or in parallel.

The conventional logic circuit will be explained using FIG. 2.

That is, the input terminals 1-3 are connected to the gates of P-channel type MO3 (hereinafter abbreviated as Pch) transistors 21-23 and the gates of N-channel type MO9 (hereinafter abbreviated as Nch) transistors 31-33, respectively. The sources and drains of the Pch transistors 21 to 23 are connected in series, one of which is connected to the power supply 10 and the other to the output terminal 4. Also, Nchl-transistor 3
1 to 33 have their sources and drains connected in parallel, with one connected to the output terminal 4 and the other connected to the ground 11.
It is connected to the.

With this connection, when all the signals to the input terminals 1 to 3 are "0", all the Pcb transistors 21 to 23 are turned on and all the Neb transistors 31 to 33 are turned off, so that the output terminal 4 becomes "0". It becomes 1”. In other cases, at least one of the P eh transistors is turned off and at least one of the Nch transistors is turned on, so that the output terminal 4 becomes "0". therefore,
This circuit constitutes a three-person Noah circuit.

In other words, in the conventional logic circuit described above, when P eh transistors are connected in series, Nch transistors are connected in parallel, and Pc
When h transistors are connected in parallel, Nch transistors are connected in series.

However, since each transistor has parasitic resistance and parasitic capacitance, Pcht, resistance on the transistor side, customer type, and N
There is a drawback that the resistance on the channel transistor side is greatly different from that of the visitor. Therefore, the delay time from human power to output is a time constant of 17 depending on this resistance and customer type.
? 'E, a large difference occurs between the rise time and fall time of the output.

In addition, in an attempt to obtain high drive capability, each transistor is
Even if you replace it with a parallel connection of an h transistor and an NCh transistor, the parasitic resistance and parasitic capacitance will be connected in parallel at the same time, and the difference between the output rising and falling times will not change much. There is a drawback.

[1] An object of the present invention is to provide a logic circuit which can solve the above-mentioned drawbacks of the conventional art and reduce the difference between the rise time and the fall time.

Structure of the Invention A logic circuit according to the present invention includes a group of MOS transistors of a first conductivity type connected in series with each other and a group of MOS transistors of a second conductivity type connected in parallel, Each transistor of the first conductive fli type MOS transistor group has an MOS transistor of the same conductivity type as each of χ and IL1.
S transistors are connected in parallel, and the second conductivity type M
It is characterized in that a MOS transistor of the same conductivity type is connected in series to each transistor in the OS transistor group.

Example Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 14 is a circuit diagram showing the groove bottom of an embodiment of the logic circuit according to the present invention, and the same parts as those in FIG. 2 are designated by the same reference numerals. In the figure, the logic circuit according to the one-fire embodiment of the present invention has X, Pcl+l- transistors 21-23, respectively.
t t, the same Pch l-transistors 24 to 26
are connected in parallel, and the same Nchl transistors 34 to 36 are connected in series to each of the Net+ transistors 31 to 33.

That is, input terminals 1 to 3 are Pel transistors 21 to 3.
26 and each gate of NCh transistors 31 to 34. The sources and drains of each Pch transistor are connected in parallel, 21, 24, 22, 25, 23, and 26, and further connected in series. One end of the series is connected to the power supply 10, and the other end is connected to the output 4.

The sources and drains of the transistors χ, f L, and Neh are 1, 34.32, 35.33, and 36, respectively.
are connected in series and then in parallel.

One of the parallel terminals is connected to the output terminal 4, and the other is connected to the ground 11.

In a logic circuit with such a configuration, the output terminal will not become "1" unless all input terminals 1 to 3 are set to "0°";
This means that the human-powered Noah circuit is being exploited. This point is similar to FIG. 2. On the other hand, in the logic circuit of this embodiment, since transistors of the same type are connected in series or in parallel, the difference in resistance and state between the Pc11 transistor side and the Nch transistor side becomes small.

That is, if C in FIG. 2 is the parasitic capacitance value, and R is the resistance value between the source and drain of each transistor in the on state, then when the input terminals 2 and 3 are both "1", the input terminal 1 The time constant when the input terminal r1 changes from "0" to "1" is 3RC, and the ■S constant when the input terminal r1 changes from "1" to "0" is RC, so the maximum difference is 2RC. It's going to be a cow.

On the other hand,! In the i'S1 diagram, input terminal 1 is
] The IQ constant when changing from "1" to "1" is 3RC/2 because it is parallel, and the time constant when input terminal 1 changes from "1" to "Oo" is 2RC because it is serial. Therefore, there will be a maximum difference of RC/2.

Therefore, compared to the conventional circuit shown in FIG.
In the circuit shown in the figure, the difference between the output rise time and fall time becomes small.

In this embodiment, the case of a three-person NOR circuit has been described, but it is clear that the present invention can be applied to other types of logic circuits.

For example, there is a logic circuit shown in FIG.

In the figure, the output becomes "01" only when the total °C of input terminals 1 to 3 becomes "1", and in other cases, the output becomes "01".
1'', a well-known NAND circuit is configured.

In such a configuration, if C is the parasitic capacitance value and R is the resistance value between the source and drain of each transistor in the on state, the input terminal 1 will change from "0°" when both input terminals 2 and 3 are "1". The time constant when changing to "1" is 3RC, and the time constant when input terminal 1 changes from "1" to "0" is RC, so a maximum difference of 2RC occurs.

The circuit shown in FIG. 3 is obtained by applying the present invention to the circuit shown in FIG. 4 having such a configuration. In the figure, the time constant when input terminal 1 changes from "0" to "1" is 3RC/2 because it is parallel, and the time constant when input terminal 1 changes from "1" to "0" is 3RC/2. II! Since the i constant is a series, 2
It is RC. Therefore, there will be a maximum difference of RC/2.

Therefore, compared to the conventional circuit shown in FIG.
In the circuit shown in the figure, the difference between the output rise time and the fall time is small.

Note that in Figures 1 and 3, two transistors of the same type are connected in series or in parallel, but three or more transistors may be connected in series or in parallel, and the greater the number, the greater the output. It is clear that the difference between rise time and fall time becomes smaller. However, increasing the number of transistors increases the area occupied by the transistors, which is not a good idea in terms of integration.
Out ) also needs to be large, which is not a good idea.

DETAILED DESCRIPTION OF THE INVENTION As described in detail, the present invention reduces the difference between the rise time and fall time of the ID force by connecting transistors of the same type to each transistor in a logic circuit in series or in parallel. It has the effect of being able to be made smaller.

[Brief explanation of drawings]

1 and 3 are circuit diagrams showing the bottom of a logic circuit according to an embodiment of the present invention, and FIGS. 2 and 4 are circuit diagrams showing adjustment of a conventional logic circuit. Explanation of symbols of main parts 1-3...Input terminal 4...Output terminal 21-26...P-channel type MO3 transistor 3t-36...N Channel type MOS transistor

Claims (1)

[Claims] (1) A group of MOS transistors of a first conductivity type connected in series with each other and a group of MOS transistors of a second conductivity type connected in parallel with each other.
a logic circuit having a group of transistors, the first
MOS transistors of the same conductivity type are connected in parallel to each transistor of the MOS transistor group of the conductivity type, and MOS transistors of the same conductivity type are connected in parallel to each transistor of the MOS transistor group of the second conductivity type. A logic circuit characterized by being connected in series.