JPH038350A - Wiring device - Google Patents

Wiring device

Info

Publication number
JPH038350A
JPH038350A JP1143551A JP14355189A JPH038350A JP H038350 A JPH038350 A JP H038350A JP 1143551 A JP1143551 A JP 1143551A JP 14355189 A JP14355189 A JP 14355189A JP H038350 A JPH038350 A JP H038350A
Authority
JP
Japan
Prior art keywords
gold
pattern layer
copper
connection pattern
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1143551A
Other languages
Japanese (ja)
Other versions
JP2660051B2 (en
Inventor
Tadao Hanagata
花形 忠男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koa Corp
Original Assignee
Koa Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koa Corp filed Critical Koa Corp
Priority to JP1143551A priority Critical patent/JP2660051B2/en
Publication of JPH038350A publication Critical patent/JPH038350A/en
Application granted granted Critical
Publication of JP2660051B2 publication Critical patent/JP2660051B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structure Of Printed Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent the corrosion of gold by copper in a connection pattern layer by using metal, whose conductivity is near the gold and copper and whose softening point is higher than gold and copper and which does not reach chemically on gold and copper, for the connection pattern layer between the electrode of gold and the wiring of copper. CONSTITUTION:An electrode pattern layer 2 of gold is formed on an insulating substrate 1. Next, a connection pattern layer 3, one part of which is superposed on the layer 2, is formed. Next, a conductor wiring pattern layer of copper is superposed on one part of the layer 2 through the layer 3, and thus a conductor wiring pattern layer is formed. In the above constitution, the one consisting of metal, which has conductivity near the conductivities of gold and copper and whose softening point is higher than those of gold and copper and which does not react chemically on gold and copper, and a glass binder is used. Moreover, for this layer 3, it is to be desired that the metal should be 50-90wt.%, and that the glass binder should be 10-50wt.%.

Description

【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) 本発明は、銅を主配線としたプリント配線基板上に電子
部品チップを金でボンディングする場合に用いられる配
線基板などの配線装置に関する。
[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a wiring board, etc. used when electronic component chips are bonded with gold to a printed wiring board with copper as the main wiring. Related to wiring devices.

(従来の技術) 従来のプリント配線基板は、金、銀−パラジウム、銅等
の゛導体を単体で絶縁基板にパターン印刷し、金または
銀−パラジウムのプリント配線基板には金ワイヤーでボ
ンディング、銅のプリント配線基板に、銅ワイヤーでボ
ンディングを行なっていた。そして、金、銀−パラジウ
ムボンディングは通常の雰囲気(空気中)で行ない、銅
ボンディングは、銅が酸化してしまうためN2雰囲気中
で行なっていた。
(Prior art) Conventional printed wiring boards are made by printing a single pattern of a conductor such as gold, silver-palladium, or copper on an insulating substrate, bonding the gold or silver-palladium conductor with gold wire, and Bonding was done with copper wire to the printed wiring board. Gold and silver-palladium bonding was performed in a normal atmosphere (in air), and copper bonding was performed in an N2 atmosphere because copper would be oxidized.

(発明が解決しようとする課題) 上述のように、金や銀−パラジウムのプリント配線基板
に金ワイヤーによってボンディングを行なうことは空気
中で行なうことができるが金や銀−パラジウムが高価で
あるため、大面積のプリント配線基板には不適当である
(Problem to be Solved by the Invention) As mentioned above, bonding to a gold or silver-palladium printed wiring board using gold wire can be done in air, but gold or silver-palladium is expensive. , it is unsuitable for large-area printed wiring boards.

また、銅プリント配線基板に銅ワイヤーでボンディング
をすることは安価であるが、非酸化性のN2雰囲気中で
行なわなければならない。
Also, bonding with copper wire to a copper printed wiring board is inexpensive, but must be done in a non-oxidizing N2 atmosphere.

さらに、銅のプリント配線基板に金ワイヤーでボンディ
ングを施す場合は、銅厚膜の下に金パターンを直接塗布
(接触)すると、合金化してしまい、金がくわれを生じ
て金パターンが消失してしまうという問題がある。
Furthermore, when bonding a copper printed wiring board with gold wire, if the gold pattern is directly applied (contacted) under the thick copper film, it will become alloyed, causing the gold to become hollow and the gold pattern to disappear. There is a problem with putting it away.

本発明の目的は、銅のプリント配線基板に金ワイヤーの
ボンディングによる電子部品を搭載できるようにした配
線装置を提供するものである。
An object of the present invention is to provide a wiring device that can mount electronic components on a copper printed wiring board by bonding gold wires.

〔発明の構成〕[Structure of the invention]

(課題を解決するための手段) 本発明の配線装置は絶縁基板上に印刷形成された電子部
品ボンディング用の金の電極パターン層と、銅の配線パ
ターン層と、前記電極パターン層との接続部を上面に重
合させるとともに配線パターン層との接続部を下面に重
合させた接続パターン層とを有し、前記接続パターン層
は、金と銅との導電度に近い導電度を有し軟化点が金お
よび銅の軟化点より高くかつ金および銅と化学的に反応
しない金属と、ガラス質結合剤とよりなるものである。
(Means for Solving the Problems) The wiring device of the present invention includes a gold electrode pattern layer for electronic component bonding printed on an insulating substrate, a copper wiring pattern layer, and a connection portion between the electrode pattern layer. The connection pattern layer has a conductivity close to that of gold and copper and a softening point. It consists of a metal that has a softening point higher than that of gold and copper and does not chemically react with gold and copper, and a vitreous binder.

また、接続パターン層は、金属50〜90重量%と、ガ
ラス質結合剤10〜50重量%とよりなるものである。
Further, the connection pattern layer is composed of 50 to 90% by weight of metal and 10 to 50% by weight of vitreous binder.

(作用) 本発明の配線装置は、金の電極パターン層と、銅の配線
パターン層の接続部に介在させた接続パターン層は銅に
よる金のくわれを防止する。さらに接続パターン層は金
および銅の導電性に影響を及ぼすことがなく、また焼成
時に軟化して変形したり、銅および金と化学的に反応す
ることがなく、金のくわれ防止作用を確実にする。接続
パターン層の金属に添加されるガラス質結合剤は10重
量%以下であると絶縁基板への印刷時にのりが悪くなり
、また、50重量%以上になると導電性が不良になる。
(Function) In the wiring device of the present invention, the connection pattern layer interposed at the connection portion between the gold electrode pattern layer and the copper wiring pattern layer prevents the gold from being corroded by the copper. Furthermore, the connection pattern layer does not affect the conductivity of the gold and copper, does not soften and deform during firing, and does not chemically react with the copper and gold, ensuring the anti-corrosion effect of the gold. Make it. If the amount of the glassy binder added to the metal of the connection pattern layer is less than 10% by weight, the adhesion will be poor when printing on an insulating substrate, and if it is more than 50% by weight, the conductivity will be poor.

(実施例) 本発明の詳細な説明する。(Example) The present invention will be described in detail.

接続パターン層を形成する金属としては、タングステン
(W)、タンタル(Ta)が用いられ、タングステン、
タンタルは融点が1500℃以上で、銅または金よりも
軟化点が高く、銅または金と化学的に反応せずさらに銅
または金の導電度に近い導電度を有する。
Tungsten (W) and tantalum (Ta) are used as metals forming the connection pattern layer.
Tantalum has a melting point of 1500° C. or higher, a higher softening point than copper or gold, does not chemically react with copper or gold, and has electrical conductivity close to that of copper or gold.

またガラス質結合剤としては、ホウケイ酸鉛やホウケイ
酸バリウムが用いられ、これらの金属とガラス質結合剤
の配合比は金属50〜90重量%、ガラス質結合剤10
〜50重量%である。
Lead borosilicate and barium borosilicate are used as the vitreous binder, and the blending ratio of these metals and the vitreous binder is 50 to 90% by weight of the metal and 10% by weight of the vitreous binder.
~50% by weight.

接続パターン層のガラス質結合剤が50重量%以上にな
ると接続パターン層の導電性が低下し、10%以下にな
るとパターン印刷時ののりが悪くなる。
When the vitreous binder in the connection pattern layer exceeds 50% by weight, the conductivity of the connection pattern layer decreases, and when it exceeds 10%, adhesiveness during pattern printing becomes poor.

次に接続パターン層を形成する材料の配合比の一例を表
1に示す。
Next, Table 1 shows an example of the compounding ratio of materials forming the connection pattern layer.

(以下次頁) 表    1 *ビヒクルは有機バインダ溶液で、例えば有機結合剤と
してのエチルセルロース15重量部を溶剤としてのブチ
ルカルピトール85重量部に溶解したものである。
(See next page) Table 1 *Vehicle is an organic binder solution, for example, 15 parts by weight of ethyl cellulose as an organic binder is dissolved in 85 parts by weight of butylcarpitol as a solvent.

次に接続パターン層を形成するペーストの製造方法を説
明する。
Next, a method for manufacturing a paste for forming a connection pattern layer will be described.

(+1 タングステンと、ホウケイ酸バリウムを秤量す
る。
(+1 Weigh the tungsten and barium borosilicate.

(2)次にタングステンとホウケイ酸バリウムとを混合
しボールミルで1日間攪拌する。
(2) Next, tungsten and barium borosilicate are mixed and stirred in a ball mill for one day.

(3)次に真空オーブン中で175℃1日間保持し、さ
きの混合時に加えたアセトン等の有機溶剤を除去する。
(3) Next, the mixture is kept in a vacuum oven at 175°C for 1 day to remove the organic solvent such as acetone added during the previous mixing.

(4)次にビヒクルを秤量して添加する。(4) Next weigh and add vehicle.

(5)次に3本ロールによって混合する。(5) Next, mix using three rolls.

(6)次に粘度を調整してペースト状の接続パターン層
材料を得る。
(6) Next, the viscosity is adjusted to obtain a paste-like connection pattern layer material.

次に得られた接続パターン層材料を用いた絶縁基板上に
配線パターン層と電極パターン層を形成する方法を第1
図によって説明する。
Next, the first method of forming a wiring pattern layer and an electrode pattern layer on an insulating substrate using the obtained connection pattern layer material is described.
This will be explained using figures.

(1)絶縁基板1上にスクリーン印刷機によって金ペー
ストでポンディングパッドパターンを印刷する。
(1) Print a bonding pad pattern using gold paste on the insulating substrate 1 using a screen printer.

(2)次に100℃で5分間乾燥する。(2) Next, dry at 100°C for 5 minutes.

(3)次に厚膜焼成炉によって空気中で850℃、10
分間焼成し、絶縁基板1上に金の電極パターン層2を形
成する。
(3) Next, heat the film at 850℃ for 10 minutes in air using a thick film firing furnace.
After firing for a minute, a gold electrode pattern layer 2 is formed on the insulating substrate 1.

(4)次に絶縁基板1上にスクリーン印刷機によって前
述の接続パターン層材料ペーストを、一部が金の電極パ
ターン層2上に重なるように印刷する。
(4) Next, the above-mentioned connection pattern layer material paste is printed on the insulating substrate 1 using a screen printer so that it partially overlaps the gold electrode pattern layer 2.

(5)次に100℃で5分間乾燥する。(5) Next, dry at 100°C for 5 minutes.

(6)次に厚膜焼成炉でかつ窒素還元雰囲気中で900
℃〜1000℃で焼成し、金の電極パターン層2上に一
部が重ね合わされた接続パターン層3を形成する。
(6) Next, in a thick film firing furnace and in a nitrogen reducing atmosphere,
C. to 1000.degree. C. to form a connection pattern layer 3 partially overlaid on the gold electrode pattern layer 2.

(7)次に、絶縁基板1上に、スクリーン印刷機によっ
て、銅ペーストを、一部が前記接続パターン層3を介し
て金の電極パターン層2上に重なるようにして印刷する
(7) Next, a screen printer prints copper paste on the insulating substrate 1 so that a portion thereof overlaps with the gold electrode pattern layer 2 via the connection pattern layer 3.

(8)次に、100℃で5分間乾燥する。(8) Next, dry at 100°C for 5 minutes.

(9)次に厚膜焼成炉でかつ窒素還元雰囲気中で、90
0℃〜1000℃で焼成し、金の電極パターン層2の一
部上に接続パターン層3を介して銅の配線パターン層4
を重ね合わせた導体配線バタン層を形成する。
(9) Next, in a thick film firing furnace and in a nitrogen reducing atmosphere,
Baked at 0°C to 1000°C, a copper wiring pattern layer 4 is formed on a part of the gold electrode pattern layer 2 via a connection pattern layer 3.
A conductor wiring batten layer is formed by overlapping the conductor wiring layers.

(io)  次に第2図に示すように上述のようにして
導体配線パターン層が形成された絶縁基板1上に接着剤
5を介してチップ状電子部品6を接着し、このチップ状
電子部品6上の金電極7と、絶縁基板1上の金の電極パ
ターン層2の接続部8とを金ボンディング線9によって
接続する。
(io) Next, as shown in FIG. 2, a chip-shaped electronic component 6 is bonded via an adhesive 5 onto the insulating substrate 1 on which the conductive wiring pattern layer is formed as described above, and the chip-shaped electronic component A gold bonding wire 9 connects the gold electrode 7 on the gold electrode 7 and the connecting portion 8 of the gold electrode pattern layer 2 on the insulating substrate 1 .

以上のようにして、銅の配線パターン層4が印刷配線さ
れた絶縁基板1上にチップ状電子部品6が金ボンディン
グ線9でボンディングされる。
As described above, the chip-shaped electronic component 6 is bonded with the gold bonding wire 9 onto the insulating substrate 1 on which the copper wiring pattern layer 4 is printed and wired.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、絶縁基板上に印刷形成される金の電極
パターン層、銅の配線パターン層の接続部に接続パター
ン層を介在させ、接続パターン層の金属として、導電度
が金および銅に近く、軟化点が金および銅よりも高く、
金および銅と化学的に反応しない金属を用いたため銅が
金に直接接触してくわれを生じるのを防止するとともに
、接続パターン層の介在によっても金と銅の導電度に影
響を及ぼすことがない。
According to the present invention, a connection pattern layer is interposed between a gold electrode pattern layer and a copper wiring pattern layer printed on an insulating substrate, and the conductivity of the metal of the connection pattern layer is higher than that of gold and copper. nearby, has a higher softening point than gold and copper,
Using a metal that does not chemically react with gold and copper prevents the copper from coming into direct contact with the gold and causing cracks, and the intervening connection pattern layer does not affect the conductivity of the gold and copper. .

また絶縁基板上に金の電極パターン層と銅の配線パター
ン層とを混載して接続することができるから、主配線を
銅の配線パターン層とし、電子部品が金のボンディング
線で接続される小部分のみ金の電極パターン層を形成す
れば良く、高価な金の使用量を少くすることができる。
Also, since it is possible to mix and connect a gold electrode pattern layer and a copper wiring pattern layer on an insulating substrate, the main wiring can be made of a copper wiring pattern layer and electronic components can be connected with gold bonding wires. It is only necessary to form a gold electrode pattern layer in that portion, and the amount of expensive gold used can be reduced.

またガラス質結合剤の配合によって接続パターン層の印
刷ののりが良くなり、かつ、ガラス質の介在によっても
導電性が低下するおそれもない。
Furthermore, the adhesion of printing of the connection pattern layer is improved by blending the vitreous binder, and there is no fear that conductivity will be lowered due to the presence of vitreous material.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の配線装置の一実施例を示す断面図、第
2図は同上電子部品搭載状態を示す断面図である。 1・・絶縁基板、2・・電極パターン層、3・・接続パ
ターン層、4・・配線パターン層、6・・電子部品。
FIG. 1 is a cross-sectional view showing an embodiment of the wiring device of the present invention, and FIG. 2 is a cross-sectional view showing a state in which the same electronic components are mounted. 1. Insulating substrate, 2. Electrode pattern layer, 3. Connection pattern layer, 4. Wiring pattern layer, 6. Electronic component.

Claims (2)

【特許請求の範囲】[Claims] (1)絶縁基板上に印刷形成された電子部品ボンディン
グ用の金の電極パターン層と、銅の配線パターン層と、
前記電極パターン層との接続部を上面に重合させるとと
もに配線パターン層との接続部を下面に重合させた接続
パターン層とを有し、 前記接続パターン層は、金と銅との導電度に近い導電度
を有し軟化点が金および銅の軟化点より高くかつ金およ
び銅と化学的に反応しない金属と、ガラス質結合剤とよ
りなることを特徴とする配線装置。
(1) A gold electrode pattern layer for electronic component bonding and a copper wiring pattern layer printed on an insulating substrate,
It has a connection pattern layer in which the connection part with the electrode pattern layer is polymerized on the upper surface and the connection part with the wiring pattern layer is polymerized on the bottom surface, and the connection pattern layer has a conductivity close to that of gold and copper. A wiring device comprising a metal having electrical conductivity, a softening point higher than that of gold and copper, and not chemically reacting with gold and copper, and a glassy binder.
(2)接続パターン層は金属が50〜90重量%、ガラ
ス質結合剤が10〜50重量%であることを特徴とする
請求項1記載の配線装置。
(2) The wiring device according to claim 1, wherein the connection pattern layer contains 50 to 90% by weight of metal and 10 to 50% by weight of vitreous binder.
JP1143551A 1989-06-06 1989-06-06 Wiring device Expired - Lifetime JP2660051B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1143551A JP2660051B2 (en) 1989-06-06 1989-06-06 Wiring device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1143551A JP2660051B2 (en) 1989-06-06 1989-06-06 Wiring device

Publications (2)

Publication Number Publication Date
JPH038350A true JPH038350A (en) 1991-01-16
JP2660051B2 JP2660051B2 (en) 1997-10-08

Family

ID=15341376

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1143551A Expired - Lifetime JP2660051B2 (en) 1989-06-06 1989-06-06 Wiring device

Country Status (1)

Country Link
JP (1) JP2660051B2 (en)

Also Published As

Publication number Publication date
JP2660051B2 (en) 1997-10-08

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