JPH0382145A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH0382145A JPH0382145A JP1217388A JP21738889A JPH0382145A JP H0382145 A JPH0382145 A JP H0382145A JP 1217388 A JP1217388 A JP 1217388A JP 21738889 A JP21738889 A JP 21738889A JP H0382145 A JPH0382145 A JP H0382145A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- semiconductor device
- cap
- solder
- matter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 117
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 238000000034 method Methods 0.000 claims abstract description 8
- 239000000126 substance Substances 0.000 claims abstract description 7
- 239000000463 material Substances 0.000 claims description 18
- 238000002844 melting Methods 0.000 claims description 14
- 230000008018 melting Effects 0.000 claims description 13
- 238000010438 heat treatment Methods 0.000 claims description 2
- 239000006185 dispersion Substances 0.000 claims 5
- 229910000679 solder Inorganic materials 0.000 abstract description 45
- 230000017525 heat dissipation Effects 0.000 abstract description 8
- 239000011800 void material Substances 0.000 abstract description 3
- 230000000694 effects Effects 0.000 description 11
- 230000006866 deterioration Effects 0.000 description 7
- 239000000155 melt Substances 0.000 description 7
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000000919 ceramic Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 229910020658 PbSn Inorganic materials 0.000 description 3
- 101150071746 Pbsn gene Proteins 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000000835 fiber Substances 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052745 lead Inorganic materials 0.000 description 3
- 239000008188 pellet Substances 0.000 description 3
- 239000000654 additive Substances 0.000 description 2
- 229910052797 bismuth Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- KZHJGOXRZJKJNY-UHFFFAOYSA-N dioxosilane;oxo(oxoalumanyloxy)alumane Chemical compound O=[Si]=O.O=[Si]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O KZHJGOXRZJKJNY-UHFFFAOYSA-N 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 229910052863 mullite Inorganic materials 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 230000002195 synergetic effect Effects 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052788 barium Inorganic materials 0.000 description 1
- 229910052790 beryllium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 229910052791 calcium Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000002657 fibrous material Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229920002545 silicone oil Polymers 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置、特に熱放散性の良好な半導体装置
の製造技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor device, and particularly to a technology for manufacturing a semiconductor device with good heat dissipation properties.
〔従来の技術]
半導体装置の高機能・高集積化の要請によって、半導体
素子(チップ)の寸法はより大型化しかつその動作時の
発熱量も増大化する傾向にある。したがって、半導体装
置の信頼性を確保するためには、動作時にチップで発生
した熱を速やかに外部に放散する必要がある。コンピュ
ータ等においては、多数組み込まれる半導体装置を気体
あるいは液体を使用して強制的に冷却する手段が採用さ
れている。[Background Art] Due to the demand for higher functionality and higher integration of semiconductor devices, the dimensions of semiconductor elements (chips) tend to become larger and the amount of heat generated during their operation tends to increase. Therefore, in order to ensure the reliability of a semiconductor device, it is necessary to quickly dissipate the heat generated in the chip during operation to the outside. 2. Description of the Related Art Computers and the like employ means for forcibly cooling a large number of built-in semiconductor devices using gas or liquid.
一方、特願昭61−92032号公報には、半導体装置
のパッケージ外に効率的に熱を放散する技術が開示され
ている。前記公報には、半導体ペレット(チップ)の−
主面とキャップ裏面(パッケージ内壁面)とが間隙充填
用金属(接合体)、すなわち低融点のろう材で接着され
た半導体装置について記載されている。なお、前記半導
体ペレットはCCB (Controlled Co1
1apse Bonding)構造となっていて、電極
であるCCBバンプが前記キャップとともにパンケージ
を構成するパッケージ基板の主面に固定される構造とな
っている。On the other hand, Japanese Patent Application No. 61-92032 discloses a technique for efficiently dissipating heat outside the package of a semiconductor device. The above-mentioned publication states that semiconductor pellets (chips) -
A semiconductor device is described in which the main surface and the back surface of the cap (inner wall surface of the package) are bonded with a gap-filling metal (joint body), that is, a low-melting brazing material. Note that the semiconductor pellet is CCB (Controlled Co1
1apse bonding) structure, in which a CCB bump, which is an electrode, is fixed to the main surface of a package substrate that constitutes a pan cage together with the cap.
CCB構造の半導体装置は、基板に直接半導体素子を固
定する構造と異なり、CCBバンブを介して基板に固定
しているため、半導体素子で発生した熱はCCBバンプ
を経由して基板に伝わり、パッケージ外部に放散される
。したがって、この種の構造の半導体装置では伝熱経路
面積が小さくなる。前記文献に開示される構造では、半
導体ペレットのCCBバンブを有しない上面(背面)を
、充填層を介してキャップの裏面(内壁面)に接続する
構造と威して伝熱経路面積の増大を図り、これによって
熱放散性を高めている。A semiconductor device with a CCB structure is different from a structure in which the semiconductor element is directly fixed to the substrate, but is fixed to the substrate via CCB bumps, so the heat generated in the semiconductor element is transferred to the substrate via the CCB bumps, and the package is damaged. Dissipated to the outside. Therefore, in a semiconductor device having this type of structure, the heat transfer path area becomes small. In the structure disclosed in the above document, the top surface (back surface) of the semiconductor pellet without the CCB bump is connected to the back surface (inner wall surface) of the cap via the filling layer, thereby increasing the heat transfer path area. This improves heat dissipation.
ところで、このような構造の半導体装置において、とき
として熱放散性が悪く特性劣化を起こすものが発生する
ことがある。このような特性劣化を起こした半導体装置
について分析検討した結果、以下の事実が本発明者によ
ってあきらかにされた。Incidentally, in semiconductor devices having such a structure, some devices sometimes have poor heat dissipation properties, causing characteristic deterioration. As a result of analyzing and studying semiconductor devices that have suffered from such characteristic deterioration, the inventors have clarified the following facts.
特性劣化を起こした半導体装置にあっては、前記チップ
とキャップを接合する充填層中に大きな空洞(ボイド)
が認められた。半導体装置の製造(組立)においては、
パッケージの内壁面上に半田板が重ねられるとともに、
前記半田板上に半導体素子が重ねられかつ前記半田板が
加熱処理されて半導体素子とパッケージとの接合が行わ
れる。In semiconductor devices whose characteristics have deteriorated, large cavities (voids) are found in the filling layer that connects the chip and the cap.
was recognized. In the manufacturing (assembly) of semiconductor devices,
A solder plate is stacked on the inner wall of the package, and
A semiconductor element is stacked on the solder plate, and the solder plate is heat-treated to bond the semiconductor element and the package.
この際、パッケージの内壁面と半導体素子の背面半導体
素子の背面とパッケージ内壁面間から抜けるが、一部は
巻き込まれて接合体である半田層(充填層)内に気泡と
なって残留する0本発明者の分析によれば、前記ボイド
はそれぞれが微細でかつ接合面全体に均一に分散してい
る状態であれば、特性劣化が発生する確率は極めて低い
が、前記ボイドが大きなボイドである場合、ボイドの部
分には熱伝達性が必ずしも良好であるとは言えない空気
が存在するため、この大きなボイドに対面する領域では
熱放散が順調に行えず熱上昇が起きて特性が劣化してし
まうことが多い。At this time, the inner wall of the package and the back surface of the semiconductor element escape from between the back surface of the semiconductor element and the inner wall of the package, but some of it gets caught up and remains as bubbles in the solder layer (filling layer) that is the bonded body. According to the inventor's analysis, if each of the voids is fine and uniformly distributed over the entire bonding surface, the probability of property deterioration occurring is extremely low; however, if the voids are large voids. In this case, since there is air in the void area that does not necessarily have good heat transfer properties, heat dissipation cannot be performed smoothly in the area facing this large void, resulting in heat rise and deterioration of characteristics. I often put it away.
本発明の目的は、放熱特性の良好な半導体装置およびそ
の製造方法を提供することにある。An object of the present invention is to provide a semiconductor device with good heat dissipation characteristics and a method for manufacturing the same.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、本発明の半導体装置は、セラミックからなる
パッケージのキャップ内壁面に半導体素子の背面を半田
を介して接続し、この半田を前記半導体素子からキャン
プに熱を伝熱する伝熱体とする構造となっているととも
に、前記半田内には網体が敷設されている。この網体は
その表面が半田との濡れ性が良好なもので形成され、半
田と良く密着している。That is, the semiconductor device of the present invention has a structure in which the back surface of a semiconductor element is connected to the inner wall surface of a cap of a ceramic package via solder, and the solder serves as a heat transfer body that transfers heat from the semiconductor element to the camp. In addition, a net is laid within the solder. The surface of this net is made of a material that has good wettability with solder, and is in good contact with solder.
本発明の他の実施例では、前記実施例において前記半導
体素子とキャップ間に設けられる伝熱体は、常温では硬
化しているが、前記半導体素子の発熱時にはその温度で
軟化溶融する物質で形成されている。したがって、半導
体素子駆動時には、前記伝熱体は軟化溶融し、半導体素
子の背面およびキャップ内壁面に密着する。また、軟化
溶融した物質はパッケージがセラミックで形成されてい
るため、濡れ難く半導体素子背面とキャップ内壁面間か
ら離脱し難くなっている。In another embodiment of the present invention, the heat transfer body provided between the semiconductor element and the cap in the above embodiment is made of a material that is hardened at room temperature, but softens and melts at that temperature when the semiconductor element generates heat. has been done. Therefore, when the semiconductor element is driven, the heat transfer body softens and melts and comes into close contact with the back surface of the semiconductor element and the inner wall surface of the cap. Further, since the package is made of ceramic, the softened and molten substance is difficult to wet and is difficult to separate from between the back surface of the semiconductor element and the inner wall surface of the cap.
上記した手段によれば、本発明の半導体装置は半導体素
子の背面とキャップの内壁面は熱伝導性の良好な半田を
介して接続されていることから、半導体素子で発生した
熱は速やかにキャップに伝達される。また、前記半田内
には半田の濡れ性が良い網体が敷設されていることから
、半田内に空気が巻き込まれてボイドが発生しても、半
田は網体に良く濡れること、網体がボイドを区分けする
ことから、ボイドは網体の網目よりも充分小さなものと
なる。したがって、伝熱経路の一部に大きなボイドが発
生するようなこともなく、局所的に温度が上昇して半導
体素子の特性が劣化するような現象も抑止できる。According to the above-mentioned means, in the semiconductor device of the present invention, the back surface of the semiconductor element and the inner wall surface of the cap are connected through the solder having good thermal conductivity, so that the heat generated in the semiconductor element is quickly transferred to the cap. transmitted to. In addition, since a mesh with good solder wettability is laid inside the solder, even if air gets caught in the solder and voids occur, the solder will wet the mesh well, and the mesh will Since the voids are divided, the voids are sufficiently smaller than the mesh of the net body. Therefore, large voids do not occur in a part of the heat transfer path, and it is possible to prevent a phenomenon where the temperature locally increases and the characteristics of the semiconductor element deteriorate.
また、他の実施例では、前記伝熱体を前記半田の代わり
に常温では固体となり、半導体素子駆動時の熱による温
度では軟化溶融する物質で構成していることから、半導
体素子の駆動時は、前記伝熱体は軟化溶融し、かつ前記
網体および半導体素子背面ならびにキャップ内壁面に密
着するため、さらには網体の作用によってボイドが小さ
なものとなることから、伝熱経路面全体で均一に伝熱が
行えるようになり、半導体素子の安定した動作を保障す
ることができる。In another embodiment, the heat transfer body is made of a substance that becomes solid at room temperature instead of the solder, but softens and melts at the temperature generated by the heat generated when driving the semiconductor element. Since the heat transfer body softens and melts and comes into close contact with the net, the back surface of the semiconductor element, and the inner wall surface of the cap, and furthermore, the voids are reduced by the action of the net, so that the heat transfer path is uniform over the entire surface. As a result, stable operation of the semiconductor device can be guaranteed.
以下図面を参照して本発明の一実施例について説明する
。An embodiment of the present invention will be described below with reference to the drawings.
第1図は本発明の一実施例による半導体装置の要部を示
す模式的断面図、第2図は同じく半導体装置の製造状態
を示す模式的断面図である。FIG. 1 is a schematic cross-sectional view showing essential parts of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a schematic cross-sectional view showing the manufacturing state of the semiconductor device.
この実施例の半導体装置1は、外観的には第1図に示さ
れるように、矩形体からなるパッケージ2と、このパッ
ケージ2の底面に整列配設された複数の電極3とからな
っている。前記パッケージ2は前記電極3を有するベー
ス4と、このベース4の主面側に鑞材からなる接合層5
を介して固定されたキャップ6とによって形成されてい
る。そして、前記パッケージ2の内部には、たとえば、
高速E CL (Emitter−Coupled L
ogic)を構成する半導体素子(チップ)7が配設さ
れている。前記半導体素子7はその一面に多数のCCB
バンプ8が設けられている。これらCCBバンブ8は半
田(PbSn)からなるとともに、たとえば、−辺が8
〜10rr+mとなる矩形体のチップ7においては、5
00〜600個程度設けられている。The semiconductor device 1 of this embodiment, as shown in FIG. . The package 2 includes a base 4 having the electrode 3, and a bonding layer 5 made of a solder material on the main surface side of the base 4.
and a cap 6 fixed thereto. For example, inside the package 2,
High-speed E CL (Emitter-Coupled L
A semiconductor element (chip) 7 constituting the Logic) is disposed. The semiconductor element 7 has a large number of CCBs on one side.
A bump 8 is provided. These CCB bumps 8 are made of solder (PbSn), and have negative sides of, for example, 8.
In the rectangular chip 7 with ~10rr+m, 5
Approximately 00 to 600 are provided.
このようなチップ7は、前記CCBバンブ8を介してベ
ース4に固定されている。ベース4はアルミナ系のセラ
ミックで形成されかつ配線基板構造となっている。そし
て、前記ベース4の一面(内面)には前記チップ7のC
CBバンプ8に対応するパッド9が設けられ、他面(外
面)には前記電極3が設けられている。また、この電極
3および前記パッド9は、一部を図で示す前記ベース4
内に設けられた配線部10を介して電気的に接続されて
いる。前記ベース4は、具体的にはムライト(3A見、
03 ・2SiOりで形成されている。このムライトは
その熱膨張係数αが3.0XIO−”/’Cとなり、前
記チップ7を構成するシリコ7(s+)の熱膨張係数3
. 5 X 10−’/”Cに近似している。したがっ
て、高速ECLが動作して発熱しても、前記チップ7と
ベース4間に大一方、前記チップ7の他面は接合体11
を介してキャップ6の内壁面に固定されている。この接
合体11は前記チップ7で発熱した熱を速やかにキャン
プ6に伝達する役割を果たすべくチップ7およびキャン
プ6と接着性の良いものが選ばれるとともに、熱伝導率
の高いものが選ばれる。また、この接合体11は前記チ
ップ7のCCBバンブ8をベース4に固定した後に接続
されるため、この接合体11による接続時、前記CCB
バンプ8が溶けたりしないような低融点金属、たとえば
、半田(PbSn)が選ばれる。この場合、半田からな
る前記CCBバンブ8の融点が前記接合体11の融点よ
りも高くなるように両者の半田組成が選択される。Such a chip 7 is fixed to the base 4 via the CCB bump 8. The base 4 is made of alumina ceramic and has a wiring board structure. Then, on one surface (inner surface) of the base 4, the C of the chip 7 is provided.
A pad 9 corresponding to the CB bump 8 is provided, and the electrode 3 is provided on the other surface (outer surface). Further, this electrode 3 and the pad 9 are connected to the base 4, a part of which is shown in the figure.
They are electrically connected via a wiring section 10 provided therein. The base 4 is specifically made of mullite (see 3A,
03 ・Made of 2SiO. This mullite has a thermal expansion coefficient α of 3.0
.. 5 x 10-'/''C. Therefore, even if the high-speed ECL operates and generates heat, most of the heat is generated between the chip 7 and the base 4, while the other surface of the chip 7 is connected to the bonded body 11.
It is fixed to the inner wall surface of the cap 6 via. The bonded body 11 is selected to have good adhesion to the chip 7 and the camp 6, and to have high thermal conductivity so that the heat generated by the chip 7 can be quickly transferred to the camp 6. Moreover, since this bonded body 11 is connected after the CCB bump 8 of the chip 7 is fixed to the base 4, when the bonded body 11 is connected, the CCB bump 8 of the chip 7 is connected to the base 4.
A low melting point metal such as solder (PbSn) that will not melt the bumps 8 is selected. In this case, the compositions of both solders are selected so that the melting point of the CCB bump 8 made of solder is higher than the melting point of the joined body 11.
他方、前記半田からなる接合体11と、前記チップ7お
よびキャップ6の内壁面との接着性を良好とするために
、前記チップ7の他面においてはCr / Cu /
A uからなるメタライズ1i12が設けられていると
ともに、前記キャップ6の内壁面にはTi/Ni/Au
からなるメタライズN13が設けられている。なお、前
記接合体11をその作用から伝熱体とも称することにす
る。On the other hand, in order to improve the adhesion between the bonded body 11 made of the solder and the inner wall surfaces of the chip 7 and the cap 6, the other surface of the chip 7 is made of Cr/Cu/
A metallization 1i12 made of Au is provided, and the inner wall surface of the cap 6 is made of Ti/Ni/Au.
A metallization N13 consisting of is provided. Note that the joined body 11 will also be referred to as a heat transfer body due to its function.
また、これが本発明の特徴の一つであるが、前記接合体
11(半田)内には網体14が配設(敷設)されている
。この網体14は、半導体装置の組立時、半田内に空気
が巻き込まれて気泡(ボイド)が発生するようなことが
ある場合、このボイドを網目によって細分化させて大き
なボイドの発生を抑止する役割を果たす。したがって、
網体14の存在によってボイドは網体14の網目よりも
充分小さくなり、かつ網体14によって分散されること
から、大きなボイドの存在による局所部の熱伝導性の低
下による局所的な温度上昇現象も抑止でき、半導体素子
の特性劣化も発生し難くなり、半導体素子は安定して動
作することになる。Further, which is one of the features of the present invention, a net 14 is disposed (laid) within the bonded body 11 (solder). When assembling a semiconductor device, if air is caught in the solder and bubbles (voids) are generated, this mesh body 14 subdivides the voids using the mesh to prevent the generation of large voids. play a role. therefore,
Due to the presence of the net 14, the voids are sufficiently smaller than the mesh of the net 14 and are dispersed by the net 14, so that the presence of large voids prevents a local temperature increase phenomenon due to a decrease in thermal conductivity in a local area. This also suppresses deterioration of the characteristics of the semiconductor element, and the semiconductor element operates stably.
一方、前記網体14は銅や金等の金属線あるいはガラス
繊維やプラスチック繊維等のファイバを編んだものによ
って構成されている。また、この網体14は伝熱性向上
のために少なくとも熱伝導を阻害しないものを選択する
必要があるとともに、この網体14と前記接合体11と
の密着性を高める必要がある。網体14と前記接合体1
1との密着性を高めるためには、網体14は接合体11
との濡れ性が良好な材質なもので形成したり、あるいは
前記網体14の表面に接合体11と濡れ性が良い物質を
コーティングする手段がとられる。この実施例では、接
合体11は低融点金属材料の一つである半田(PbSn
)が用いられる。On the other hand, the net 14 is made of a metal wire such as copper or gold, or a braided fiber such as glass fiber or plastic fiber. Further, in order to improve heat conductivity, it is necessary to select a mesh member 14 that does not inhibit at least heat conduction, and it is also necessary to improve the adhesion between the mesh member 14 and the bonded body 11. Net body 14 and the joined body 1
In order to improve the adhesion with the bonded body 11, the net body 14 is
The net member 14 may be made of a material that has good wettability with the bonded body 11, or the surface of the net member 14 may be coated with a substance that has good wettability with the bonded body 11. In this embodiment, the bonded body 11 is made of solder (PbSn), which is one of the low melting point metal materials.
) is used.
他方、網体14は、半導体素子7の背面とキャップ6の
内壁面にそれぞれ弾力的に接触するような弾性が要求さ
れる。この実施例では、金線で編んだ網体14が使用さ
れている。On the other hand, the mesh body 14 is required to have such elasticity that it can come into elastic contact with the back surface of the semiconductor element 7 and the inner wall surface of the cap 6, respectively. In this embodiment, a mesh body 14 knitted with gold wire is used.
また、前記網体14は、前記半導体素子7の背面から均
一に熱をキャップに放散するために、半導体素子7と同
一寸法あるいはより大きい(広い)寸法となっている。Further, the mesh body 14 has the same size or larger (wider) size than the semiconductor element 7 in order to uniformly dissipate heat from the back surface of the semiconductor element 7 to the cap.
また、半田内に空気が巻き込まれた場合、この空気によ
るボイドを細分化するために、綱目は半田が入り込むこ
とができるのを限度として網目の細かいものが使用され
ている。Furthermore, in order to subdivide the voids caused by the air when air is caught in the solder, a wire with a fine mesh is used to the extent that the solder can enter.
ところで、前記網体14を構成するファイバを、低融点
金属に対して濡れ性が良い材料自身で形成した場合、低
融点金属材料とファイバ材料が反応して融点が上昇する
場合があるが、融点の上昇が好ましくない場合には、低
融点金属に対して濡れ性の良い材料を薄くコーティング
したもので網体14を構成することが望ましい。この場
合、酸素親和性に富む添加物を入れたものをコーティン
グするとよい。前記添加物としては、Li、Ca。By the way, if the fibers constituting the net body 14 are made of a material itself that has good wettability with a low melting point metal, the low melting point metal material and the fiber material may react and the melting point increases; If an increase in the amount of heat is undesirable, it is preferable that the net body 14 is made of a thin coating of a material that has good wettability with respect to a low melting point metal. In this case, it is advisable to coat the material with an additive that has a high affinity for oxygen. The additives include Li and Ca.
Be、 Mg、 Au、 Ba、 Ti、 Ta、 S
、 V等が良く、かつその添加量としては0.1〜2%
が適当である。Be, Mg, Au, Ba, Ti, Ta, S
, V, etc. are good, and the amount added is 0.1 to 2%.
is appropriate.
つぎに、このような半導体装置1の製造(組立)方法に
ついて、第2図を参照しながら説明する。最初に、セラ
ミックからなるキャップ6が用意されかつ裏返し状態に
される。このキャップ6の内壁面にはあらかじめメタラ
イズ層13が設けられている。そこで、このメタライズ
層13上に前述のような網体14.半田板20.裏返し
状態にありかつその下面中央に半導体素子7を取り付け
たベース4が順次重ねられる。前記半導体素子7の下面
にはメタライズ層12が設けられている。Next, a method for manufacturing (assembling) such a semiconductor device 1 will be explained with reference to FIG. First, a ceramic cap 6 is prepared and turned inside out. A metallized layer 13 is previously provided on the inner wall surface of the cap 6. Therefore, on this metallized layer 13, a network 14 as described above is placed. Solder plate 20. The bases 4, which are turned upside down and have the semiconductor element 7 attached to the center of the lower surface thereof, are successively stacked on top of each other. A metallized layer 12 is provided on the lower surface of the semiconductor element 7.
そして、このメタライズ層12が前記半田板20に対面
するようになっている。前記半田板20は半導体素子7
と略同じ大きさとなっている。また、網体14は前記半
導体素子7と同じ大きさまたは望ましくは半導体素子7
よりも僅かに大きな寸法となっている。また、前記キャ
ン160周縁上面には前記ベース4の周縁に対面して接
合層5が設けられている。This metallized layer 12 faces the solder plate 20. The solder plate 20 is the semiconductor element 7
It is approximately the same size. Further, the mesh body 14 has the same size as the semiconductor element 7 or preferably has the same size as the semiconductor element 7.
It is slightly larger than the . Further, a bonding layer 5 is provided on the upper surface of the periphery of the can 160 so as to face the periphery of the base 4.
このように順次重ねられた物品は加熱処理される。この
加熱処理は前記半導体素子7とベース4を接合するCC
Bバンブ8が軟化溶融しない温度で行われるが、前記接
合層5および半田板20は軟化溶融し、前記ベース4と
キャップ6の気密封止が行われるとともに、キャップ6
の内壁面と半導体素子7の背面を接合することになる。The articles stacked one after another in this way are heat treated. This heat treatment is performed during the CC process for bonding the semiconductor element 7 and the base 4.
Although the B bump 8 is not softened and melted, the bonding layer 5 and the solder plate 20 are softened and melted, and the base 4 and the cap 6 are hermetically sealed.
The inner wall surface of the semiconductor element 7 and the back surface of the semiconductor element 7 are bonded to each other.
この際、半田板20は溶け、)容融した半田はキャップ
6の内壁面と半導体素子7の背面間に延在する網体14
の網目内に浸入する。このため、多くの網目からは空気
が抜けることとなる。また、残留した空気も網体14で
区分けられること、網体14に半田が良く濡れることか
ら、広い面積に亘って気泡(ボイド)が発生しなくなり
かつ発生したボイドの大きさも小さなものとなる。At this time, the solder plate 20 is melted, and the molten solder is transferred to the net 14 extending between the inner wall surface of the cap 6 and the back surface of the semiconductor element 7.
Penetrates into the mesh. Therefore, air escapes from many of the meshes. Further, since the remaining air is separated by the net 14 and the solder is well wetted with the net 14, air bubbles (voids) are not generated over a wide area and the size of the generated voids is also small.
したがって、半導体素子7の背面とキャップ6の内壁面
との間の伝熱経路面全域において熱抵抗は均一となる。Therefore, the thermal resistance becomes uniform over the entire heat transfer path surface between the back surface of the semiconductor element 7 and the inner wall surface of the cap 6.
このような実施例によれば、つぎのような効果が得られ
る。According to such an embodiment, the following effects can be obtained.
(1)本発明の半導体装置は、半導体素子の背面が伝熱
体を介してパッケージを構成するキャンプの内壁面に固
定されていることから、半導体素子で発生した熱を前記
伝熱体を介してパンケージ外に放散できるという効果が
得られる。(1) In the semiconductor device of the present invention, since the back surface of the semiconductor element is fixed to the inner wall surface of the camp constituting the package via the heat transfer body, the heat generated in the semiconductor element is transferred via the heat transfer body. This has the effect that it can be dissipated outside the pan cage.
(2)本発明の半導体装置は、半導体素子の背面とキャ
ップの・内壁面間に伝熱体が配設されているが、この伝
熱体中には網体が敷設されていることから、大きな気泡
が存在せず、微細な気泡のみとなっているという効果が
得られる。(2) In the semiconductor device of the present invention, a heat transfer body is disposed between the back surface of the semiconductor element and the inner wall surface of the cap, and since a mesh body is laid in this heat transfer body, The effect is that there are no large bubbles, only fine bubbles.
(3)本発明の半導体装置は、前記のように半導体素子
とキャップとの間に網体を敷設した伝熱体が介在されて
いるが、前記伝熱体と網体とは相互に密着する材質が選
択されていることから、伝熱体と網体とはその界面に隙
間を発生することなく接触するため、熱抵抗は最小とな
るという効果が得られる。(3) In the semiconductor device of the present invention, as described above, a heat transfer body with a net laid between the semiconductor element and the cap is interposed, but the heat transfer body and the net are in close contact with each other. Since the materials are selected, the heat transfer body and the mesh body come into contact with each other without creating a gap at the interface, resulting in the effect that the thermal resistance is minimized.
(4)上記(1)〜(3)により、本発明の半導体装置
は半導体素子とキャップ間に伝熱体が配設されているこ
と、またこの伝熱体中には伝熱体形成時に発生する気泡
を細分化する綱体が設けられていること、前記網体と伝
熱体との密着性が良好なことから、伝熱抵抗は最小とな
り、熱に起因する特性劣化が発生し難くなるという相乗
効果が得られる。(4) According to (1) to (3) above, in the semiconductor device of the present invention, a heat transfer body is disposed between the semiconductor element and the cap, and in this heat transfer body, heat generation occurs during formation of the heat transfer body. Since the wire is provided to subdivide the air bubbles, and the adhesion between the net and the heat transfer body is good, the heat transfer resistance is minimized and property deterioration due to heat is less likely to occur. A synergistic effect can be obtained.
(5)本発明の半導体装置の製造方法によれば、半導体
素子の背面をキャップの内壁面に半田(伝熱体)を介し
て接合する際、半導体素子の背面とキャップ内壁面間に
網体を介在させ、この状態で半田板を溶かして半導体素
子をキャップに固定するため、半導体素子とキャップ間
に空気が巻き込まれて気泡が形成されることがあっても
、気泡は網体の網目毎に分断されること、半田が網体に
濡れ易く網目内の空間を半田で埋め尽くし易いことから
、広い範囲に亘って大きな気泡が形成されることがなく
、気泡が発生しても均一化されるという効果が得られる
。したがって、前記伝熱体はその全領域で熱抵抗は均一
化することから、半導体装置の動作時の熱によって半導
体装置が劣化し難くなる。(5) According to the method for manufacturing a semiconductor device of the present invention, when the back surface of the semiconductor element is bonded to the inner wall surface of the cap via solder (heat conductor), a mesh is formed between the back surface of the semiconductor element and the inner wall surface of the cap. Since the semiconductor element is fixed to the cap by melting the solder plate in this state, even if air is caught between the semiconductor element and the cap and air bubbles are formed, the air bubbles will be removed from each mesh of the mesh. Because the solder easily wets the mesh and fills the space within the mesh with solder, large bubbles do not form over a wide area, and even if bubbles do occur, they are uniform. This has the effect of Therefore, the thermal resistance of the heat transfer body is made uniform over the entire region, so that the semiconductor device is less likely to be deteriorated by the heat generated during operation of the semiconductor device.
(6)本発明の半導体装置の製造においては、前記網体
の材質は少なくともその表面が伝熱体となる半田との濡
れ性が良好な材質で形成されていることから、伝熱体と
の密着性が良くなり、放熱特性の良好な半導体装置を製
造することができるという効果が得られる。(6) In manufacturing the semiconductor device of the present invention, at least the surface of the net is made of a material that has good wettability with the solder that serves as the heat transfer body, so that it has good wettability with the heat transfer body. The effect is that the adhesion is improved and a semiconductor device with good heat dissipation characteristics can be manufactured.
(7)本発明の半導体装置の製造方法においては、半導
体素子とキャップ間に伝熱体を形成する作業は、キャッ
プの内壁面と半導体素子の背面間に網体および半田板(
伝熱体形成素材)を挟み、その後熱を加えて前記半田板
を軟化溶融することによって容易に形成できるという効
果が得られる。(7) In the method for manufacturing a semiconductor device of the present invention, the operation of forming a heat transfer body between the semiconductor element and the cap includes a mesh body and a solder plate (
By sandwiching the heat conductor forming material) and then applying heat to soften and melt the solder plate, it is possible to easily form the solder plate.
(8)上記(1)〜(7)により、本発明によれば半導
体素子で発生した熱をパッケージ外部に効率的に放散で
きる半導体装置を安価に製造することができるという相
乗効果が得られる。(8) According to the above (1) to (7), according to the present invention, a synergistic effect is obtained in that a semiconductor device that can efficiently dissipate heat generated in a semiconductor element to the outside of the package can be manufactured at a low cost.
以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は上記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない、たとえば、第2図の半田
板20と網体14の位置関係が逆でも良く、また第3図
に示されるように、前記半導体素子7の背面とキャップ
6の内壁面との間に形成される接合体11、すなわち伝
熱体11を常温では固体となるが、半導体素子7の動作
時は半導体素子7で発生した熱で軟化溶融する材質で形
成しておいても良い、この構造では、溶けた伝熱体11
が直接半導体素子7の背面、キャップ6の内壁面および
網体14に密着することから、半導体素子で発生した熱
を速やかにかつ全域で放散されるようになる。動作時軟
化溶融する材質としては、たとえばBiが50%、Pb
が30%、Snが20%となる融点が92°Cのもの、
Biが50%、Pbが25%、Snが12.5%。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, the positional relationship between the solder plate 20 and the net 14 shown in FIG. 2 may be reversed, and as shown in FIG. The bonded body 11 to be formed, that is, the heat transfer body 11, may be made of a material that is solid at room temperature but softens and melts with the heat generated by the semiconductor element 7 when the semiconductor element 7 is in operation. Now, the melted heat transfer body 11
Since it is in direct contact with the back surface of the semiconductor element 7, the inner wall surface of the cap 6, and the mesh body 14, the heat generated in the semiconductor element can be quickly dissipated over the entire area. Examples of materials that soften and melt during operation include 50% Bi and Pb.
is 30%, Sn is 20%, and has a melting point of 92°C.
Bi is 50%, Pb is 25%, and Sn is 12.5%.
Cdが12.5%となる融点が60°Cのウッドアロイ
と称されるもの、Biが49.4%、Pbが18%、S
nが11.6%、Inが21%となる融点が58℃のも
のが使用される。なお、前記伝熱体11はベース4とキ
ャップ6を封止する際の温度で沸騰現象を起こすことは
好ましくないが、前記動作時軟化溶融する材質はいずれ
もベース4とキャップ6を接合する封止時、沸騰現象を
起こすものではない。What is called a wood alloy with a melting point of 60°C where Cd is 12.5%, Bi is 49.4%, Pb is 18%, and S
A material with a melting point of 58° C. in which n is 11.6% and indium is 21% is used. Although it is not preferable for the heat transfer body 11 to boil at the temperature used to seal the base 4 and the cap 6, any material that softens and melts during operation is used for the seal that joins the base 4 and the cap 6. It does not cause boiling phenomenon when stopped.
なお、前記動作時軟化溶融する材質は、半導体素子のシ
リコンおよびキャップ母材となるセラミックとの濡れ性
が悪いことから、半導体素子7の背面とキャップ6の内
壁面間から外に溢れでることは殆どない。しかし、溢れ
出てCCBバンプ8側に流れ込むと、CCBバンプ8間
をシコートさせるおそれもあることから、組立前に前記
ベース4と半導体素子7間の間のCCBバンブ8群にお
いて、最外周のCCBバンプ8の外側部分を蒸着処理等
によって絶縁性物質21で被っておいても良い。この絶
縁性物質21としては、絶縁性のシリコンオイル等を塗
布する構造であっても前記実施例同様な効果が得られる
。Note that the material that softens and melts during operation has poor wettability with the silicon of the semiconductor element and the ceramic that is the base material of the cap, so it will not overflow from between the back surface of the semiconductor element 7 and the inner wall surface of the cap 6. There aren't many. However, if it overflows and flows into the CCB bump 8 side, there is a risk that the spaces between the CCB bumps 8 will be coated. The outer portion of the bump 8 may be covered with an insulating material 21 by vapor deposition or the like. Even if the insulating substance 21 is coated with insulating silicone oil or the like, the same effect as in the above embodiment can be obtained.
前記実施例では面実装構造について説明したが、他のパ
ンケージ構造でも前記実施例同様な効果が得られる。Although the surface mount structure has been described in the above embodiment, the same effects as in the above embodiment can be obtained with other pancage structures.
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野である面実装構造の半導体
装置の製造技術に適用した場合について説明したが、そ
れに限定されるものではなく、ピングリッド等地の構造
の半導体装置の製造技術にも適用できる。In the above explanation, the invention made by the present inventor was mainly applied to the manufacturing technology of surface-mounted semiconductor devices, which is the background field of application, but the invention is not limited to this. It can also be applied to the manufacturing technology of semiconductor devices having a uniform structure.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記のとおりであ
る。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
本発明の半導体装置は、半導体素子とキャップ間に伝熱
体が配設されているとともに、前記伝熱体中には伝熱体
形戒時に発生する気泡を細分化する網体が設けられ、さ
らに前記網体と伝熱体とは相互に密着する構造となって
いることから、伝熱抵抗は最小となり、熱放散性が高く
なる。したがって、本発明の半導体装置は熱に起因する
特性劣化が発生し難くなる。In the semiconductor device of the present invention, a heat transfer body is disposed between the semiconductor element and the cap, and a net is provided in the heat transfer body to subdivide air bubbles generated when the heat transfer body is shaped. Since the mesh body and the heat transfer body have a structure in which they are in close contact with each other, heat transfer resistance is minimized and heat dissipation performance is increased. Therefore, in the semiconductor device of the present invention, characteristic deterioration due to heat is less likely to occur.
第1図は本発明の一実施例による半導体装置の要部を示
す模式的断面図、
第2図は同じく半導体装置の製造状態を示す模式的断面
図、
第3図は本発明の他の実施例による半導体装置の要部を
示す模式的断面図である。
1・・・半導体装置、2・・・パッケージ、3・・・電
極、4・・・ベース、5・・・接合層、6・・・キャッ
プ、7・・・半導体素子、8・・・CCBバンプ、9・
・・パッド、10・・・配線部、11・・・接合体(伝
熱体)、12・・・メタライズ層、13・・・メタライ
ズ層、14・・・網体、20・・・半田板、21・・・
絶縁性物質。
第 1
図
第 2
図
2−バブケージ
6−へダ−f7゜
8−CCBバンア
14−基泊佳
4−ベース
7−子導俸束チ
11−蒋合伴
20−早田杖FIG. 1 is a schematic sectional view showing the main parts of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a schematic sectional view showing the manufacturing state of the semiconductor device, and FIG. 3 is another embodiment of the present invention. 1 is a schematic cross-sectional view showing a main part of a semiconductor device according to an example. DESCRIPTION OF SYMBOLS 1... Semiconductor device, 2... Package, 3... Electrode, 4... Base, 5... Bonding layer, 6... Cap, 7... Semiconductor element, 8... CCB Bump, 9・
...Pad, 10...Wiring part, 11...Joint body (heat conductor), 12...Metallized layer, 13...Metallized layer, 14...Network, 20...Solder board , 21...
Insulating substance. Fig. 1 Fig. 2 Fig. 2 - Bab cage 6 - Header - f7゜8 - CCB bumper 14 - Base case 4 - Base 7 - Child guide bundle 11 - Jiang Heban 20 - Hayata cane
Claims (1)
面に固定してなる半導体装置であって、前記半導体素子
とパッケージ間の接合体内には気泡分散体が敷設されて
いることを特徴とする半導体装置。 2、前記気泡分散体は網体で形成されていることを特徴
とする特許請求の範囲第1項記載の半導体装置。 3、前記気泡分散体は前記半導体素子動作時の温度で溶
融状態となる物質で形成されていることを特徴とする特
許請求の範囲第1項記載の半導体装置。 4、前記気泡分散体の少なくとも表面は前記接合体と濡
れ性が良好な材質で形成されていることを特徴とする特
許請求の範囲第1項乃至第3項いずれか記載の半導体装
置。 5、パッケージの内壁面に接合体、半導体素子を順次重
ね合わせ、その後熱処理を行って前記接合体を溶かし、
前記接合体で半導体素子をパッケージの内壁面に固定す
る半導体装置の製造方法であって、前記パッケージの内
壁面と半導体素子との間に接合体を介在させる際気泡分
散体を介在させ、その後前記接合体を溶融させて前記半
導体素子を前記パッケージの内壁面に固定することを特
徴とする半導体装置の製造方法。[Claims] 1. A semiconductor device in which one side of a semiconductor element is fixed to an inner wall surface of a package via a bonded body, wherein a bubble dispersion is laid in the bonded body between the semiconductor element and the package. A semiconductor device characterized by: 2. The semiconductor device according to claim 1, wherein the bubble dispersion is formed of a net. 3. The semiconductor device according to claim 1, wherein the bubble dispersion is made of a substance that becomes molten at a temperature during operation of the semiconductor element. 4. The semiconductor device according to any one of claims 1 to 3, wherein at least the surface of the bubble dispersion is made of a material that has good wettability with the bonded body. 5. Sequentially stack the bonded body and the semiconductor element on the inner wall surface of the package, then perform heat treatment to melt the bonded body,
A method for manufacturing a semiconductor device in which a semiconductor element is fixed to an inner wall surface of a package using the bonded body, wherein a bubble dispersion is interposed when the bonded body is interposed between the inner wall surface of the package and the semiconductor element, and then the A method of manufacturing a semiconductor device, comprising: fixing the semiconductor element to an inner wall surface of the package by melting a bonded body.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1217388A JPH0382145A (en) | 1989-08-25 | 1989-08-25 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1217388A JPH0382145A (en) | 1989-08-25 | 1989-08-25 | Semiconductor device and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0382145A true JPH0382145A (en) | 1991-04-08 |
Family
ID=16703396
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1217388A Pending JPH0382145A (en) | 1989-08-25 | 1989-08-25 | Semiconductor device and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0382145A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5459352A (en) * | 1993-03-31 | 1995-10-17 | Unisys Corporation | Integrated circuit package having a liquid metal-aluminum/copper joint |
USH1699H (en) * | 1995-10-31 | 1997-12-02 | The United States Of America As Represented By The Secretary Of The Navy | Thermal bond system |
US6166445A (en) * | 1997-02-07 | 2000-12-26 | Nec Corporation | Semiconductor device and method for producing same |
KR100446290B1 (en) * | 2001-11-03 | 2004-09-01 | 삼성전자주식회사 | Semiconductor package having dam and fabricating method the same |
JP2012064845A (en) * | 2010-09-17 | 2012-03-29 | Mitsubishi Electric Corp | Semiconductor device and method for manufacturing the same |
JP2014212182A (en) * | 2013-04-18 | 2014-11-13 | 三菱電機株式会社 | Thermal conductive bonding material, and semiconductor device using the same |
-
1989
- 1989-08-25 JP JP1217388A patent/JPH0382145A/en active Pending
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5459352A (en) * | 1993-03-31 | 1995-10-17 | Unisys Corporation | Integrated circuit package having a liquid metal-aluminum/copper joint |
US5658831A (en) * | 1993-03-31 | 1997-08-19 | Unisys Corporation | Method of fabricating an integrated circuit package having a liquid metal-aluminum/copper joint |
USH1699H (en) * | 1995-10-31 | 1997-12-02 | The United States Of America As Represented By The Secretary Of The Navy | Thermal bond system |
US6166445A (en) * | 1997-02-07 | 2000-12-26 | Nec Corporation | Semiconductor device and method for producing same |
KR100446290B1 (en) * | 2001-11-03 | 2004-09-01 | 삼성전자주식회사 | Semiconductor package having dam and fabricating method the same |
JP2012064845A (en) * | 2010-09-17 | 2012-03-29 | Mitsubishi Electric Corp | Semiconductor device and method for manufacturing the same |
JP2014212182A (en) * | 2013-04-18 | 2014-11-13 | 三菱電機株式会社 | Thermal conductive bonding material, and semiconductor device using the same |
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