JPH0381734A - Formation of electrode for display panel - Google Patents

Formation of electrode for display panel

Info

Publication number
JPH0381734A
JPH0381734A JP21912689A JP21912689A JPH0381734A JP H0381734 A JPH0381734 A JP H0381734A JP 21912689 A JP21912689 A JP 21912689A JP 21912689 A JP21912689 A JP 21912689A JP H0381734 A JPH0381734 A JP H0381734A
Authority
JP
Japan
Prior art keywords
electrode
electrodes
mask
etching
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21912689A
Other languages
Japanese (ja)
Inventor
Kenji Okamoto
謙次 岡元
Tetsuro Endo
遠藤 鉄郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP21912689A priority Critical patent/JPH0381734A/en
Publication of JPH0381734A publication Critical patent/JPH0381734A/en
Pending legal-status Critical Current

Links

Classifications

    • CCHEMISTRY; METALLURGY
    • C03GLASS; MINERAL OR SLAG WOOL
    • C03CCHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C15/00Surface treatment of glass, not in the form of fibres or filaments, by etching

Abstract

PURPOSE:To improve production yield by performing etching in which a resist pattern is taken as a mask plural times. CONSTITUTION:When an electrode 2 on a glass substrate 5 is etched by taking the resist pattern as the mask, a short circuit part, etc., occurs between the electrodes 2 by dust 1, etc. When the second etching is performed by using a resist mark whose width of an electrode pattern 3 is wide, the short circuit part of the electrode is excellently etched without the damage of the end part of the electrode 2 caused by the positional deviation of the mask, etc. Thus, the production yield is enhanced in a method etching is performed plural times.

Description

【発明の詳細な説明】[Detailed description of the invention]

〔概 要〕 表示パネルに用いる電極形成方法に関し、たとえゴミの
付着による電極間短絡が生じても、これを救済し得るよ
うにすることを目的とし、絶縁性基板上に電極膜を成膜
し、該電極膜をレジストパターンをマスクとしてエツチ
ングして電極を形成するに際し、前記レジストパターン
をマスクとしてエツチングする工程を複数回施す構成と
する。 〔産業上の利用分野〕 本発明は、表示パネルに用いる電極形成方法に係り、特
に表示パネルの製造歩留りを向上させることのできる電
極形成方法に関する。 〔従来の技術〕 従来、液晶表示パネルなどの表示パネルに用いる各種電
極は、透明導電膜やアルミニウム電極を基板上の全面に
形成し、その上に所定のパターンを有するレジスト膜を
形成し、これをマスクとしてエツチングを行い、不要部
を除去することにより形成していた。 〔発明が解決しようとする課題〕 上記従来の電極形成方法では、レジストの塗布前または
塗布後にゴ兆が付着すると、そのゴごが付着したところ
はレジストをバターニング工程で取り除くことができず
、また、その部分はエツチングできないので、ゴミが電
極パターン間に跨がっていると、電極間短絡が発生する
。 電極間短絡を救済するには、従来は顕微鏡などにより基
板を検査し、電極間短絡の発生箇所を発見した後、先端
がきわめて細い針などの治具を用いて、ゴミやゴ〔が存
在することにより露光現像できなかったレジストを機械
的に取り除き、再度エツチングして電極間短絡を解消し
ていた。 しかし、この方法では、検査によりすべての電極間短絡
を発見することは困難であり、また、発見できても再度
エツチングすると、これまで最適のエツチングが施され
ている正常な電極がオーバーエツチングとなり、電極幅
が設計値よりも細くなると言う問題があった。 ゴξの付着の問題は、作業室内のクリーン度を高めれ為
ば解消するが、部屋のクリーン度を高くするには莫大な
費用がかかり、製造コストの上昇を招く。 本発明は、たとえゴごの付着による電極間短絡が生じて
も、これを救済し得るようにすることを目的とする。 〔課題を解決するための手段〕 本発明は、電極間のタッチが生じた不良パネルに再度レ
ジストを塗布し、既に形威した電極パターンに目合わせ
したレジストパターンを形成し、これをマスクとしてエ
ツチングを施すことにより、電極間の短絡箇所を除去す
る。 〔作 用〕 上述したように電極間の短絡は、ゴミが隣接する2つの
電極間にまたがっているときに生じる。 従って、レジストを一旦剥離した後、再度レジストを塗
布し、既に形威されている電極に目合わせをしてレジス
ト膜を形成すれば、今回もゴミが付着したとしても、そ
のゴミが工回目と同じ場所に乗ることはほとんどない。 従って、1回目の短絡箇所は2回目のエツチングにより
取り除かれ、良好な電極基板が得られる。 また・2回目のパターニングに用いる電極マスクを1回
目のものよりも太くすることにより、目合わせずれによ
る電極の細りを防止することができる。 〔実 施 例〕 本発明の一実施例を第1図(a)〜(d)、および第2
図により説明する。 第1図(alはゴミlが隣接する2本の電極2に跨がっ
て付着した状態を示す要部平面図、中)〜(cl)はT
a)のA−A矢視部断面を製造工程の順に示す要部断面
図、第2図は本実施例の手順を示す流れ図である。 まず、絶縁性基板としてのガラス基板5上に厚さ約17
00人のITO膜をスパッタリング法により形成し
[Summary] Regarding the method for forming electrodes used in display panels, the purpose of this method is to form an electrode film on an insulating substrate in order to be able to repair short circuits between electrodes even if they occur due to adhesion of dust. When forming an electrode by etching the electrode film using the resist pattern as a mask, the etching process is performed multiple times using the resist pattern as a mask. [Industrial Field of Application] The present invention relates to a method for forming electrodes used in display panels, and particularly to a method for forming electrodes that can improve the manufacturing yield of display panels. [Prior Art] Conventionally, various electrodes used in display panels such as liquid crystal display panels are produced by forming a transparent conductive film or an aluminum electrode on the entire surface of a substrate, forming a resist film with a predetermined pattern on top of this, and It was formed by etching using the mask as a mask and removing unnecessary parts. [Problems to be Solved by the Invention] In the conventional electrode forming method described above, if spots are attached before or after applying the resist, the resist cannot be removed in the buttering process where the spots are attached. Further, since that part cannot be etched, if dust straddles the electrode patterns, a short circuit will occur between the electrodes. Conventionally, in order to repair short circuits between electrodes, the board is inspected using a microscope, etc., and after discovering the location of the short circuit between electrodes, a jig such as a needle with an extremely thin tip is used to detect the presence of dust or dirt. Therefore, the resist that could not be exposed and developed was mechanically removed and etched again to eliminate the short circuit between the electrodes. However, with this method, it is difficult to detect all inter-electrode short circuits through inspection, and even if they are found, re-etching will result in over-etching of normal electrodes that have been etched optimally. There was a problem in that the electrode width became narrower than the designed value. The problem of the adhesion of rubber ξ can be solved by increasing the cleanliness of the work room, but increasing the cleanliness of the room costs a huge amount of money, leading to an increase in manufacturing costs. SUMMARY OF THE INVENTION An object of the present invention is to make it possible to repair even if a short circuit between electrodes occurs due to the adhesion of dirt. [Means for Solving the Problems] The present invention reapplies resist to a defective panel in which touch has occurred between electrodes, forms a resist pattern aligned with the already formed electrode pattern, and uses this as a mask for etching. By applying this, short-circuit points between electrodes are removed. [Function] As described above, a short circuit between electrodes occurs when dust straddles two adjacent electrodes. Therefore, if you peel off the resist once, apply it again, align it with the electrode that has already been formed, and form a resist film, even if dust adheres this time, the dust will be removed from the process. We rarely ride in the same place. Therefore, the first short circuit is removed by the second etching, and a good electrode substrate can be obtained. Also, by making the electrode mask used for the second patterning thicker than the one used for the first patterning, it is possible to prevent the electrode from thinning due to misalignment. [Example] An example of the present invention is shown in Figures 1 (a) to (d) and Figure 2.
This will be explained using figures. Figure 1 (al is a plan view of the main part showing the state in which dust l is attached across two adjacent electrodes 2, middle) to (cl) are T
FIG. 2 is a sectional view of main parts taken along line A--A in the order of manufacturing steps in a), and FIG. 2 is a flowchart showing the procedure of this embodiment. First, a film with a thickness of about 17 mm is placed on a glass substrate 5 as an insulating substrate.
00 people's ITO film was formed by sputtering method.

【第
2図の参照】、これの上にレジストを塗布
[Refer to Figure 2], apply resist on top of this

【第2図■参
照】した後、所望パターンを有するフォトマスクを用い
て上記レジスト膜に露光を施し
[See Figure 2 ■] After that, the resist film is exposed to light using a photomask having a desired pattern.

【第2図■参照】、現像
処理を施してレジストパターンを形成する
[Refer to Figure 2 ■], Perform a development process to form a resist pattern.

【第2図■参
照】。 次いでこのレジストパターンをマスクとして、上記IT
O膜を約40℃の塩酸によりエツチングを行い、ITO
からなるストライブ状の電極2を形威し
[See Figure 2 ■]. Next, using this resist pattern as a mask, the above IT
The O film was etched with hydrochloric acid at about 40°C, and the ITO
A striped electrode 2 consisting of

【第2図■参照
】、その後レジストパターンを剥離する
[See Figure 2 ■], then peel off the resist pattern.

【第2図■参照
】。 上記一連の工程中に、第1図(a)に見られるように、
隣接する2本の電極パターン間に跨がってゴミが付着す
ると、ゴえが付着した部分はエツチングが不完全となり
、第1図(b)に示す如く、ゴミが跨がった2本の電極
2間が短絡する。 そこで、得られた電極2のパターンを検査し
[See Figure 2 ■]. During the above series of steps, as shown in Figure 1(a),
If dust adheres across two adjacent electrode patterns, the etching will be incomplete in the area where the dust has adhered, and as shown in Figure 1(b), the two A short circuit occurs between the electrodes 2. Therefore, we inspected the pattern of electrode 2 obtained.

【第2図■
参照】、電極間が短絡していた場合には、再度レジスト
を塗布し
[Figure 2 ■
If there is a short circuit between the electrodes, apply resist again.

【第2図■参照】、フォトマスクを用いて上記
レジスト膜に露光を施す
[See Figure 2 ■], expose the above resist film to light using a photomask.

【第2図■参照】。 なお、上記電極2のパターンの検査は、目視検査でもよ
く、また、電気的に短絡の有無を調ベイ等の方法であっ
てもよく、特に材料を限定する4要はない。 2回目のフォトマスクの電極パターン3は、負1図(C
)に示すように、1回目の電極パターンよ乞ストライプ
幅を広くしておく。 このように電極2に対する電極パターン3の[合わせ余
裕を設けたことにより、電極パターン□の電極2に対す
る目合わせが容易となり、電極)・ターン3の位置ずれ
により、電極2の端部が露Hするおそれがない。従って
、この後、現像、工〉チング処理を施して得られた電極
2は、短絡箇りが除去され、表示欠陥のない表示パネル
が得らする。 本実施例では、3,00X200mmのガラス着板5に
、5本/mmピッチでストライブ状の電祠2(電極間隔
は30μm)を形成したところ、1回目のプロセスでは
70枚中25枚にゴξによ2タツチ不良が生じたが、2
回目のプロセス後に目すべてが良品となった。 ゴミは作業室内のクリーン度に依存するが、本実施例は
クラス100,000という、クリーン度の低い室内で
実施し、上記結果を得たものである。このように本発明
を用いることにより、クリーン度の低い環境においても
、良好な電極基板を形成することが出来る。 但し、2回目のフォトプロセスは目合わせの精度が要求
され、パターンがずれた分だけ電極が細くなる。そこで
、例えばI回目は170μm、  2回目は180pm
という具合に、2回目以降のパターニングでは、1回目
に用いた電極幅よりも太いパターンを用いると、電極が
細くなることがなく、良好な電極基板を形成することが
できる。 以上述べたように、本発明によればクリーン度の低い部
屋でも、大面積にわたり微細な電極パターンを形成する
ことが可能となる。また、これまで不良として廃棄して
いた基板も再生することができ、コストの低下が可能と
なる。 本発明は、液晶用の表示電極以外にも、ELやFDPな
ど、大面積の微細な電極を形成するプロセスにすべて適
用できることは言うまでもない。 また、電極膜を上記一実施例ではITO膜とした例を説
明したが、この電極材料はITOのような透明導電膜に
限らず、金属膜であってもよい・〔発明の効果〕 以上説明した如く本発明によれば、表示用電極の歩留り
を向上することができ、コストの低下に効果がある。
[See Figure 2 ■]. Note that the pattern of the electrode 2 may be inspected by visual inspection, or by a method such as checking the presence or absence of electrical short circuits, and there is no need to particularly limit the material. The electrode pattern 3 of the second photomask is negative 1 (C
), the stripe width of the first electrode pattern is made wider. In this way, by providing an alignment allowance for the electrode pattern 3 with respect to the electrode 2, it becomes easy to align the electrode pattern □ with the electrode 2, and the end of the electrode 2 may be exposed due to misalignment of the electrode pattern □ and the turn 3. There is no risk of it happening. Therefore, in the electrode 2 obtained by subsequent development and processing, short circuits are removed, and a display panel free of display defects is obtained. In this example, strip-shaped electric grout 2 (electrode spacing is 30 μm) was formed on a glass bonded plate 5 of 3,00 x 200 mm at a pitch of 5 wires/mm, and in the first process, 25 out of 70 2 touch defects occurred due to Go ξ, but 2
After the second process, all the products were of good quality. Although the amount of dust depends on the cleanliness of the work room, this example was conducted in a class 100,000 room, which has a low cleanliness level, and the above results were obtained. By using the present invention in this way, a good electrode substrate can be formed even in an environment with a low degree of cleanliness. However, the second photo process requires precision alignment, and the electrode becomes thinner to compensate for the misalignment of the pattern. So, for example, the first time is 170μm, and the second time is 180pm.
In this way, in the second and subsequent patterning, if a pattern is used that is wider than the electrode width used in the first time, the electrode will not become thinner, and a good electrode substrate can be formed. As described above, according to the present invention, it is possible to form a fine electrode pattern over a large area even in a room with low cleanliness. Furthermore, substrates that were previously discarded as defective can be recycled, making it possible to reduce costs. It goes without saying that the present invention can be applied to all processes for forming fine electrodes with large areas, such as EL and FDP, in addition to display electrodes for liquid crystals. Further, in the above embodiment, an ITO film was used as the electrode film, but the electrode material is not limited to a transparent conductive film such as ITO, but may also be a metal film. [Effects of the Invention] As explained above. As described above, according to the present invention, the yield of display electrodes can be improved and costs can be reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明一実施例の説明図、 第2図は本発明一実施例の製造工程を示す図である。 図において、1はゴミ、2は電極、3は電極パターン、
4はレジストパターン、5は絶縁性基板(ガラス基板)
を示す。 不亮明−完於例の就朗図 監気 第 図
FIG. 1 is an explanatory diagram of one embodiment of the present invention, and FIG. 2 is a diagram showing the manufacturing process of one embodiment of the present invention. In the figure, 1 is dust, 2 is an electrode, 3 is an electrode pattern,
4 is a resist pattern, 5 is an insulating substrate (glass substrate)
shows. Furyōmei-Complete example of Shurouzu Kankichuzu

Claims (2)

【特許請求の範囲】[Claims] (1)絶縁性基板(5)上に電極膜を成膜し、該電極膜
をレジストパターンをマスクとしてエッチングして電極
(2)を形成するに際し、前記レジストパターンをマス
クとしてエッチングする工程を複数回施すことを特徴と
する表示パネルの電極形成方法。
(1) When forming an electrode film on an insulating substrate (5) and etching the electrode film using a resist pattern as a mask to form an electrode (2), a plurality of etching steps are performed using the resist pattern as a mask. A method for forming electrodes for a display panel, the method comprising applying the electrodes repeatedly.
(2)前記レジストパターンをマスクとしてエツチング
する工程を複数回施すに際し、2回目以降のレジストパ
ターンの電極部の幅を、1回目よりも太くすることを特
徴とする請求項1記載の表示パネルの電極形成方法。
(2) The display panel according to claim 1, characterized in that when performing the etching step multiple times using the resist pattern as a mask, the width of the electrode portion of the resist pattern is made thicker in the second and subsequent etchings than in the first etching. Electrode formation method.
JP21912689A 1989-08-25 1989-08-25 Formation of electrode for display panel Pending JPH0381734A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21912689A JPH0381734A (en) 1989-08-25 1989-08-25 Formation of electrode for display panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21912689A JPH0381734A (en) 1989-08-25 1989-08-25 Formation of electrode for display panel

Publications (1)

Publication Number Publication Date
JPH0381734A true JPH0381734A (en) 1991-04-08

Family

ID=16730648

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21912689A Pending JPH0381734A (en) 1989-08-25 1989-08-25 Formation of electrode for display panel

Country Status (1)

Country Link
JP (1) JPH0381734A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5618384A (en) * 1995-12-27 1997-04-08 Chartered Semiconductor Manufacturing Pte, Ltd. Method for forming residue free patterned conductor layers upon high step height integrated circuit substrates using reflow of photoresist

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5618384A (en) * 1995-12-27 1997-04-08 Chartered Semiconductor Manufacturing Pte, Ltd. Method for forming residue free patterned conductor layers upon high step height integrated circuit substrates using reflow of photoresist

Similar Documents

Publication Publication Date Title
KR100276225B1 (en) Method and apparatus for preventing of short between pads of lcd
JPH0381734A (en) Formation of electrode for display panel
CN104810312B (en) The preparation method of alignment mark on grid layer
US5451292A (en) Method of manufacturing liquid-crystal elements
JPH02215134A (en) Manufacture of thin film transistor
JP2923990B2 (en) Method of manufacturing flat display panel
JPH05216052A (en) Production of liquid crystal element
JPH0561606A (en) Manufacturing method of input board for coordinate input device
JPS60176022A (en) Manufacture of liquid crystal display element
JP2638069B2 (en) Thin film pattern forming method and active matrix substrate using the same
JPH05224220A (en) Formation of pattern of substrate for liquid crystal display element
JPS6364081A (en) Formation of wire electrode
JPH0337248B2 (en)
JPS6377150A (en) Manufacture of tft matrix
JP2565601B2 (en) Thin film pattern forming method
JPS62260155A (en) Repairing method for thin film pattern
JPH05100236A (en) Production of liquid crystal display element
JPH10293326A (en) Manufacture of liquid crystal display
JPS5927408A (en) Method of forming electrode for display
JPH02251932A (en) Manufacture of nonlinear resistance element
JPS6033533A (en) Electrode for liquid crystal matrix display
JPH0810300B2 (en) Method for manufacturing electrode substrate
JPH025023A (en) Formation of wiring electrode
JPS5927409A (en) Method of forming electrode for display
JPH02217825A (en) Production of thin-film transistor matrix