JPH0380592A - Manufacture of printed wiring board - Google Patents
Manufacture of printed wiring boardInfo
- Publication number
- JPH0380592A JPH0380592A JP21600289A JP21600289A JPH0380592A JP H0380592 A JPH0380592 A JP H0380592A JP 21600289 A JP21600289 A JP 21600289A JP 21600289 A JP21600289 A JP 21600289A JP H0380592 A JPH0380592 A JP H0380592A
- Authority
- JP
- Japan
- Prior art keywords
- plating
- lead
- electroless plating
- conductor pattern
- electrolytic plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 238000007747 plating Methods 0.000 claims abstract description 46
- 239000004020 conductor Substances 0.000 claims abstract description 43
- 238000007772 electroless plating Methods 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 238000011282 treatment Methods 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 7
- 238000009713 electroplating Methods 0.000 claims description 53
- 239000012790 adhesive layer Substances 0.000 claims description 20
- 239000007800 oxidant agent Substances 0.000 claims description 16
- 239000000843 powder Substances 0.000 claims description 11
- 229920006015 heat resistant resin Polymers 0.000 claims description 10
- 239000010410 layer Substances 0.000 claims description 6
- 238000007493 shaping process Methods 0.000 claims 1
- 239000000853 adhesive Substances 0.000 abstract description 6
- 230000001070 adhesive effect Effects 0.000 abstract description 6
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 abstract description 6
- 238000000034 method Methods 0.000 description 34
- 239000002245 particle Substances 0.000 description 31
- 239000003822 epoxy resin Substances 0.000 description 22
- 229920000647 polyepoxide Polymers 0.000 description 22
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 12
- 239000000243 solution Substances 0.000 description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 11
- 229910052802 copper Inorganic materials 0.000 description 11
- 239000010949 copper Substances 0.000 description 11
- RAXXELZNTBOGNW-UHFFFAOYSA-N imidazole Natural products C1=CNC=N1 RAXXELZNTBOGNW-UHFFFAOYSA-N 0.000 description 9
- 239000000654 additive Substances 0.000 description 8
- 230000000996 additive effect Effects 0.000 description 8
- 239000010408 film Substances 0.000 description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 8
- 238000005530 etching Methods 0.000 description 7
- 239000010931 gold Substances 0.000 description 7
- YMWUJEATGCHHMB-UHFFFAOYSA-N Dichloromethane Chemical compound ClCCl YMWUJEATGCHHMB-UHFFFAOYSA-N 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- 239000011347 resin Substances 0.000 description 6
- 238000005520 cutting process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 229910052759 nickel Inorganic materials 0.000 description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- IISBACLAFKSPIT-UHFFFAOYSA-N bisphenol A Chemical compound C=1C=C(O)C=CC=1C(C)(C)C1=CC=C(O)C=C1 IISBACLAFKSPIT-UHFFFAOYSA-N 0.000 description 4
- 239000004109 brown FK Substances 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 3
- 229920003986 novolac Polymers 0.000 description 3
- 238000004080 punching Methods 0.000 description 3
- VTYYLEPIZMXCLO-UHFFFAOYSA-L Calcium carbonate Chemical compound [Ca+2].[O-]C([O-])=O VTYYLEPIZMXCLO-UHFFFAOYSA-L 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- CDBYLPFSWZWCQE-UHFFFAOYSA-L Sodium Carbonate Chemical compound [Na+].[Na+].[O-]C([O-])=O CDBYLPFSWZWCQE-UHFFFAOYSA-L 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000003054 catalyst Substances 0.000 description 2
- KRVSOGSZCMJSLX-UHFFFAOYSA-L chromic acid Substances O[Cr](O)(=O)=O KRVSOGSZCMJSLX-UHFFFAOYSA-L 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 2
- AWJWCTOOIBYHON-UHFFFAOYSA-N furo[3,4-b]pyrazine-5,7-dione Chemical compound C1=CN=C2C(=O)OC(=O)C2=N1 AWJWCTOOIBYHON-UHFFFAOYSA-N 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- -1 permanganate Chemical compound 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000000725 suspension Substances 0.000 description 2
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 235000013405 beer Nutrition 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004841 bisphenol A epoxy resin Substances 0.000 description 1
- 125000000484 butyl group Chemical group [H]C([*])([H])C([H])([H])C([H])([H])C([H])([H])[H] 0.000 description 1
- 229910000019 calcium carbonate Inorganic materials 0.000 description 1
- BGTFCAQCKWKTRL-YDEUACAXSA-N chembl1095986 Chemical compound C1[C@@H](N)[C@@H](O)[C@H](C)O[C@H]1O[C@@H]([C@H]1C(N[C@H](C2=CC(O)=CC(O[C@@H]3[C@H]([C@@H](O)[C@H](O)[C@@H](CO)O3)O)=C2C=2C(O)=CC=C(C=2)[C@@H](NC(=O)[C@@H]2NC(=O)[C@@H]3C=4C=C(C(=C(O)C=4)C)OC=4C(O)=CC=C(C=4)[C@@H](N)C(=O)N[C@@H](C(=O)N3)[C@H](O)C=3C=CC(O4)=CC=3)C(=O)N1)C(O)=O)=O)C(C=C1)=CC=C1OC1=C(O[C@@H]3[C@H]([C@H](O)[C@@H](O)[C@H](CO[C@@H]5[C@H]([C@@H](O)[C@H](O)[C@@H](C)O5)O)O3)O[C@@H]3[C@H]([C@@H](O)[C@H](O)[C@@H](CO)O3)O[C@@H]3[C@H]([C@H](O)[C@@H](CO)O3)O)C4=CC2=C1 BGTFCAQCKWKTRL-YDEUACAXSA-N 0.000 description 1
- ZCDOYSPFYFSLEW-UHFFFAOYSA-N chromate(2-) Chemical compound [O-][Cr]([O-])(=O)=O ZCDOYSPFYFSLEW-UHFFFAOYSA-N 0.000 description 1
- 239000011362 coarse particle Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229960003280 cupric chloride Drugs 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003348 petrochemical agent Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920001225 polyester resin Polymers 0.000 description 1
- 239000004645 polyester resin Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 229910000029 sodium carbonate Inorganic materials 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、プリント配線板の製造方法に関し、特にその
プリント配線板を、いわゆるアディティブプロセスによ
り、導体パターンを比較的安価にかつ迅速に形成する方
法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a printed wiring board, and particularly to a method for manufacturing a printed wiring board, in which a conductor pattern is formed relatively inexpensively and quickly by a so-called additive process. Regarding the method.
近年、電子工業技術の進歩に伴い、電子機器の小型化、
高速化が進んでいる。それに伴い、プリント配線板やL
SIを実装する配線板においても、ファインパターンに
よる高密度化および高い信頼性が要求されるようになっ
てきた。In recent years, with the advancement of electronic industry technology, electronic equipment has become smaller and smaller.
Speeds are increasing. Along with this, printed wiring boards and
Even in wiring boards on which SI is mounted, higher density and higher reliability due to fine patterns are required.
このような要求に応えられる方法として、最近、無電解
めっきにより導体パターンを形成する、いわゆるアディ
ティブプロセスが提唱されている。As a method that can meet these demands, a so-called additive process has recently been proposed in which a conductor pattern is formed by electroless plating.
ところで、アディティブプロセスは、無電解銅めっきを
行う方法であるため、コストと時間がかかる上、さらに
次のような問題点もあった。すなわち、使用するめっき
液が強塩基性であるため、このようなめっき液に長時間
耐えられるめっきレジストが必要であるにも拘わらず、
このようなものは少なく、その選択が困難で、コストも
高くなることである。By the way, since the additive process is a method of performing electroless copper plating, it is costly and time consuming, and also has the following problems. In other words, since the plating solution used is strongly basic, a plating resist that can withstand such a plating solution for a long time is required.
There are few such products, making it difficult to select one and increasing the cost.
このような問題を解決する手段として、従来、導体パタ
ーンを電解めっきにて形成する方法として、例えば、(
1)まず、銅張り積層板にスルーホール用の貫通孔を設
けた後、全面に無電解めっきを施し、次いでめっきレジ
ストをコートしてから電解めっきして導体パターンを形
成し、その後前記めっきレジストを剥離除去してからエ
ツチングを行うことにより、パターン間の銅を除去する
方法、(2)無電解めっき用接着材層を形成した絶縁板
の表面に、無電解めっきを施し、ついでめっきレジスト
を形成してから電解めっきにて導体パターンを形成し、
その後めっきレジストを剥離除去してからエツチングを
行い、パターン間の銅を除去する方法、などが提案され
ている。As a means to solve such problems, conventional methods of forming conductor patterns by electrolytic plating have been used, for example, (
1) First, after providing a through hole for a through hole in a copper-clad laminate, electroless plating is applied to the entire surface, and then a plating resist is coated, electrolytic plating is performed to form a conductor pattern, and then the plating resist is coated with electrolytic plating. (2) Electroless plating is applied to the surface of the insulating plate on which the adhesive layer for electroless plating is formed, and then the plating resist is applied. After forming, a conductor pattern is formed by electrolytic plating,
A method has been proposed in which the plating resist is then peeled off and then etched to remove the copper between the patterns.
しかし、これらの方法は、工程数が多く複雑である上、
エツチング処理が必須となるため高密度化が難しく、さ
らにはパターン精度が悪くなるなどの問題点があり、結
局アディティブプロセスとしてのメリットが減殺される
方法であった。However, these methods require many steps and are complicated.
Since etching processing is required, it is difficult to achieve high density, and there are also problems such as poor pattern accuracy, and in the end, this method diminishes the advantages of an additive process.
以上説明したように、従来方法は、アディティブプロセ
スのメリットを阻害することなく、電解めっきにより導
体パターンを形成することが困難であった。As explained above, in the conventional method, it is difficult to form a conductor pattern by electrolytic plating without impairing the merits of the additive process.
本発明の目的は、従来技術が抱える上述した問題点を克
服することができるプリント配線板の製造方法を完成す
るところにある。An object of the present invention is to complete a printed wiring board manufacturing method that can overcome the above-mentioned problems faced by the prior art.
上述した目的を実現するために、本発明者らは、まず無
電解めっきを施すことにより、取り敢えず導体パターン
の一部と共に電解めっき用リードを薄く形成する。そし
て、その時形成した電解めっき用リードを介してこれに
電流を流すことによって、電解めっきを行い、それによ
って最終的な所定厚の導体パターンを形成するという方
法を開発したのである。In order to achieve the above-mentioned object, the present inventors first perform electroless plating to form a thin lead for electrolytic plating together with a part of the conductor pattern. They then developed a method in which electrolytic plating is performed by passing a current through the electrolytic plating leads formed at that time, thereby forming a final conductor pattern of a predetermined thickness.
・すなわち本発明は、少なくとも以下に示す(a)〜(
c)の工程、すなわち、
(a) 基板上に、まず無電解めっき用接着材層を形
成し、ついでめっきレジストを形成し、その後、無電解
めっきを施すことにより、導体パターンの一部を形造る
と同時に、電解めっき用リードを形成する工程、
(b) 前記(a)工程での無電解めっきにより得ら
れたリードを介して電解めっきを行うことにより、既に
形成した薄肉の前記導体パターンを肥厚化させて所定厚
の導体パターンとする工程、(c) 前記電解めっき
用リードと(b)工程で形成した導体パターンとを絶縁
する工程、
の各工程を経ることを特徴とするプリント配線板の製造
方法である。・That is, the present invention provides at least the following (a) to (
Step c): (a) First, an adhesive layer for electroless plating is formed on the substrate, a plating resist is formed, and then a part of the conductor pattern is formed by electroless plating. (b) performing electrolytic plating via the leads obtained by electroless plating in step (a), thereby forming the already formed thin conductor pattern; A printed wiring board characterized by going through the following steps: (c) insulating the electrolytic plating lead from the conductor pattern formed in step (b). This is a manufacturing method.
前記工程において、無電解めっきにより形成される薄肉
の導体パターンの一部と電解めっき用リードとは、それ
ぞれ2μm以上の厚さにすることが好ましい。In the step, it is preferable that a part of the thin conductor pattern formed by electroless plating and the electrolytic plating lead each have a thickness of 2 μm or more.
前記電解めっき用リードは、基板の外周に沿って形成さ
れた金属層および/または基板内に形成されたバンドで
あることが好ましい。The electrolytic plating lead is preferably a metal layer formed along the outer periphery of the substrate and/or a band formed within the substrate.
前記無電解めっき用接着材層は、酸化剤に対して可溶性
である予め硬化処理された耐熱性微粉末を、硬化処理す
ることにより酸化剤に対して難溶性となる耐熱性樹脂中
に分散させたものを、硬化処理した後、酸化剤で処理す
ることにより形成されることが好ましい。The adhesive layer for electroless plating is made by dispersing heat-resistant fine powder that is soluble in oxidizing agents and cured in advance into a heat-resistant resin that becomes poorly soluble in oxidizing agents through curing treatment. It is preferable that the material is formed by curing the material and then treating it with an oxidizing agent.
本発明では、基板(積層板)上に、まず無電解めっき用
接着材層を形成し、ついで電解めっきに際して用いるめ
っきレジストを配設し、その後導体パターンの一部を形
造る薄肉の導体パターンと共に、この導体パターンと電
気的に導通する電解めっき用リードとを、無電解めっき
をすることによって同時に形成する。In the present invention, an adhesive layer for electroless plating is first formed on a substrate (laminate), then a plating resist used for electrolytic plating is provided, and then a thin conductor pattern forming a part of the conductor pattern is formed. At the same time, electrolytic plating leads electrically connected to this conductor pattern are formed by electroless plating.
次に、前記電解めっき用リードへ電流を流して電解めっ
きを行うことにより、既に無電解めっきにより薄い膜(
#2μm)状に生成している前記導体パターンの上に、
さらに所定の厚さ(10μm〜35μm程度)に肥厚化
させた導体パターンを形成する。その後、かかる電解め
っき用リードと前記導体パターンを絶縁する。Next, by applying current to the electrolytic plating lead to perform electrolytic plating, a thin film (
#2 μm) on the conductor pattern,
Furthermore, a conductive pattern thickened to a predetermined thickness (approximately 10 μm to 35 μm) is formed. Thereafter, the electrolytic plating lead and the conductive pattern are insulated.
このような製造方法では、導体パターンの大半は電解め
っき処理により形成されるため、従来のように無電解め
っきのみを使用して導体パターンの全部を形成する場合
より、導体パターンを低コスト、短時間で形成すること
ができる。さらに、この方法では、めっきレジストの耐
塩基性をそれ程考慮する必要がないため、低価格のめっ
きレジストを用いることができる利点もある。In this manufacturing method, most of the conductor pattern is formed by electrolytic plating, so it is possible to make the conductor pattern at a lower cost and in a shorter time than in the conventional case where the entire conductor pattern is formed using only electroless plating. Can be formed in time. Furthermore, this method does not require much consideration of the base resistance of the plating resist, and therefore has the advantage that a low-cost plating resist can be used.
無電解めっきにより予め形成する薄い導体パターンと薄
い電解めっき用リードの厚さは、それぞれ2μm以上で
あることが望ましい。この理由は、無電解めっき膜の厚
さが2μm未満の場合、充分な電気的導通を果たすこと
ができず、良好な電解めっき処理を行うことができない
からである。It is desirable that the thickness of the thin conductor pattern and the thin lead for electrolytic plating, which are formed in advance by electroless plating, are each 2 μm or more. The reason for this is that if the thickness of the electroless plated film is less than 2 μm, sufficient electrical conduction cannot be achieved and good electrolytic plating treatment cannot be performed.
前記無電解めっき処理としては、無電解銅めっき法、無
電解ニッケルめっき法、無電解スズめっき法、無電解金
めっき法、無電解銀めっき法のいずれの処理でもよいが
、なかでも無電解銅めっき処理が最適である。The electroless plating treatment may be any of electroless copper plating, electroless nickel plating, electroless tin plating, electroless gold plating, and electroless silver plating, but in particular, electroless copper plating may be used. Plating treatment is optimal.
また、前記電解めっき処理は、電解銅めっき法、電解ニ
ッケルめっき法、電解スズめっき法、電解金めっき法、
電解銀めっき法のいずれの処理でもよく、なかでも電解
銅めっき処理は好ましい方法といえる。Further, the electrolytic plating treatment includes electrolytic copper plating method, electrolytic nickel plating method, electrolytic tin plating method, electrolytic gold plating method,
Any of the electrolytic silver plating methods may be used, and among them, electrolytic copper plating is a preferable method.
なお、前記電解めっきを施した上に、さらに異なる種類
の電解めっきを行ったり、ハンダをコートする処理でも
よい。とりわけ電解銅めっき処理を行った後、電解ニッ
ケルめっき処理、電解金めっき処理をそれぞれ行うこと
により、COB (チンプオンボード)基板などで使用
される金線との密着型のよい導体パターンを形成できる
。Note that in addition to the electrolytic plating described above, a different type of electrolytic plating may be performed or a solder coating may be performed. In particular, by performing electrolytic copper plating, followed by electrolytic nickel plating and electrolytic gold plating, it is possible to form conductive patterns that adhere well to gold wires used in COB (chimp-on-board) boards, etc. .
この発明における電解めっき用リードは、例えば基板の
外周部に形成される金属層、あるいは基板内に形成され
るパッドなどである。電解めっき用リードをこのような
形状にする理由は、電解めっき用リードによる基板の有
効面積の損失を最小限にし、なおかつ電解めっき用リー
ドの除去を容易にするためである。前記金属層およびパ
ッドなどは、導体パターンとの電気的導通はリード線に
より得ており、電解めっきを行う際には、この電解めっ
き用リードに電流を流せばよい。なお、前記基板の外周
部に形成される金属層は、環状に形成されたものである
ことが好ましい。The electrolytic plating lead in this invention is, for example, a metal layer formed on the outer periphery of a substrate, or a pad formed within the substrate. The reason why the electrolytic plating lead is shaped like this is to minimize the loss of the effective area of the substrate due to the electrolytic plating lead and to facilitate the removal of the electrolytic plating lead. The metal layer, pad, etc. are electrically connected to the conductive pattern through lead wires, and when performing electrolytic plating, current may be passed through the electrolytic plating leads. Note that the metal layer formed on the outer periphery of the substrate is preferably formed in an annular shape.
次に、本発明における、電解めっき用リードと導体パタ
ーンを絶縁する方法としては、前記電解めっき用リード
と導体パターンとの間を結ぶリード線を切断するか、電
解めっき用リードを剥離する方法が望ましい。このリー
ド線の切断および電解めっき用リードの#J離方法とし
ては、カンティングにより切り取るか、パンチングで打
ち抜くか、切削加工で削るか、エツチングにより溶解し
て剥離する方法が望ましい。Next, as a method of insulating the electrolytic plating lead and the conductor pattern in the present invention, there is a method of cutting the lead wire connecting the electrolytic plating lead and the conductor pattern, or peeling off the electrolytic plating lead. desirable. As a method for cutting the lead wire and separating #J from the lead for electrolytic plating, it is desirable to cut by canting, punching, cutting, or dissolving and peeling by etching.
特に、電解めっき用リードのうち、基板外周部に沿って
形成されている金属層は、外形加工の際、カッティング
されることが望ましい。また、前記電解めっき用リード
としてのパッドは、パンチング、切削加工、エツチング
により除去するか、あるいは、導体パターンとつながる
リード線のうち、不必要な部分を除去して実装用パッド
とすることが望ましい。In particular, it is desirable that the metal layer of the electrolytic plating lead, which is formed along the outer periphery of the substrate, be cut during contour processing. Further, it is preferable that the pads serving as leads for electrolytic plating be removed by punching, cutting, or etching, or by removing unnecessary portions of the lead wires connected to the conductor pattern to use as mounting pads. .
つぎに、本発明で使用される無電解めっき用接着材層は
、酸化剤に対して可溶性の予め硬化処理された耐熱性微
粉末が、硬化処理することにより酸化剤に対して難溶性
となる耐熱性樹脂中に分散されてなるものを硬化処理し
た後、酸化剤で処理することにより形成されることが望
ましい。例えば、酸化剤に対して難溶性を示す耐熱性樹
脂中に、平均粒径2〜10μmの耐熱性樹脂粒子と平均
粒径2μm以下の耐熱性樹脂微粉末との混合物、平均粒
径2〜10μmの耐熱性樹脂粒子の表面に平均粒径2μ
m以下の耐熱性樹脂微粉末もしくは平均粒径2μm以下
の無機微粉末のいずれか少なくとも1種を付着させてな
る擬似粒子、または平均粒径2〜10μmの大きさとし
た凝集粒子、
の内から選ばれるいずれか少なくとも1種の粒子;すな
わち、酸化剤に対して可溶性の耐熱性粒子を含有させた
ものを、硬化処理した後、酸化剤で処理することにより
形成した接着材層であることが好ましい。この接着材層
は、酸化剤に対する溶解度の相違により、表面に多数の
アンカーを形造った表面を有しており、ビール強度、プ
ル強度などのめっき膜の密着強度を向上させることがで
きる。Next, the adhesive layer for electroless plating used in the present invention is made of heat-resistant fine powder that is soluble in oxidizing agents and has been hardened in advance, and becomes hardly soluble in oxidizing agents through hardening treatment. It is desirable to form the material by curing a material dispersed in a heat-resistant resin and then treating it with an oxidizing agent. For example, a mixture of heat-resistant resin particles with an average particle size of 2 to 10 μm and heat-resistant resin fine powder with an average particle size of 2 μm or less in a heat-resistant resin that is poorly soluble in oxidizing agents, or a mixture of heat-resistant resin particles with an average particle size of 2 to 10 μm or less The average particle size is 2μ on the surface of the heat-resistant resin particles.
Pseudo-particles formed by adhering at least one of heat-resistant resin fine powder with a particle size of 2 μm or less or inorganic fine powder with an average particle size of 2 μm or less, or agglomerated particles with an average particle size of 2 to 10 μm. In other words, it is preferable that the adhesive layer is formed by curing a material containing heat-resistant particles soluble in an oxidizing agent and then treating it with an oxidizing agent. . This adhesive layer has a surface with a large number of anchors formed thereon due to the difference in solubility to the oxidizing agent, and can improve the adhesion strength of the plating film, such as beer strength and pull strength.
上記接着材層形成に際して用いる前記酸化剤ととしは、
クロム酸、クロム酸塩、過マンガン酸塩、オゾンなどを
使用することができ、また、耐熱性粒子を構成する樹脂
としては、エポキシ樹脂、ポリエステル樹脂、ビスマレ
イミド−トリアジン樹脂の中から選ばれるいずれか少な
くとも1種を用いることができるが、なかでもエポキシ
樹脂は好適である。また、酸化剤に対して可溶性を示す
前記無機微粉末としては、例えば炭酸カルシウムを使用
する。The oxidizing agent used in forming the adhesive layer includes:
Chromic acid, chromate, permanganate, ozone, etc. can be used, and as the resin constituting the heat-resistant particles, any resin selected from epoxy resin, polyester resin, and bismaleimide-triazine resin can be used. At least one type of resin can be used, and among them, epoxy resin is preferred. Further, as the inorganic fine powder that is soluble in an oxidizing agent, for example, calcium carbonate is used.
実施例1
(1) ヘンシヱルミキサー(三井三池化工機製、F
MIOB型)で攪拌中の、エポキシ樹脂粒子(東し製、
トレパールEP−B、平均粒径3.9 p m)200
gを51のアセトン中に分散させたエポキシ樹脂粒子
懸濁液中に、アセトン11に対してエポキシ樹脂(三井
石油化学製、商品名T A −1800)を30gの割
合で溶解させたアセトン溶液中に、エポキシ樹脂粉末(
東し製、トレバールEP−B。Example 1 (1) Hensiel mixer (manufactured by Mitsui Miike Kakoki, F
Epoxy resin particles (manufactured by Toshi,
Trepearl EP-B, average particle size 3.9 pm) 200
In an acetone solution, epoxy resin (manufactured by Mitsui Petrochemicals, trade name TA-1800) was dissolved at a ratio of 30 g to 11 g of acetone in an epoxy resin particle suspension prepared by dispersing 51 g of acetone in acetone. , epoxy resin powder (
Made by Toshi, Trevor EP-B.
平均粒径0.5μm) 300gを分散させた懸濁液を
滴下することにより、上記エポキシ樹脂粒子表面にエポ
キシ樹脂粉末を付着せしめ、その後上記アセトンを除去
した後、150℃に加熱し、いわゆるエポキシ樹脂の擬
似粒子を作成した。このエポキシ樹脂擬似粒子は、平均
粒径が4.3μmであり、約75重量%が平均粒径を中
心として±2μmの範囲内に存在していた。The epoxy resin powder was attached to the surface of the epoxy resin particles by dropping a suspension in which 300 g (average particle size: 0.5 μm) was dispersed, and after the acetone was removed, the so-called epoxy resin was heated to 150°C. We created pseudo-particles of resin. The epoxy resin pseudoparticles had an average particle size of 4.3 μm, and about 75% by weight existed within a range of ±2 μm around the average particle size.
(2) 前記(1)で調製したエポキシ樹脂擬似粒子5
0重量部、フェノールノボラック型エポキシ樹脂(油化
シェル製、商品名 E−154) 60重量部、ビスフ
ェノールA型エポキシ樹脂(油化シェル製、商品名 E
−1001) 40重量部、イミダゾール硬化剤(四国
化成製、P4MH2)4重量部からなるものにブチルカ
ルピトールを加え、粘度が120 cpとなるようにホ
モデイスパー分散機で調整し、接着剤溶液を得た。(2) Epoxy resin pseudoparticles 5 prepared in (1) above
0 parts by weight, phenol novolac type epoxy resin (manufactured by Yuka Shell, trade name E-154) 60 parts by weight, bisphenol A epoxy resin (manufactured by Yuka Shell, trade name E-154)
-1001) and 4 parts by weight of an imidazole curing agent (manufactured by Shikoku Kasei Co., Ltd., P4MH2), butyl carpitol was added, and the viscosity was adjusted to 120 cp using a homodisper disperser to obtain an adhesive solution. Ta.
(3)そこで、ガラスポリイミド基板l(東芝ケミカル
製、商品名:東芝デュライト積層板−EL)に、前記工
程(2)で得られた接着材溶液を塗布した後、100℃
で1時間、さらに150℃で5時間乾燥硬化させて厚さ
20μmの接着材層2を形成した。(3) Therefore, after applying the adhesive solution obtained in the step (2) to a glass polyimide substrate l (manufactured by Toshiba Chemical Co., Ltd., trade name: Toshiba Durite Laminated Board-EL),
The adhesive layer 2 was dried and cured at 150° C. for 1 hour and then at 150° C. for 5 hours to form an adhesive layer 2 with a thickness of 20 μm.
(4) 前記工程(3)で得られた接着材層2を破戒し
た基板1を、クロム酸500 g / It水溶液から
なる酸化剤に70℃で15分間浸漬し、接着材層2の表
面を粗化してから、中和溶液(シブレイ社製、商品名:
P N−950)に浸漬し水洗した。(4) The substrate 1 from which the adhesive layer 2 obtained in step (3) has been removed is immersed in an oxidizing agent consisting of 500 g of chromic acid/It aqueous solution for 15 minutes at 70°C to immerse the surface of the adhesive layer 2. After roughening, neutralize solution (manufactured by Sibley, trade name:
PN-950) and washed with water.
(5) 上記工程(4)で得られる接着材層2の表面を
粗化した基板1に、パラジウム触媒(シブレイ社製、商
品名:キャタボジソト44)を付与して接着材層2の表
面を活性化させた。(5) A palladium catalyst (manufactured by Sibley, trade name: Catabodisoto 44) is applied to the substrate 1 on which the surface of the adhesive layer 2 obtained in step (4) has been roughened to activate the surface of the adhesive layer 2. turned into
(6) 上記基板1上に、感光製ドライフィルムをうξ
ネートし、所望の導体回路パターンと電解めっき用リー
ドが描画されたマスクフィルムを通して紫外線露光させ
、画像を焼き付けた。ついで、5%炭酸ナトリウム溶液
で現像し、めっき用レジスト3を形成した。(6) Place a photosensitive dry film on the substrate 1 ξ
The film was exposed to ultraviolet light through a mask film on which a desired conductor circuit pattern and leads for electrolytic plating had been drawn, and the image was printed. Then, it was developed with a 5% sodium carbonate solution to form a plating resist 3.
(7) 第1表に示す組成の無電解銅めっき液に30分
間浸漬して、無電解めっき処理を施してフラッシュめっ
き(薄付けめっき)することにより、厚さ2μmの導体
パターンを構成するその一部4と、基板の外周部に形成
した電解めっき用リード6と、およびパターン4とリー
ド6とを結ぶリード線5とを形成した。(7) By immersing it in an electroless copper plating solution having the composition shown in Table 1 for 30 minutes and performing electroless plating treatment, flash plating (thin plating) is performed to form a 2 μm thick conductor pattern. A portion 4, an electrolytic plating lead 6 formed on the outer periphery of the substrate, and a lead wire 5 connecting the pattern 4 and the lead 6 were formed.
(8)電解めっきり−ド6に入力端子7を接続したのち
電流を流し、第2表に示される条件で電解めっきを70
分間行い、厚さ30μmの導体パターンを形成した。(8) After connecting the input terminal 7 to the electrolytic plate 6, apply current and conduct electrolytic plating for 70 minutes under the conditions shown in Table 2.
This was carried out for a minute to form a conductor pattern with a thickness of 30 μm.
第2表
電解めっきの条件
(9) 基板の外周部をカッティングして、電解めっき
リード6部分を切り取り、プリント配線板を得た。Table 2 Electrolytic plating conditions (9) The outer periphery of the board was cut to remove 6 electrolytic plating leads to obtain a printed wiring board.
実施例2
(1) エポキシ樹脂粒子(東し製、トレパールEP−
B、平均粒径0.5μm)を熱風乾燥機内に装入し、1
80℃で3時間加熱処理して凝集結合させた。この凝集
結合させたエポキシ樹脂粒子を、アセトン中に分散させ
、ボールミルにて5時間解砕した後、風力分級機を用い
て分級しエポキシ樹脂凝集粒子を作成した。このエポキ
シ樹脂凝集粒子は、平均粒径が約3.5μmであり、約
68重量%が平均粒径を中心として±2μ川の範囲に存
在していた。Example 2 (1) Epoxy resin particles (Trepar EP- manufactured by Toshi)
B, average particle size 0.5 μm) was charged into a hot air dryer, and 1
The mixture was heat-treated at 80° C. for 3 hours to form a cohesive bond. The aggregated and bonded epoxy resin particles were dispersed in acetone, crushed in a ball mill for 5 hours, and then classified using an air classifier to produce aggregated epoxy resin particles. The average particle size of the epoxy resin aggregated particles was about 3.5 μm, and about 68% by weight existed within a range of ±2 μm around the average particle size.
(2) 前記工程(1)で調製したエポキシ樹脂擬似粒
子50重量部、フェノールノボラック型エポキシ樹脂(
油化シェル製、商品名E−154)60重量部、ビスフ
ェノールA型樹脂(油化シェル製、E −1001)
40重量部、イミダゾール硬化剤(四国化成製、2P4
MH2)4重量部からなるものにブチルカルピトールを
加え、接着剤溶液とした。(2) 50 parts by weight of the epoxy resin pseudoparticles prepared in step (1) above, phenol novolac type epoxy resin (
Yuka Shell Co., Ltd., trade name E-154) 60 parts by weight, bisphenol A type resin (Yuka Shell Co., Ltd., E-1001)
40 parts by weight, imidazole curing agent (Shikoku Kasei, 2P4
Butylcarpitol was added to 4 parts by weight of MH2) to prepare an adhesive solution.
(3〉 前記工程(2〉で調製した接着剤溶液を用いて
、前記実施例1の工程(3)〜(6)に示される処理を
施し、厚さ3μmの無電解めっき処理を行って、導体パ
ターンの一部4と、基板1の中心に無電解めっき用リー
ドであるバンド9とを形成した。(3) Using the adhesive solution prepared in step (2), perform the treatments shown in steps (3) to (6) of Example 1, and perform electroless plating to a thickness of 3 μm, A portion 4 of the conductor pattern and a band 9 serving as a lead for electroless plating were formed at the center of the substrate 1.
(4) ついで、電解めっき用の前記パッド9に電流を
流し、第2表に示される条件で電解銅めっき処理を行い
、厚さ35μmの導体パターン8を形成した。(4) Next, a current was applied to the pad 9 for electrolytic plating, and electrolytic copper plating was performed under the conditions shown in Table 2 to form a conductor pattern 8 with a thickness of 35 μm.
(5) パフ研磨を行い、基板表面を平滑化した後、前
記電解めっき用パッド9をドリルを用いて切削加工によ
り除去し、プリント配線板を得た。(5) After performing puff polishing to smooth the substrate surface, the electrolytic plating pad 9 was removed by cutting using a drill to obtain a printed wiring board.
実施例3
(1) フェノールノボラック型エポキシ樹脂(油化
シェル製、E−154)60重量部、ビスフェノールA
型エポキシ樹脂(油化シェル製E −1001)40重
量部、イミダゾール硬化剤(四国化成製、2P4MH2
)4重量部、アンカー形成用の粗粒子及び、微粉末とし
てエポキシ樹脂粉末(東し製、トレパールEP−B、平
均粒径3.9μm)10重量部およびエポキシ樹脂(東
し製、トレバールEP−B、平均粒径0.5μm )
25重量部からなるものにブチルカルピトールを加え、
接着剤溶液を調製した。Example 3 (1) 60 parts by weight of phenol novolac type epoxy resin (manufactured by Yuka Shell, E-154), bisphenol A
40 parts by weight of type epoxy resin (Yuka Shell E-1001), imidazole curing agent (Shikoku Kasei, 2P4MH2)
) 4 parts by weight, coarse particles for anchor formation, 10 parts by weight of epoxy resin powder (Torepar EP-B, average particle size 3.9 μm, manufactured by Toshi) as fine powder, and 10 parts by weight of epoxy resin (Torepar EP-B, manufactured by Toshi). B, average particle size 0.5 μm)
Adding butylcarpitol to 25 parts by weight,
An adhesive solution was prepared.
(2) 実施例1の工程(3)と同様の方法により、接
着材層を基板1の両面に形成した後、実施例工の工程(
4)に示される方法により、接着材層2の粗化を行い、
粗化面2′を形成した。(2) After forming an adhesive layer on both sides of the substrate 1 by the same method as step (3) of Example 1, the process of Example 1 (
Roughen the adhesive layer 2 by the method shown in 4),
A roughened surface 2' was formed.
(3) スルーホール形成用の貫通孔10をドリルで形
成した。(3) A through hole 10 for forming a through hole was formed using a drill.
(4〉 基板1上にパラジウム触媒(シブレイ社製、商
品名:キャタボジソト44)を付与して接着材層2の粗
化面2′を活性化させた。(4) A palladium catalyst (manufactured by Sibley, trade name: CATABODISOTO 44) was applied onto the substrate 1 to activate the roughened surface 2' of the adhesive layer 2.
(5) 実施例1の工程(6)の方法により、めっきレ
ジスト3を基板1の両面に形威し、次いで実施例1の工
程(7〉の方法により、厚さ3μmの無電解銅めっき処
理を行って、導体パターン4と、リード線5と、および
電解めっき用リードとしてのパッド9を形成した。(5) Plating resist 3 is formed on both sides of the substrate 1 by the method of step (6) of Example 1, and then electroless copper plating is applied to a thickness of 3 μm by the method of step (7>) of Example 1. A conductor pattern 4, a lead wire 5, and a pad 9 as a lead for electrolytic plating were formed.
(6) 前記リード用パッド9へ電流を流し、第2表に
示す条件にて電解銅めっきを施し、厚さ30μmの導体
パターン8とスルーホール11を形威した。(6) A current was applied to the lead pad 9 and electrolytic copper plating was performed under the conditions shown in Table 2 to form a 30 μm thick conductor pattern 8 and through hole 11.
(7)前記パッド9をパンチングで打抜き除去してプリ
ント配線板を得た。(7) The pad 9 was removed by punching to obtain a printed wiring board.
実施例4
本実施例は基本的には実施例2と同様であるが、電解め
っき用リードとしてのパッドを除去するために、感光製
ドライフィルム(デュポン社製、商品名:リストン10
51)をラミレートして、露光現像することにより、前
記パッド9以外の部分にエツチングレジスト12を形威
し、塩化第二銅エツチング溶液で電解めっきリード用パ
ッド9を溶解除去した。ついでエツチングレジストを塩
化メチレンで剥離してプリント配線板を得た。Example 4 This example is basically the same as Example 2, but in order to remove the pads as leads for electrolytic plating, a photosensitive dry film (manufactured by DuPont, trade name: Riston 10) was used.
51) was laminated and exposed and developed to form an etching resist 12 on the parts other than the pad 9, and the electrolytic plating lead pad 9 was dissolved and removed using a cupric chloride etching solution. Then, the etching resist was removed with methylene chloride to obtain a printed wiring board.
実施例5
本実施例では、実施例1の工程(1)〜(8)までの処
理を施した後、ニッケルめっき13を施し、ついで金め
っき14を施した。この後、電解めっき用リード6をカ
ッティングして、めっきレジストを塩化メチレンを用い
て剥離して、プリント配線板を作成した。Example 5 In this example, after processing steps (1) to (8) of Example 1, nickel plating 13 was applied, and then gold plating 14 was applied. Thereafter, the electrolytic plating lead 6 was cut, and the plating resist was peeled off using methylene chloride to create a printed wiring board.
Ni/Auめっきを施した基板は、金線などを用いてワ
イヤボンディングを行う際、導体パターンと金線との密
着性が改善されるため、COB (チップオンボード)
用基板として、好適に用いることができる。Ni/Au plated substrates improve the adhesion between the conductor pattern and the gold wire when performing wire bonding using gold wire, etc., making it suitable for COB (chip on board).
It can be suitably used as a substrate.
実施結果について;
以上実施例1〜5に説明した方法により製造したプリン
ト配線板について、導体パターンの形成に要した時間を
第3表に示した。比較のため、同等のプリント配線板を
、従来のアディティブ法で製造した場合を同時に示す。Regarding the implementation results; Table 3 shows the time required to form conductor patterns for printed wiring boards manufactured by the methods described in Examples 1 to 5 above. For comparison, an equivalent printed wiring board manufactured using the conventional additive method is also shown.
また、実施例1〜5で得られたプリント配線板のパター
ン精度(パターン幅の設計値からのずれ)は、±3μm
程度であり、アディティブ法と同等のパターン精度が得
られた。ちなみにサブトラクティブ法のパターン精度は
、±(20〜40)μm、従来技術(1〉あるいは(2
)に示される方法では、±(10〜20)μmであり、
上記各実施例の工程で得られるプリント配線板は、従来
技術に比べると、パターン精度に優れていることが判っ
た。 なお、各実施例とも、プリント配線板1m2あた
りの製造コストを、従来のアディティブ法に比べると、
10〜15%程度低減させることができた。Furthermore, the pattern accuracy (deviation of pattern width from the design value) of the printed wiring boards obtained in Examples 1 to 5 was ±3 μm.
The pattern accuracy was about the same as that of the additive method. By the way, the pattern accuracy of the subtractive method is ±(20 to 40) μm, compared to the conventional technology (1> or (2)
), it is ±(10-20) μm,
It was found that the printed wiring boards obtained through the steps of each of the above-mentioned Examples had superior pattern accuracy compared to the conventional technology. In addition, in each example, the manufacturing cost per 1 m2 of printed wiring board is compared to the conventional additive method.
It was possible to reduce the amount by about 10 to 15%.
以上説明したように本発明は、高密度の配線板を高い信
頼性の下に簡易に製造することができ、かつ高いパター
ン精度のものを低コストで製造するのに有効である。As explained above, the present invention enables high-density wiring boards to be easily manufactured with high reliability, and is effective in manufacturing high-pattern-accuracy boards at low cost.
第1図(a)〜(f)は゛、実施例1における製造工程
の説明図、
第2図(a)〜(f)は、実施例2における製造工程の
説明図、
第3図(a)〜(f)は、実施例3における製造工程の
説明図、
第4図(a)〜(g)は、実施例4における製造工程の
説明図、
第5図(a)〜(h)は、実施例5における製造工程の
説明図である。
1・・・基板、 2・・・接着材層、 2′・・・粗化
面、3・・・めっきレジスト、
4・・・無電解めっき導体パターン、
5・・・リード線、
6・・・電解めっき用リード、
7・・・電流入力用端子、
8・・・導体パターン、
9・・・電解めっき用パッド、
0・・・スルーホール用貫通孔
1・・・スルーホール、
2・・・エツチングレジスト、
3・・・ニッケルめっき膜、
4・・・金めつき膜。Figures 1 (a) to (f) are explanatory diagrams of the manufacturing process in Example 1. Figures 2 (a) to (f) are explanatory diagrams of the manufacturing process in Example 2. Figure 3 (a) - (f) are explanatory diagrams of the manufacturing process in Example 3, Figures 4 (a) to (g) are explanatory diagrams of the manufacturing process in Example 4, and Figures 5 (a) to (h) are FIG. 6 is an explanatory diagram of the manufacturing process in Example 5. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Adhesive layer, 2'... Roughened surface, 3... Plating resist, 4... Electroless plated conductor pattern, 5... Lead wire, 6...・Lead for electrolytic plating, 7...Terminal for current input, 8...Conductor pattern, 9...Pad for electrolytic plating, 0...Through hole for through hole 1...Through hole, 2... - Etching resist, 3...nickel plating film, 4...gold plating film.
Claims (4)
、ついでめっきレジストを形成し、その後、無電解めっ
きを施すことにより、導体パターンの一部を形造ると同
時に、電解めっき用リードを形成する工程、 (b)前記(a)工程での無電解めっきにより得られた
リードを介して電解めっきを行うことにより、既に形成
した薄肉の前記導体パターンを肥厚化させて所定厚の導
体パターンとする工程、(c)前記電解めっき用リード
と(b)工程で形成した導体パターンとを絶縁する工程
、 の各工程を経ることを特徴とするプリント配線板の製造
方法。1. When manufacturing printed wiring boards, (a) first form an adhesive layer for electroless plating on the board, then form a plating resist, and then apply electroless plating to partially remove the conductor pattern. a step of forming leads for electrolytic plating at the same time as the shaping; (b) performing electrolytic plating via the leads obtained by electroless plating in step (a), thereby forming the already formed thin conductor pattern; (c) insulating the electrolytic plating lead from the conductor pattern formed in step (b). Method of manufacturing the board.
される薄肉の導体パターンの一部と電解めっき用リード
とは、それぞれ2μm以上の厚さにすることを特徴とす
る請求項1に記載の製造方法。2. The manufacturing method according to claim 1, wherein in the step (a), the part of the thin conductor pattern formed by electroless plating and the electrolytic plating lead each have a thickness of 2 μm or more. .
成された金属層および/または基板内に形成されたパッ
ドである請求項1あるいは2に記載の製造方法。3. 3. The manufacturing method according to claim 1, wherein the electrolytic plating lead is a metal layer formed along the outer periphery of the substrate and/or a pad formed within the substrate.
溶性である予め硬化処理された耐熱性樹脂微粉末を、硬
化処理することにより酸化剤に対して難溶性となる耐熱
性樹脂中に分散させたものを硬化処理した後、酸化剤で
処理することにより形成される請求項1〜3のいずれか
1つに記載の製造方法。4. The adhesive layer for electroless plating is made by dispersing heat-resistant resin fine powder, which has been cured in advance and is soluble in oxidizing agents, into a heat-resistant resin that becomes poorly soluble in oxidizing agents through curing treatment. The manufacturing method according to any one of claims 1 to 3, wherein the material is hardened and then treated with an oxidizing agent.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1216002A JP2842631B2 (en) | 1989-08-24 | 1989-08-24 | Manufacturing method of printed wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1216002A JP2842631B2 (en) | 1989-08-24 | 1989-08-24 | Manufacturing method of printed wiring board |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP28665597A Division JP2919817B2 (en) | 1997-10-20 | 1997-10-20 | Manufacturing method of printed wiring board |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0380592A true JPH0380592A (en) | 1991-04-05 |
JP2842631B2 JP2842631B2 (en) | 1999-01-06 |
Family
ID=16681769
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1216002A Expired - Lifetime JP2842631B2 (en) | 1989-08-24 | 1989-08-24 | Manufacturing method of printed wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2842631B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001358257A (en) * | 2000-06-16 | 2001-12-26 | Toppan Printing Co Ltd | Method for manufacturing substrate for semiconductor device |
US7594320B2 (en) | 1997-01-10 | 2009-09-29 | Ibiden Co., Ltd. | Method of manufacturing printed wiring board |
US9595404B2 (en) | 2013-07-19 | 2017-03-14 | General Electric Company | Electrical switching apparatus including an adjustable damper assembly |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5596682U (en) * | 1978-12-26 | 1980-07-04 | ||
JPS5694690A (en) * | 1979-12-27 | 1981-07-31 | Asahi Chemical Ind | Method of manufacturing thick film fine pattern |
JPS5715489A (en) * | 1980-06-30 | 1982-01-26 | Matsushita Electric Works Ltd | Method of forming electric path for printed board |
JPS61276875A (en) * | 1985-06-03 | 1986-12-06 | Ibiden Co Ltd | Adhesive for electroless plating and production of wiring board using said adhesive |
JPS62196891A (en) * | 1986-02-24 | 1987-08-31 | 三菱電機株式会社 | Manufacture of printed wiring board |
-
1989
- 1989-08-24 JP JP1216002A patent/JP2842631B2/en not_active Expired - Lifetime
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5596682U (en) * | 1978-12-26 | 1980-07-04 | ||
JPS5694690A (en) * | 1979-12-27 | 1981-07-31 | Asahi Chemical Ind | Method of manufacturing thick film fine pattern |
JPS5715489A (en) * | 1980-06-30 | 1982-01-26 | Matsushita Electric Works Ltd | Method of forming electric path for printed board |
JPS61276875A (en) * | 1985-06-03 | 1986-12-06 | Ibiden Co Ltd | Adhesive for electroless plating and production of wiring board using said adhesive |
JPS62196891A (en) * | 1986-02-24 | 1987-08-31 | 三菱電機株式会社 | Manufacture of printed wiring board |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7594320B2 (en) | 1997-01-10 | 2009-09-29 | Ibiden Co., Ltd. | Method of manufacturing printed wiring board |
US7765692B2 (en) | 1997-01-10 | 2010-08-03 | Ibiden Co., Ltd. | Method of manufacturing printed wiring board |
JP2001358257A (en) * | 2000-06-16 | 2001-12-26 | Toppan Printing Co Ltd | Method for manufacturing substrate for semiconductor device |
US9595404B2 (en) | 2013-07-19 | 2017-03-14 | General Electric Company | Electrical switching apparatus including an adjustable damper assembly |
Also Published As
Publication number | Publication date |
---|---|
JP2842631B2 (en) | 1999-01-06 |
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