JPH0380293A - Display device - Google Patents

Abstract

PURPOSE:To select video data corresponding to the number of the display lines of a display means by providing a horizontal direction address data generation means and a reduction vertical direction address data generation means. CONSTITUTION:A control part 3 converts an input signal into digital data and gives it to a display part 4 so as to perform the thinning of an inputted video signal corresponding to the number of the display lines in a horizontal direction of the display part 4. In such a case, a horizontal synchronizing signal HS is given to a horizontal address generation circuit 7 being the horizontal direction address data generation means and a horizontal signal thinning circuit 8 and a vertical synchronizing signal VS is given to a vertical address generation circuit 9 and a storage part 10 being a storage means. Then, the reduction vertical direction address data generation means is constituted of the horizontal signal thinning circuit 8 and the vertical address generation circuit 9. Thus, the video data is selected and displayed corresponding to the number of the display lines of the display part 4.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a display device configured by a plurality of lamps arranged in a matrix.

Prior Art FIG. 6 is a block diagram showing the basic configuration of a conventional display device. This display device has a display section 36 configured by arranging lamps 39 in a matrix, receives a video signal from a video camera, video tape recorder, etc. as an input signal, and uses this input signal to display each display on the display section 36. The video signal is converted into digital data corresponding to three lamps, which are pixels, and displayed on the display section 36.

The video signal is converted into a red signal R by the video signal processing device 37.
a, a green signal Ga, a blue signal Ba (generally referred to as a color signal), a horizontal synchronizing signal H1, and a vertical synchronizing signal V. The color signal is given to an A/D conversion circuit (analog/digital conversion circuit) 31, the horizontal synchronization signal H is given to a horizontal address creation circuit 32 and a vertical address creation circuit 33, and the vertical synchronization signal V is given to a vertical address creation circuit. Given to 33. The A/D conversion circuit 31 converts each color signal into digital data in response to a clock signal from the horizontal address generation circuit 32, and provides the digital data to the storage section 35. The horizontal address generation circuit 32 counts clock signals from an internal clock generation circuit using a counter, and provides the counted value to the storage section 35 as a horizontal address. This counter is reset by vertical synchronization signal H.

The vertical address generation circuit 33 counts the horizontal synchronization signal H with a counter, and stores the counted value in the storage unit 3 as a vertical address.
Give to 5. This counter is reset by the vertical synchronization signal V.

The storage unit 5 stores A at the address specified by the horizontal address generation circuit 32 and the vertical address generation circuit 33.
Stores digital data from the /D conversion circuit 31. The digital data stored in the storage section 35 is read out based on address data from the read address generation circuit 34 and displayed on the display section 36.

Currently, in Japan, the NTSC system is adopted as a TV (Te1evision) signal, and the NTSC system performs interlacing. In addition, IDTV method (
As an intermediate between HDTV and NTSC, I perform motion compensation to fill in data between interlaces.
A DTV system has been developed, and the IDTV system is non-interlaced. The IDTV system is a system that improves the image quality mainly on the receiver side without changing the NTSC TV signal. For example, using frame memory, etc., to reliably separate luminance signals and color signals,
Converting interlaced scanning to progressive scanning improves the apparent vertical resolution. However, the horizontal resolution does not improve.
Furthermore, in addition to display units in which the number of horizontal lines constituting the display screen is the same as the number of horizontal scanning lines of the TV signal, there are also small display units in which the number of horizontal lines constituting the display screen is only half the number of horizontal lines.

Problems to be Solved by the Invention As mentioned above, when the number of horizontal lines of the display section 35 is different from the number of horizontal scanning lines of the input video signal, conventionally, before inputting the video signal to the display section 36, the video signal is It was necessary to input the signal after converting it into a signal adapted to the size of the display section 36 by the video signal processing device 37.

The video signal processing device 37 has a memory 38 inside, and is a device that uses this memory 38 to perform data calculations and enlarge/reduce the video signal, but it is very expensive. There is a problem that the display device also becomes expensive.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and provide a display device capable of reducing a video signal, that is, selecting video data according to the number of display lines of a display means.

Means for Solving the Problems The present invention provides a display means for displaying video data based on a video signal, and a capacity corresponding to a number of horizontal scanning lines that is smaller than the number of horizontal scanning lines within a vertical scanning period that defines the video signal. a storage means in which the video data is stored; a horizontal address data creation means for creating horizontal address data of the storage means based on a horizontal synchronization signal that defines the video signal; and reduced vertical address data creation means for creating vertical address data of the storage means corresponding to a number of horizontal scanning lines smaller than the number of horizontal scanning lines within the vertical scanning period. .

According to the present invention, video data based on a video signal is stored in the storage means, and the video data stored in the storage means is displayed on the display means. When the video data is stored in the storage means, it is stored at an address specified by the horizontal address data and vertical address data created by the horizontal address data creation means and the reduced vertical address data creation means, respectively.

The horizontal direction address data creation means creates horizontal direction address data of the storage means based on the horizontal synchronization signal that defines the video signal. Further, the reduced vertical address data creating means creates vertical address data of the storage means corresponding to the number of horizontal scanning lines smaller than the number of horizontal scanning lines within the vertical scanning period, based on the horizontal synchronization signal.

Therefore, the video data is stored in the storage means by reducing the number of horizontal scanning lines of the video signal. This allows video data to be selected and displayed according to the number of display lines of the display means.

Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing the basic configuration of a display device in which the present invention is implemented. Referring to FIGS. 1 and 2, the display device includes a control section 3 and a display section 4 serving as display means, and includes a video camera 1, a video tape recorder 2, etc.
video signal from
The 0 display unit 4, which receives an input signal such as an on) signal, is configured by a plurality of lamps 5, which are display pixels, arranged in a matrix. For example, red lamps and green lamps are alternately arranged in the first horizontal column, and green lamps and blue lamps are alternately arranged in the second column. Hereinafter, odd-numbered columns have the same configuration as the first column, and even-numbered columns have the same configuration as the second column.

The control section 3 converts the input signal into digital data corresponding to the lamp 5 and supplies it to the display section 4 . At this time, the control section 3 thins out the input video signal according to the number of display lines in the horizontal direction of the display section 4. Such display devices are installed, for example, at baseball stadiums, and display replays and the like.

A video signal from the video camera 1 or the video tape recorder 2 is processed by a separation circuit (not shown) in the control unit 3 to receive an RGB signal C1 horizontal synchronization signal H3 and a vertical synchronization signal
Separated into S. RGB signal signal hole Red signal R1 Green signal G and blue signal B''C'C' configuration, RGB signal signal hole/D conversion circuit 6 is given, horizontal synchronization signal H9 is horizontal address creation means which is horizontal direction address data creation means The vertical synchronizing signal VS is applied to the vertical address generation circuit 9 and the storage unit 10 which is a storage means.The reduced vertical address data generation means is applied to the horizontal signal thinning circuit 8 and the vertical It is composed of an address generation circuit 9.

The A/D conversion circuit 6 converts each of the RGB signal holes A/D based on the clock signal CK from the horizontal address generation circuit 7.
D conversion is performed and the digital data is provided to the storage unit 10. The storage unit 10 responds to the address data from the horizontal address generation circuit 7 and the vertical address generation circuit 9, and stores the digital data from the A/D conversion circuit 6 at a designated address.

Further, the storage section 10 provides digital data to the display section 4 in response to address data from the read address generation circuit 11. The 0 display section 4 performs display based on the data from the storage section 10.

FIG. 3 is a block diagram showing the configuration of the control section 3.
The figure is a timing chart showing the operation of the control section 3.

The vertical synchronizing signal VS is shown in FIG. 4 (1), and the horizontal synchronizing signal H9
are shown in FIG. 4 (4>). The period from the low level of the vertical synchronizing signal vS to the low level is the display period for one screen, that is, the vertical scanning period, and the period from the low level of the horizontal synchronizing signal HS to the low level is the display period for one screen, that is, the vertical scanning period. The period until the low level is a display period for one horizontal line, that is, a horizontal scanning period.

The A/D conversion circuit 6 includes an A/D conversion circuit 12R912G,
12B and a selector S1.

For example, the red signal R is shown in FIG. 4 (9),
The red signal R is given to the A/D conversion circuit 12R. Further, the green signal G and the blue signal B are provided to A/D conversion circuits 12G and 12B, respectively.

The A/D conversion circuits 12R, 12G, and 12B convert the red signal R1, green signal G, and blue signal B into digital data DR, DG, and DB, respectively, in response to the clock signal CK from the clock generation circuit 14.

Data is given to memories M1 and M2 via DR, DG and DB selector S1.

The selector S1 selects and outputs only one type of input data DR, DG, and DB in response to a clock signal representing the least significant bit output from counters 13 and 15, which will be described later. . As mentioned above, the odd-numbered columns of the display section 4 are composed of red lamps and green lamps, so when the RGB signal signal hole of the odd-numbered horizontal scanning period is input, it responds to the signal from the counter 13. The data DR and DG are output alternately. Furthermore, since the even-numbered columns are composed of red lamps and blue lamps, when the RGB signal C of the even-numbered horizontal scanning period is input, the data DG, D
B is output alternately. Further, switching of the operation for each horizontal scanning period is performed in response to a signal from the counter 15.

The write operation and read operation of the memories M1 and M2 are switched by a vertical synchronizing signal VS. In other words, the vertical synchronizing signal VS is input to the CLKI of the flip-flop 19, and therefore the signal shown in FIG. 4 (2).

(As shown in 3>, the signal level of the Q1 output of the flip-flop 19 is inverted every time the vertical synchronization signal VS is input. The Q1 output of the flip-flop 19 is given to the selectors S4 and S5, and the inverter circuit 18 to selectors S2 and S3.

Selector S3. For example, when a high level signal is input, S5 supplies the address data from the counters 13 and 15 to the memories M1 and M2, and when a low level signal is input, the address data from the counter 16 is supplied to the memories M1 and M2. Give to M2. For example, when a high level signal is input, the selectors 82 and 94 select A.
The digital data from the /D conversion circuits 12R, 12G, and 12B is applied to the memories Ml and M2, and when a low level signal is input, the data in the memories Ml and M2 is displayed on the display section 4.
Output to.

Therefore, for example, when the Q1 output is at a high level, data is written into the memory M2, and at this time, data is read from the memory M1 and displayed on the display section 4. Further, when the Q1 output is at a low level, data is written into the memory M1, and at this time, data is read from the memory M2 and displayed on the display section 4. Such write operation and read operation are switched for each screen, that is, each time the vertical synchronization signal vS is input.

The horizontal address generation circuit 7 includes a counter 13 and a clock generation circuit 14. The counter 13 performs a counting operation based on the clock signal CK from the clock generation circuit 14, and is reset by the horizontal synchronization signal H3. The count value, which is the output of the counter 13, is horizontal address data, and selector S3. given to S5.

The vertical address generation circuit 9 is composed of a counter 15. The counter 15 performs a counting operation using the output signal from the horizontal signal thinning circuit 8 as a clock signal, and is reset by the vertical synchronizing signal VS. The count value that is the output of the counter 15 is vertical address data, and the selector 8
3. given to S5.

The horizontal signal thinning circuit 8 is composed of a dip switch DSW and a flip-flop 20.

When the switch X1 of the dip switch DSW is turned on, the horizontal synchronizing signal H3 is directly applied to the counter 15, so the counter 15 increments by 1 each time the horizontal synchronizing signal H8 is input, as shown in Figure 4 (5>). It is counted up and the counted value is given to the selector 83, S5.Therefore, the data of all the horizontal lines constituting one screen are stored in the memory M1.

Written to M2.

When switch X2 of dip switch DSW is turned on,
Horizontal synchronization signal H8 is applied to flip-flop 20. As a result, the Q2 output of the flip-flop 20 becomes a signal whose signal level is inverted every time the horizontal synchronizing signal H3 is input, as shown in FIG. 4 (6) and (7). In other words, a signal having a period twice as long as the horizontal scanning period becomes the clock signal of the counter 15. Therefore, Fig. 4 (
8), the counter 15 receives the horizontal synchronizing signal HS.
When is input twice, the count is increased by l. The count value which is the output of the counter 15 is output from the selector S3. given to S5. As a result, in the area where the data of the odd-numbered horizontal line was written, the data of the even-numbered horizontal line following that odd-numbered horizontal line will be written, and the data of the odd-numbered horizontal line will be written. The data will be erased, and only the data of even-numbered horizontal lines will be stored in the memories M1 and M2.

The read address creation date Fn111 is composed of a counter 16 and a clock generation circuit 17. The counter 16 counts the clock signal of the clock generation circuit 17 and is reset by the vertical synchronization signal vS.

The count value, which is the output of the counter 16, is determined by the selectors S3 and S.
given to 5. This causes memory Ml.

Video data is sequentially read out from M2 and displayed on the display section 4. The counter 16 is the counter 13 described above.
．． If 15 are each, for example, an 8-bit counter, then it is a 16-bit counter.

As described above, according to this embodiment, the horizontal signal thinning circuit 8
By using the image data forming one screen, the image data constituting one screen is stored in the memory Ml every other horizontal line.

It is stored in M2. Therefore, the size of the display screen of the display section 4 is 1/4, that is, the number of horizontal lines of the display section 4 is 1/4.
/2, the input video signal is easily displayed on the display unit 4.
can be displayed.

Furthermore, when the number of lamps 5 constituting one horizontal line increases or decreases, the frequency of the clock generation circuit 14 may be changed in accordance with the number of lamps 5.

FIG. 5 is a block diagram of another embodiment of the present invention. This embodiment is similar to the previously described embodiments, so corresponding components are given the same reference numerals. A feature of this embodiment is that a preset counter 21 is used as the horizontal signal thinning circuit 8.

The preset counter 21 is, for example, a 4-bit counter, and is set to, for example, "1101" as an initial value using the date switch 22. When the horizontal synchronizing signal HS is input once, the “110
1” is read into the preset counter 21. Thereafter, when the horizontal synchronizing signal HS is input twice, the count value of the preset counter 21 becomes "1111", and a pulse is output from the CY output. This pulse is used as a clock signal for the counter 15. Furthermore, the CY output is output from counter 15.
is input to the LD input as a read permission signal for the initial value of
Next, when the horizontal synchronizing signal H8 is input, the counter 15 again performs the counting operation starting from "1101".

Therefore, when the horizontal synchronizing signal H8 is input three times to the counter 15, the count value is incremented by 1, so that data is stored in the memories M1 and M2 every two horizontal lines. As a result, the display screen size of the display unit 4 is reduced to 1/
It becomes 9. Furthermore, by changing the initial value of the preset counter 21, it can be made to correspond to any display screen size.

Effects of the Invention As described above, according to the present invention, since video data is selected and displayed according to the number of horizontal lines of the display means, the size of the display screen of the display means can be easily changed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing the basic configuration of a display device in which the present invention is implemented, and FIG. 3 is a block diagram showing the specific configuration of the control unit 3. 4 is a timing chart showing the operation of the control unit 3 shown in FIG. 3, FIG. 5 is a block diagram showing another embodiment of the present invention, and FIG. 6 is a block diagram showing the configuration of a conventional display device. It is. 3... Control unit, 4... Display unit, 7... Horizontal address generation circuit, 8... Horizontal signal thinning circuit, 9... Vertical address generation circuit, 10... Storage unit, 11.・Read address creation circuit

Claims (1)

[Scope of Claims] Display means for displaying video data based on a video signal, having a capacity corresponding to a number of horizontal scanning lines smaller than the number of horizontal scanning lines within a vertical scanning period defining the video signal, and displaying means for displaying video data based on a video signal; storage means for storing data; horizontal address data creation means for creating horizontal address data of the storage means based on a horizontal synchronization signal that defines the video signal; A display device comprising reduced vertical address data creating means for creating vertical address data of a storage means corresponding to a number of horizontal scanning lines smaller than the number of horizontal scanning lines within a period.