JPH08297481A - Graphic image display device - Google Patents

Abstract

PURPOSE: To clearly display the color of an arbitrarily formed frame which partitions the parent screen from the child screen by writing a mixture of image voltage and graphic data into image memory. CONSTITUTION: The data which composes the graphic pattern generated by the CPU 5-3 is written into an image memory 1-8 after a switch 5-2 is turned to the side of the CPU 5-3 during the blanking periods, etc., of child screen image signals. Next, after the switch 5-2 is turned to a clipper 5-1 side, the child screen information data is written into the memory 1-8 by the effect of a writing control circuit 1-11. And, a comparison circuit 5-4 turns switches, 1-16 to 1-18, to the side of resistors, 1-13 to 1-15, to select the frame data when coincidence between the readout data from the memory 1-8 and '1' is detected and to convert the output signals into analog signals. When the coincidence between the output data of the memory 1-8 and '0' is detected, switches, 1-20 to 1-22, are switched to the signals from the parent screen decoder 1-2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit suitable for storing an image in an image memory and displaying it on a screen to display a graphic pattern such as when a frame is superimposed on the image.

[0002]

2. Description of the Related Art FIG. 5 shows a main part of a conventional parent-child screen television receiver. This television receiver has a function of receiving different broadcasts at the same time by two tuners and superimposing a small screen on a main screen with one CRT. The conventional parent-child screen television receiver of FIG. 5 includes tuners 1-1, 1-3, a parent screen decoder 1-2, a child screen decoder 1-4, and an analog / digital converter (hereinafter abbreviated as ADC). Yes) 1-
5, 1-6, 1-7 and image memories 1-8, 1-9, 1
-10, write control circuit 1-11, read control circuit 1-12, palette register 1-13, 1-1
4, 1-15 and switches 1-16, 1-17, 1-1
8, frame generation circuit 1-19, switches 1-20, 1-
21, 1-22, matrix 1-23, R output terminal 1-24, G output terminal 1-25, and B output terminal 1-2.
6 and a digital / analog converter (hereinafter abbreviated as DAC) 1-27, 1-28, and 1-29.

The broadcast received by the tuner 1-1 is decoded by the master screen decoder 1-2 into the master screen Y, RY and BY video signals. The broadcast received by the tuner 1-3 is sub-screen Y, RY by the sub-screen decoder 1-4.
(U), BY (V) video signals are decoded. The sub-screen video signal is digitized by the ADCs 1-5, 1-6, 1-7, and based on the timing signal generated by the write control circuit 1-11, the image memories 1-8, 1-9, 1-1.
Written to zero. Whether the entire small screen is displayed in a reduced size or a part of the small screen is cut and displayed is controlled by the timing control by the write control circuit 1-11.

When writing the sub-picture video signal to the image memory, in order to save the image memory capacity, the R signal for the Y signal is saved.
The -Y and BY signals are written by thinning out the number of pixels. For example, if memory is thinned out to 4 to 1, and considering writing Y into 4 pixels, Y, RY, Y
It is necessary to write 4 pixels for BY, that is, 12 pixels in total, but when thinning out, a total of 6 pixels of Y4 pixels, 1 pixel for each of RY and BY, may be written, and the image memory capacity should be halved. You can On the other hand, the read control circuit 1-
Reference numeral 12 denotes an image memory 1-based on the sync signal of the main screen.
Read 8, 1-9, 1-10.

The frame generation circuit 1-19 is a timing signal wsw indicating at which position on the parent screen the child screen signal is fitted.
And ys, and wsw is a switch 1-16, 1-
17, 1-18, and ys is a switch 1-20, 1-
21 and 1-22 are switched. Switches 1-16, 1-
By switching between 17 and 1-18, a frame image which is a graphic pattern is added around the small screen signal. Then, it is converted into an analog signal by the DAC 1-27, 1-28, 1-29, and the switch 1-20, 1-21, 1-.
By switching 22, the child screen is fitted into the parent screen. The embedded video signal is sent to the matrix circuit 1-24.
Is converted into an RGB signal and sent to a CRT (not shown) to display an image. The added frame signal is a palette register 1-13, 1-14, 1 holding the value of the frame.
It is determined by the value set to −15, and the color corresponding to this value becomes the frame color.

FIG. 6 shows an example of the configuration of the frame signal generating circuit. Dot clock and horizontal of main screen from terminal 2-1
A vertical sync signal is input. The horizontal counter 2-2 counts the dot clock and is reset at the horizontal synchronization timing. The vertical counter 2-3 counts horizontal synchronizing timing pulses and is reset by a vertical synchronizing signal.

FIG. 7 shows a conventional display example of a parent-child screen. Registers 2-4, 2-5, 2-6, 2-7 of FIG.
In FIG. 7, the values corresponding to the locations of the timings a, b, c, d in FIG.
3, 2-14 and 2-15 compare the value of these registers with the value of the horizontal counter 2-2.

Registers 2-8, 2-9, 2-10, 2
In -11, the values corresponding to the locations of the timings e, f, g, and h in FIG. 7 are stored, and the comparators 2-16, 2-17,
2-18 and 2-19 compare the value of these registers with the value of the vertical counter 2-3. The results of these comparisons are the inverters 2-20 to 2-23, 2-28, 2-
30 and AND gates 2-24 to 2-27, 2-29,
By passing through the gate logic composed of 2-31 to 2-33, the timing signal wsw corresponding to the frame portion in FIG. 7 is shown at the terminal 2-35 and whether it is inside or outside the outer circumference of the frame. The timing signal Ys is obtained at the terminal 2-34.

In the above conventional parent-child screen television receiver, the image signals read from the image memories 1-8, 1-9 and 1-10 are thinned out from the RY and BY signals. The resolution is low. However, since the signals from the frame generator circuit 1-19 are switched at the same time, the color resolution of the frame image is higher than that of the image stored in the image memory and looks clear.

[0010]

However, when the frame signal is added in the subsequent stage of the image memory, it is possible to display a frame image having a high resolution regardless of the resolution of the color signal written in the image memory. However, on the other hand, the shape of the frame is determined by the shape that can be generated by the frame signal generation circuit, and for example, the configuration of FIG. 6 can only realize a simple square.

Further, in the case of displaying a complicated shape as shown in FIG. 4, it can be realized by writing a desired image in the image memory, but color signals are thinned out and stored in the image memory. Therefore, there is a problem that a clear frame cannot be added.

In view of the above problems, it is an object of the present invention to generate a frame having an arbitrary shape that separates a main screen and a child screen and display the color of the frame clearly.

[0013]

In order to achieve the above object, the present invention has the following constitution. That is, according to the first aspect of the invention, the first input terminal for inputting the first image data composed of the luminance signal and the color signal, the image memory, and the image memory are inputted from the first input terminal. Image data writing means for writing image data and graphic data writing means for writing graphic data having a predetermined luminance value forming a graphic pattern in the image memory are provided, and the image data and the graphic data are stored in the image memory. It is a graphic image display device characterized by writing mixedly.

According to a second aspect of the present invention, a read control means for controlling the reading of the image memory, a data comparison circuit for comparing the read image data with the predetermined brightness value, and a second input. It further comprises a data terminal, and a data selector for switching and outputting the output of the image memory and the data given to the second data terminal based on the comparison result by the data comparison circuit. The graphic image display device according to item 1.

The invention according to claim 3 is further provided with a palette register, and the second input data terminal receives an output of the palette register. .

The invention according to claim 4 is the graphic image display device according to claim 2, wherein the second image data is input to the second input data terminal.

The invention according to claim 5 further comprises a limiting circuit for limiting the image data input from the first input terminal to a value other than the predetermined value. Item 5. The graphic image display device according to any one of Items 4.

According to a sixth aspect of the present invention, the graphic data writing means is a means for reading the image memory, and when the value read from the image memory indicates the predetermined value, other than the value. 6. The graphic image display device according to claim 1, further comprising means for rewriting a value.

The invention according to claim 7 is characterized in that the predetermined value is an upper limit value or a lower limit value of the data representation in the image memory.
The graphic image display device according to any one of 1.

The invention according to claim 8 comprises a plurality of the palette registers, a plurality of the comparators, and a plurality of the data selector circuits, wherein a plurality of the predetermined values are set and the plurality of the plurality of predetermined values are set. Each of the comparators compares the predetermined value with the image memory read data, and the data selector selects either the image data read value or the palette register based on the comparison result. The graphic image display device according to claim 3.

According to a ninth aspect of the present invention, a third data input terminal and a plurality of the comparators are provided, and the data from the second data input terminal and the third data input terminal are provided. And the data from the image memory are input to the data selector circuit, the plurality of predetermined values are set, and each of the plurality of comparators compares each predetermined value with the image memory read data. , The data selector circuit selects any one of the data from the second data input terminal, the data from the third data input terminal, and the data from the image memory based on the comparison result. The graphic image display apparatus according to claim 3, wherein the graphic image display apparatus outputs the graphic image.

The invention according to claim 10 further comprises an area mask circuit for generating a mask signal for masking a specific region of the display screen, and in accordance with the mask signal,
The graphic image display device according to any one of claims 2 to 9, wherein the data selector is controlled.

The invention according to claim 11 is characterized in that the graphic data writing means writes in the image memory during a vertical blanking period of a video signal. It is the described graphic image display device.

The invention according to claim 12 is characterized in that the image data writing means writes the image data in the image memory after the graphic data writing means writes. Item 12. The graphic image display device according to any one of Items 11.

[0025]

The gist of the present invention is to eliminate two gradations from the sub-picture image signal from the peak level of white or black, which rarely appears as a normal image signal, and to use the two-gradation signals for the parent-child picture and the graphic. It is used for pattern control.

That is, while the image data of the small screen is written in the image memory by the image data writing means, two gradations from the white or black peak level are set as a predetermined value, and an arbitrary graphic pattern having this predetermined value is written in the graphic writing means. To write to the image memory. In this way, the image memory in which the image data and the graphic pattern of the predetermined value are mixed and written is read out according to the synchronization signal, and if the first predetermined value or the second predetermined value is satisfied, the image signal of the parent screen or the frame is read. Output, otherwise
The image signal of the small screen read from the image memory is output.

In this way, by switching Y, RY, and BY of the video signal at the output of the image memory, they can be switched at the same switching time. Therefore, an image with a frame of arbitrary shape with clear edges can be obtained.

[0028]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a first embodiment of a graphic image display device according to the present invention. FIG. 3 shows an example of a display according to the same embodiment.

In FIG. 1, the graphic image display device of the embodiment has tuners 1-1 and 1-3, a parent screen decoder 1-2, a child screen decoder 1-4, and ADCs 1-5.
1-6, 1-7 and image memories 1-8, 1-9, 1-1
0, write control circuit 1-11, read control circuit 1-12, palette registers 1-13, 1-14, 1
-15 and switches 1-16, 1-17, 1-18,
Switches 1-20, 1-21, 1-22, matrix 1-23, R output terminal 1-24, and G output terminal 1-2.
5, B output terminal 1-26, DAC 1-27, 1-2
8, 1-29, clipper 5-1 and switch 5-2
And a CPU 5-3 and comparators 5-4 and 5-5. The same components as those in the conventional example shown in FIG. 5 are designated by the same reference numerals.

The image memories 1-8, 1-9, 1-10 are
It is a memory that stores a Y signal, a U (RY) signal, and a V (BY) signal, respectively. The image memory 1-8 has a storage area for one frame, but the image memories 1-9 and 1-10
In the same manner as the conventional example, the storage area is compressed to 1/4.
The gradation of image brightness is expressed by 8 bits, and the image memory 1-
Each of the eight storage addresses can store 8-bit data.

The analog Y signal output from the child screen decoder 1-4 is converted into an 8-bit digital Y signal by the ADC 1-5, and the clipper 5-1 limits the amplitude of the data from "2" to "255". It The lower value of the luminance signal limits the expressiveness of the black image data, but the distribution of the normal signal is likely to be concentrated around "128", so the image quality is high. Is unlikely to be a problem.

In writing to the image memory 1-8, first, the switch 5-2 is turned to the CPU 5-3 side during the blanking period of the sub-picture video signal, and the data forming the graphic pattern generated by the CPU 5-3 is stored. Image memory 1
Write to -8. That is, the data “0” is written in the area of the memory 1-8 corresponding to the area 3-3, and
Data "1" is written in the area of the memory 1-8 corresponding to the area 3-1. At this time, the area in which the data “1” is written may be written in both 3-1 and 3-4. This is because the image data will be overwritten later.

The timing at which the CPU 5-3 writes the data to the memory 1-8 may be any time as long as the sub-picture image signal is not taken in, but the CPU 5-3 enables the writing operation in a coherent time. In order to do so, it is preferable to carry out during the V blanking period.

Then, the switch 5-2 is moved to the clipper 5-.
The sub screen image data is written to the memory 1-8 by the writing control circuit 1-11. As a result, the memory 1-8 stores "0" as the data of the area for displaying the main screen and "1" as the data for displaying the frame signal.
As the data for displaying the sub-screen video data, the values of “2” to “255” are held therein. Memory 1-
Color signals are stored in 9, 1-10 as usual. When writing the sub-screen image data, as in the prior art,
The image size of the inset screen may be compressed and written, or a part of the inset image may be cut and written.

The comparator circuit 5-4 compares the read data from the memory 1-8 with "1", and when a match is detected, switches 1-16, 1-17, 1-18 are connected to the register 1-.
13, 1-14, 1-15 and select frame data. The output signals of the switches are DAC 1-27, 1-28,
Converted to an analog signal at 1-29. Comparison circuit 5-5
Compares the output data of the memory 1-8 with "0", and if a match is detected, switches 1-20, 1-21, 1-22
To the signal from the parent screen decoder 1-2. In this way, as shown in FIG.
The frame image is displayed on the screen, and the small screen image signal is displayed on the area 3-4.

According to the application of the present invention, as shown in FIG. 3 (b), each frame of a moving image is displayed while being superimposed,
It is possible to display such that the receiving channels are displayed one by one while changing the channels one by one. The operation will be described by taking as an example the case where each frame of a moving image is displayed while being overlapped.

First, the switch 5-2 is tilted to the CPU 5-3 side, and the data "0" is written in the area corresponding to the area of the CPU 5-3 to 3-5. Next, the data "1" is written in the area corresponding to the area 3-6. Then switch 5-2
To the side of the clipper 5-1 and the sub-screen image is written in the area 3-10. This will display the first frame.

Then, in step 5-2, the CPU5-
The CPU moves it to the 3 side and writes "1" in the area 3-7 of the frame. Then, the switch 5-2 is tilted to the clipper 5-1 side, and the small screen image is written in the area corresponding to the area 3-11. With this, the display of the second frame is performed.

Then, the switch 5-2 is turned on again to the CPU 5-
The CPU moves it to the 3 side and writes "1" in the area 3-8 of the frame. Then, the switch 5-2 is tilted to the clipper 5-1 side, and the small screen image is written in the area corresponding to the area 3-12. With this, the display of the third frame is performed.

Then, the switch 5-2 is turned on again to the CPU 5-
The CPU moves it to the 3 side and writes "1" in the area 3-9 of the frame. Then, the switch 5-2 is tilted to the clipper 5-1 side, and the small screen image is written in the area corresponding to the area 3-13. With this, the display of the fourth frame is performed.

In the above description, the clipper 5-1 functions to limit the data so that the image data does not take the value "0" or "1". However, if the CPU 5-3 has the memory 1-8. If the data in the memory can be read, the CPU can read the data in the memory 1-8 without using the clipper 5-1 to find the data "0" and "1" and call it "2". It can also be realized by using software control of changing to a value.

In the above embodiments, the frame information and the data indicating the switching with the parent image signal are stored in the memory 1-8 for storing the Y signal. Y signal memory 1-
8 has a large amount of data as compared with the color signal memory, and can be set with a finer resolution. On the contrary, the memory 1-8
1-9 or 1-10 can be used instead of. In this case, there is an effect that the frame information can be reduced. In this case, the accuracy of switchable timing is reduced to 1/4, but the switching edge is not blunted and a clear frame signal is added.

In the above description, the sub-picture video signal is A
Since it is assumed that DC1-5 is converted from "0" to "255", it is highly possible that the values of the video data are distributed around "128". Therefore, if the data indicating the frame portion or the portion displaying the parent screen is "0" and "1" or vice versa as described above, it is unlikely that the data range of the video data is limited. The data indicating the frame part and the part displaying the main screen are “254” and “255”.
The same can be said of. If the value converted by the ADC is from -128 to 127, the video data is likely to be distributed around 0, so that the data indicating the frame portion and the portion displaying the main screen is " 0 ",
Since "1", "254", and "255" have a high possibility of overlapping with the image data, "-128" or "127"
It is possible to avoid the influence on the image quality by using the value of.

Next, the configuration of the second embodiment of the graphic image display device according to the present invention is shown in FIG. In the first embodiment of FIG. 1, the child screen image memory 1-8 had to have a capacity of an area covering the entire screen, but in the present embodiment, the child screen and its frame area are included. It suffices to have the capacity of only a part. Therefore, the area mask generation circuit 5-
8 is provided. The area mask circuit 5-8 generates a timing signal corresponding to the area 3-2 in FIG. Then, by ORing the parent screen switching signal generated by the comparator 5-5 and the signal output by the area mask circuit 5-8, if either one gives an instruction to switch to the parent screen, the parent screen is output. To switch. Therefore, memory 1
The capacity of -8 is only the area shown in 3-2, and no matter what data is output outside the area of 3-2, the parent screen is displayed outside 3-2, and the area mask circuit 5-8 The inside of can be realized with the same configuration as the frame signal generating circuit in FIG.

In FIG. 2, the palette register 1-
Two sets of (a) and (b) are prepared for 13, 1-14, and 1-15, respectively. Then, a comparator 5-6 is added. In the clipper 5-1, the video signal is clipped to a value of "3" to "255". Then, as the frame information, the value of "1" or "2" is written in the memory 1-8.
When the comparator 5-6 detects a value of "1", it switches the switches 1-16, 1-17, 1-18 to the register 1-13.
When the values of (a), 1-14 (a), and 1-15 (a) are selected and the value of "2" is detected, the register 1-13
The values of (b), 1-14 (b) and 1-15 (b) are selected.

FIG. 4B shows an example of a display that can be made by using the present invention. In this display example, the image 4-3 is displayed in an arbitrary shape that is not a rectangle.

First, the CPU 5-3 writes data in the memory 1-8 in the form shown in FIG. Area 4 where data “0” is added to the area 4-0 where the main screen is displayed and a frame is added
Write data "1" in -1. After that, switch 5
-2 to the clipper 5-1 side, and store the image in memory 1-8
Write in the area 4-3. This is the write control circuit 1-11 so that the write area is changed line by line.
Is realized by operating. Thus, FIG.
The display as shown in (b) becomes possible.

[0048]

As described above, according to the present invention,
By writing in the image memory an arbitrary graphic pattern configured by a predetermined value generated by the CPU of the microcomputer, it is possible to generate a frame having an arbitrary shape,
Since the switching is performed at the same data rate as the luminance signal, there is an effect that a clear frame can be added.

Further, according to the present invention, a plurality of predetermined values for designating a frame are defined and a plurality of sets of palette registers corresponding to the respective predetermined values are provided, so that a frame of a plurality of colors having an arbitrary shape can be clearly displayed. The effect is that you can

[Brief description of drawings]

FIG. 1 is a first graphic image display device according to the present invention.
It is a block diagram which shows the structure of an Example.

FIG. 2 is a second graphic image display device according to the present invention.
It is a block diagram which shows the structure of an Example.

FIG. 3 is a diagram showing a display example of a screen according to an embodiment of the present invention.

FIG. 4 is a diagram showing a display example of a screen according to an embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional example.

FIG. 6 is a circuit diagram illustrating details of a frame signal generation circuit in a conventional example.

FIG. 7 is a diagram showing a display example according to a conventional example.

[Explanation of symbols]

1-1, 1-3 Tuner 1-2 Main Screen Decoder 1-4 Child Screen Decoder 1-5, 1-6, 1-
7 ADC 1-8, 1-9, 1-10 Image memory 1-11 Write control circuit 1-12 Read control circuit 1-13, 1-14, 1-15 Palette register
1-16, 1-17, 1-18 Switch 1-2
0, 1-21, 1-22 switch 1-23 matrix 1-24 R output 1-25 G output 1
-26 B output 1-27, 1-28, 1-29 DAC 5-1 Clipper 5-2 Switch 5-3 CPU 5
-4, 5-5 Comparison circuit

Claims (12)

[Claims] 1. A first input terminal for inputting first image data composed of a luminance signal and a color signal, an image memory, and an image in which the image data input from the first input terminal is written in the image memory. And a graphic data writing unit for writing graphic data having a predetermined brightness value forming a graphic pattern to the image memory, wherein the image data and the graphic data are written together in the image memory. A graphic image display device characterized by the above. 2. A read control means for controlling reading of the image memory, a data comparison circuit for comparing the read image data with the predetermined brightness value, a second input data terminal, and the data comparison. The graphic image display according to claim 1, further comprising: a data selector that switches and outputs the output of the image memory and the data provided to the second data terminal based on a comparison result by a circuit. apparatus. 3. The graphic image display device according to claim 2, further comprising a palette register, wherein the second input data terminal receives an output of the palette register. 4. The graphic image display device according to claim 2, wherein second image data is input to the second input data terminal. 5. The limiting circuit according to claim 1, further comprising a limiting circuit that limits the image data input from the first input terminal to a value other than the predetermined value. Graphic image display device. 6. The graphic data writing means includes means for reading the image memory, and means for rewriting a value other than the value when the value read from the image memory indicates the predetermined value. The graphic image display device according to any one of claims 1 to 5, further comprising: 7. The graphic image display device according to claim 1, wherein the predetermined value is an upper limit value or a lower limit value of data representation in the image memory. 8. A plurality of the palette registers, a plurality of the comparators, and a plurality of the data selector circuits, wherein a plurality of the predetermined values are set, and each of the plurality of comparators respectively Comparing a predetermined value of the image memory read data, based on the comparison result,
4. The graphic image display device according to claim 3, wherein the data selector selects either the image data read value or the palette register. 9. A third data input terminal and a plurality of the comparators are provided, and data from the second data input terminal, data from the third data input terminal and the image memory are provided. Data of the above are input to the data selector circuit, the plurality of predetermined values are set, and each of the plurality of comparators compares each predetermined value with the image memory read data, and based on the comparison result. The data selector circuit selects and outputs any one of data from the second data input terminal, data from the third data input terminal, and data from the image memory. The graphic image display device according to claim 3. 10. The method according to claim 2, further comprising an area mask circuit for generating a mask signal for masking a specific area of the display screen, wherein the data selector is controlled according to the mask signal. Item 10. The graphic image display device according to any one of items 9. 11. The graphic image display device according to claim 2, wherein the graphic data writing means writes data in the image memory during a vertical blanking period of a video signal. 12. The image data writing means writes the image data in the image memory after the graphic data writing means writes the image data in the image memory. Graphic image display device.