JPH0379050A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0379050A JPH0379050A JP21501689A JP21501689A JPH0379050A JP H0379050 A JPH0379050 A JP H0379050A JP 21501689 A JP21501689 A JP 21501689A JP 21501689 A JP21501689 A JP 21501689A JP H0379050 A JPH0379050 A JP H0379050A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- tape carrier
- bump
- insulating film
- conductor pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000004020 conductor Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims description 20
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 238000003825 pressing Methods 0.000 abstract description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 238000007747 plating Methods 0.000 description 6
- 239000011889 copper foil Substances 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000009719 polyimide resin Substances 0.000 description 3
- 238000005452 bending Methods 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229920006332 epoxy adhesive Polymers 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、テープキャリアに半導体チップを実装する、
テープキャリア方式の半導体装置の製造方法に関するも
のである。[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a method for mounting a semiconductor chip on a tape carrier.
The present invention relates to a method for manufacturing a tape carrier type semiconductor device.
近年、デイスプレィ、電子計算機など半導体を用いるデ
バイスにおいて、小型化・薄型化・高密度化のため、テ
ープキャリア方式が有望視されている。しかしながら、
従来のテープキャリアは、デバイス孔内へ突き出したリ
ードを形成する必要があったため工程が複雑で、不安定
なリードが変形するため歩留まりが悪く、このため極め
てコストも高いという欠点があった。In recent years, tape carrier systems have been viewed as promising for devices using semiconductors, such as displays and electronic computers, to make them smaller, thinner, and more dense. however,
Conventional tape carriers have disadvantages in that the process is complicated because it is necessary to form leads that protrude into the device hole, the yield is poor because the leads are unstable and deform, and the cost is therefore extremely high.
このような問題を解消するため、本発明者らは先に、デ
バイス孔へ突き出すリードを形成させるの
ことなく半導体チップを実装する方法を発明をなし開示
した。これは、第2図に示すように、まず絶縁性フィル
ム(1)と導電体(2)を接着剤(3)ではりあわせた
フレキシブル基板上に形成された導電体パターンに、バ
ンプ(6)を上面に形成した半導体チップ(5)をフェ
イスダウンで位置合わセをする。その後、絶縁性フィル
ム側からボンディングツール(7)を当接させ、絶縁性
フィルム(1〕を介して導電体バターンのリードの先端
の接続部と半導体チップ上のバンプ(6)を加熱加圧す
ることにより半導体チップ(5)を実装しテープキャリ
ア方式の半導体装置が完成する。この方法では、デバイ
ス孔を形成する必要がないため、工程が少なくて済み、
しかもデバイス孔へ突き出している導電体のリードが変
形する不良発生がないため、歩留まりが高く低コストに
なり、しかも接続部の信鯨性が高いという特徴があった
。In order to solve this problem, the present inventors have previously invented and disclosed a method for mounting a semiconductor chip without forming leads that protrude into device holes. As shown in Figure 2, bumps (6) are first formed on a conductor pattern formed on a flexible substrate made by gluing an insulating film (1) and a conductor (2) together with an adhesive (3). The semiconductor chip (5) having a structure formed on its upper surface is aligned face down. After that, the bonding tool (7) is brought into contact with the insulating film side, and the connection part of the lead end of the conductor pattern and the bump (6) on the semiconductor chip are heated and pressurized via the insulating film (1). The semiconductor chip (5) is mounted by this method, and a tape carrier type semiconductor device is completed.With this method, there is no need to form device holes, so the number of steps is reduced.
Moreover, since there is no defect such as deformation of the conductor lead protruding into the device hole, the yield is high and the cost is low, and the reliability of the connection part is high.
ところが、一般にボンディング時の温度・時間・圧力は
、テープキャリアを構成する絶縁性フィルム、銅箔(導
電体)、表面のメツキの種類、厚みなどにより組合せて
設定するものであるが、この方法の場合、設定の許容範
囲が狭く、特に400〜500℃の高温でボンディング
するため、設定の許容範囲を越えると、絶縁性フィルム
が熱分解したり、まったく接続できない状態になり、そ
の結果、歩留まりが低くなるという欠点が判明した。However, the temperature, time, and pressure during bonding are generally set depending on the insulating film that makes up the tape carrier, the copper foil (conductor), the type and thickness of the surface plating, etc., but this method In this case, the setting tolerance range is narrow, especially since bonding is performed at a high temperature of 400 to 500°C, so if the setting tolerance range is exceeded, the insulating film may thermally decompose or the connection will not be possible at all, resulting in lower yields. It turns out that the drawback is that it becomes lower.
本発明は、従来技術のこのような欠点に鑑みて種々の検
討の結果なされたものであり、その目的とするところは
、歩留まりが高く、低コストで、且つ信転性の高いテー
プキャリア方式の半導体装置を提供することにある。The present invention was developed as a result of various studies in view of the above drawbacks of the prior art, and its purpose is to provide a tape carrier system with high yield, low cost, and high reliability. The purpose of the present invention is to provide a semiconductor device.
すなわち本発明は、可とう性のある絶縁性フィルム上に
導電体で形成した回路パターンを有するテープキャリア
に半導体チップを実装する半導体装置の製造方法におい
て、リードの先端にバンプを形成した導電体パターンを
下側にしたテープキャリアを、バンプを形成した半導体
チップ上に載置し、位置合せした後、前記絶縁性フィル
ム側からボンディングツールを当接させ加熱加圧するこ
とを特徴とする半導体装置の製造方法である。That is, the present invention provides a method for manufacturing a semiconductor device in which a semiconductor chip is mounted on a tape carrier having a circuit pattern formed of a conductor on a flexible insulating film, and a conductor pattern having bumps formed at the tips of the leads. A tape carrier with the tape carrier facing downward is placed on a semiconductor chip on which bumps have been formed, and after alignment, a bonding tool is brought into contact with the insulating film side and heated and pressurized. It's a method.
以下、図面により本発明の詳細な説明する。Hereinafter, the present invention will be explained in detail with reference to the drawings.
第1図は本発明による半導体装置の製造方法を示す図で
ある。絶縁性フィルム(1)と導電体(2)を接着剤(
3)で貼りあわせたフレキシブル基板上にフォトエツチ
ングなどの方法により形成された導電体パターンのリー
ドの先端をメツキ、エツチングなどの方法でちりあげて
バンプ(8)を形成し、表面にメツキ(4)を施したテ
ープキャリア(9)を用意する。FIG. 1 is a diagram showing a method of manufacturing a semiconductor device according to the present invention. Connect the insulating film (1) and conductor (2) with adhesive (
The tips of the leads of the conductive pattern formed by photo-etching or other methods on the flexible substrate bonded in step 3) are removed by plating, etching, or other methods to form bumps (8), and the surface is plated (4). ) A tape carrier (9) is prepared.
このテープキャリア(9)の導電体パターンを下側にし
て、上面側にバンプ(6)を形成した半導体チップ(5
)の上に載置し、チップ上のバンプ(6)と導電体パタ
ーンのリードの先端のバンプ(8)との位置を合わせる
。S*いて、絶縁性フィルム(1)側からボンディング
ツール(7)を当て、押圧しながら導電体パターンに半
導体チップ(5)を接続する。With the conductor pattern of this tape carrier (9) facing downward, the semiconductor chip (5) has bumps (6) formed on its upper surface.
) and align the bumps (6) on the chip with the bumps (8) at the ends of the leads of the conductor pattern. S*, apply the bonding tool (7) from the insulating film (1) side and connect the semiconductor chip (5) to the conductive pattern while pressing.
このように、半導体チップ(5)と同様に、導電体パタ
ーンのリードにほんのわずかのバンプ(8)を形成する
ことによりボンディングの温度・時間・圧力の設定の許
容範囲を拡大することができ、極めて簡単に半導体チッ
プ(5)を実装することができる。In this way, similarly to the semiconductor chip (5), by forming just a few bumps (8) on the leads of the conductive pattern, it is possible to expand the allowable range of temperature, time, and pressure settings for bonding. The semiconductor chip (5) can be mounted extremely easily.
本発明において使用する絶縁性フィルム(1)と導電体
口)との積層体は、通常フレキシブル印刷回路用基板と
して用いられているものであれば何ら特定するものでは
ないが、絶縁性フィルム(1)を介して加熱加圧するた
め、絶縁性フィルム(1)、接着剤(3)はポリイミド
樹脂などのように耐熱性があり、かつできるだけ薄いも
のであるほうが望ましい。The laminate of the insulating film (1) and the conductor port used in the present invention is not particularly limited as long as it is normally used as a flexible printed circuit board. ), it is desirable that the insulating film (1) and adhesive (3) be heat resistant, such as polyimide resin, and as thin as possible.
さらには、絶縁性フィルム(1)上に蒸着、スパッタリ
ング、メツキなどの方法で金属膜を形成し、もしくは、
金属箔上にエポキシ樹脂、ポリイミド樹脂などの絶縁性
樹脂を塗布、乾燥して得られた、接着剤を使用しない2
層構造の積層体であれば、耐熱性を低下させ、あるいは
ボンディングツールにる加熱加圧の際に熱を遮る層が少
なくなるので、よりよい結果を与える。Furthermore, a metal film is formed on the insulating film (1) by a method such as vapor deposition, sputtering, plating, or
No adhesive is used, obtained by coating insulating resin such as epoxy resin or polyimide resin on metal foil and drying it.
A laminate with a layered structure provides better results because there are fewer layers that reduce heat resistance or block heat during heating and pressurization using a bonding tool.
通常のデバイス孔のあるテープキャリア方式の半導体装
置では、半導体チップ上のバンプのかわりに、メツキ、
エツチング、転写などによりデバイス孔へ突き出したリ
ードの先端にバンプを形成する方法が工夫されているが
、細い不安定なリードの為工程が長くなり、歩留まりも
高(なくコスト高になるものであるのに対し、本発明に
おける導電体パターンのリードの先端へのバンプ(8)
の形成は、リードの裏に絶縁性フィルム(1)があるた
め、リードの先端のみ部分的にメツキを厚くつけたり、
導電ペーストを塗布したり、先端以外の部分をエツチン
グで細くするなど一般に行われている方法で節単に行な
うことができ、その方法は特に限定するものではない、
また、バンプ(8)の高さは、特に制限はないがその効
果から考えて1〜50μmの間が望ましい。In tape carrier type semiconductor devices with normal device holes, plating and bumps are used instead of bumps on the semiconductor chip.
Etching, transfer, etc. have been devised to form bumps on the tips of the leads that protrude into the device holes, but because the leads are thin and unstable, the process is long and yields are high (and costs are high). In contrast, the bump (8) on the tip of the lead of the conductor pattern in the present invention
Since there is an insulating film (1) on the back of the lead, the formation of the lead is done by applying a thick plating to only the tip of the lead.
This can be easily done by a commonly used method such as applying a conductive paste or etching the part other than the tip, and the method is not particularly limited.
Further, the height of the bump (8) is not particularly limited, but considering the effect, it is preferably between 1 and 50 μm.
導電体パターン表面上にはメツキ(4)を施しであるが
、その材質は金、錫、半田など特に限定するものではな
いが、半導体チップ(5)上のバンプ(6)の材質にあ
わせるほうが好ましい。The surface of the conductor pattern is plated (4), and the material is not limited to gold, tin, solder, etc., but it is better to match the material of the bumps (6) on the semiconductor chip (5). preferable.
本発明の方法で使用するボンディングツール(7)は、
600℃、1秒、200g/リード以上の加熱加圧がで
き、半導体チップとの平行度が5μm以下の通常使用さ
れているものであれば特に限定するものではない。The bonding tool (7) used in the method of the present invention is:
It is not particularly limited as long as it can be heated and pressed at 600° C. for 1 second at 200 g/lead or more and has a parallelism with the semiconductor chip of 5 μm or less and is commonly used.
このように、本発明では、デバイス孔を必要としない新
しいフィルムキャリア方式の半導体装置の製造方法のボ
ンディング条件の制御の難しさという欠点を排除するこ
とができ、高い歩留まりで、低コストかつ高倍転性のフ
ィルムキャリア方式の半導体装置が得られる。As described above, the present invention can eliminate the drawback of difficulty in controlling the bonding conditions of the new film carrier type semiconductor device manufacturing method that does not require device holes, and can achieve high yield, low cost, and high multiplication. A film carrier type semiconductor device is obtained.
以下、本発明の実施例と従来方法による比較例を示す。Examples of the present invention and comparative examples using conventional methods will be shown below.
厚さ35μmの電解銅箔にポリイミド樹脂を塗布・乾燥
して厚さ25μmの絶縁層を形成し、2層構造の積層体
を得た。これを幅35mのテープ状にスリットし、銅箔
面をエツチング加工によりパターン化した。その後マス
クを当てて、リードの先端に部分メツキで高さ約10μ
mのバンプを形成し、表面にニッケル4.0tImを下
地にして金1.0μmのメツキを施しテープキャリアを
得た。A polyimide resin was coated on an electrolytic copper foil having a thickness of 35 μm and dried to form an insulating layer having a thickness of 25 μm to obtain a laminate having a two-layer structure. This was slit into a tape shape with a width of 35 m, and the copper foil surface was patterned by etching. After that, apply a mask and partially plate the tip of the lead to a height of about 10μ.
A tape carrier was obtained by forming bumps of m in diameter and plating the surface with 1.0 μm of gold using a nickel base of 4.0 tIm.
のバンプとを位置合わせし、ポリイミド樹脂絶縁層を介
して、ボンディングツールを用いて、温度を400.4
30.450℃、時間を0.5.1.2秒、荷重を80
.100.120g/リードとボンディング条件を変え
て加熱加圧して接合し、半導体チップの実装を行った。Using a bonding tool, adjust the temperature to 400.4
30.450℃, time 0.5.1.2 seconds, load 80
.. 100.120 g/lead and bonding conditions were changed and the semiconductor chips were bonded by heating and pressurizing and mounting the semiconductor chip.
得られた半導体装置には、銅パターンのリードの曲がり
のような変形を生ずることはなく、リードとチップとの
せん断強度はいずれの設定条件でも5 g/l 000
μポ以上であり、実用上問題の無いものであった。In the obtained semiconductor device, there was no deformation such as bending of the leads of the copper pattern, and the shear strength between the leads and the chip was 5 g/l 000 under any setting conditions.
It was more than μ point and there was no problem in practical use.
(比較例)
厚さ35μmの電解銅箔と、デバイスホールおよびスプ
ロケットホールを打抜いた厚さ75μmのポリイミドフ
ィルムとを、エポキシ系接着で貼合わせた幅35mの3
層テープの銅箔面をパターン化し、Ni0.5μmおよ
びAu1μmのメツキを施して、従来方式のテープキャ
リアを作成した。(Comparative example) A 35 m wide 35 m thick electrolytic copper foil with a thickness of 35 m and a 75 m thick polyimide film with device holes and sprocket holes punched out are pasted together using epoxy adhesive.
The copper foil surface of the layered tape was patterned and plated with 0.5 μm of Ni and 1 μm of Au to create a conventional tape carrier.
次に、半導体チップ上の金バンプとテープキャリアのデ
バイスホール内へつきだしたリードとを、400℃、1
sec、100g/リード荷重で、加熱加圧して接続し
たところ、一部にリードの曲がり等による不良が目立ち
、歩留りは78%と低いものであった。Next, the gold bumps on the semiconductor chip and the leads protruding into the device holes of the tape carrier were heated at 400°C for 1 hour.
When the wires were connected by heating and pressurizing the wires under a load of 100 g/lead, defects such as bending of the leads were noticeable in some parts, and the yield was as low as 78%.
このように、本発明の方法に従うと、テープキャリア方
式の半導体装置の従来の欠点である歩留りの低さと高コ
ストを克服することができるばかりでなく、ボンディン
グ条件の許容範囲の狭さも克服することができ、極めて
簡単なボンディング条件の設定で半導体チップを実装す
ることができ、その結果、歩留まりが高く低コストで、
かつ信頼性の高い半導体装置を得ることが可能となる。As described above, according to the method of the present invention, it is possible not only to overcome the conventional drawbacks of tape carrier type semiconductor devices, such as low yield and high cost, but also to overcome the narrow tolerance range of bonding conditions. This allows semiconductor chips to be mounted with extremely simple bonding conditions, resulting in high yields and low costs.
Moreover, it becomes possible to obtain a highly reliable semiconductor device.
第1図は、本発明による半導体装置の製造方法を示す図
である。第2図は、従来のデバイス孔のないテープキャ
リア方式の半導体装置の製造方法を示す図である。FIG. 1 is a diagram showing a method for manufacturing a semiconductor device according to the present invention. FIG. 2 is a diagram showing a conventional method for manufacturing a tape carrier type semiconductor device without device holes.
Claims (1)
した回路パターンを有するテープキャリアに半導体チッ
プを実装する半導体装置の製造方法において、リードの
先端にバンプを形成した導電体パターンを下側にしたテ
ープキャリアを、バンプを形成した半導体チップ上に載
置し、位置合わせした後、前記絶縁性フィルム側からボ
ンディングツールを当接させ加熱加圧することを特徴と
する半導体装置の製造方法。(1) In a method for manufacturing a semiconductor device in which a semiconductor chip is mounted on a tape carrier having a circuit pattern formed of a conductor on a flexible insulating film, a conductor pattern with bumps formed at the tips of the leads is placed on the tape carrier. A method for manufacturing a semiconductor device, which comprises placing a tape carrier with a tape carrier on its side on a semiconductor chip on which bumps have been formed, aligning the same, and then bringing a bonding tool into contact with the insulating film side to apply heat and pressure.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21501689A JPH0379050A (en) | 1989-08-23 | 1989-08-23 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21501689A JPH0379050A (en) | 1989-08-23 | 1989-08-23 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0379050A true JPH0379050A (en) | 1991-04-04 |
Family
ID=16665331
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21501689A Pending JPH0379050A (en) | 1989-08-23 | 1989-08-23 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0379050A (en) |
-
1989
- 1989-08-23 JP JP21501689A patent/JPH0379050A/en active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102017142A (en) | Three-dimensionally integrated semiconductor device and method for manufacturing the same | |
US9021690B2 (en) | Method of manufacturing printed circuit board having buried solder bump | |
US20040106288A1 (en) | Method for manufacturing circuit devices | |
JPH0357617B2 (en) | ||
JPH03101142A (en) | Manufacture of semiconductor device | |
JP2002170853A (en) | Flip chip mounting method | |
KR0165883B1 (en) | Gold/tin eutectic bonding for tape automated process | |
JPH0379050A (en) | Manufacture of semiconductor device | |
JPH03129745A (en) | Mounting of semiconductor device | |
JPH0385741A (en) | Manufacture of semiconductor | |
JPH0385739A (en) | Mounting of semiconductor device | |
JPH03104133A (en) | Semiconductor device | |
JPH03126237A (en) | Manufacture of semiconductor device | |
JPH03126236A (en) | Manufacture of semiconductor device | |
JPH03101140A (en) | Semiconductor device | |
JP2705263B2 (en) | Method for manufacturing TAB tape carrier | |
JPH03131045A (en) | Manufacture of semiconductor device | |
JPH039546A (en) | Manufacture of semiconductor device | |
JPH0379049A (en) | Manufacture of semiconductor device | |
JP2000340594A (en) | Transfer bump sheet and manufacture thereof | |
JPH0385740A (en) | Semiconductor device | |
JPH0379051A (en) | Mounting method of semiconductor device | |
JP3028413B1 (en) | Electronic circuit device | |
JPH01112741A (en) | Connection of integrated circuit | |
JP2879159B2 (en) | Method of forming electrical connection member and metal bump |