JPH0378788B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit using an inverted GaAs static induction transistor.

An I ² L logic circuit (hereinafter referred to as SITL) using an inverted static induction transistor (hereinafter referred to as SIT) has already been patented by one of the inventors of the present invention.
Disclosed in No. 1208034 (Special Publication No. 58-38938) "Semiconductor Integrated Circuits", prototyped with Si and achieved minimum delay time.
A value of 2fJ was obtained for the power delay product at 3.5nsec.
Of course, considering the abundance of materials and the completeness of the manufacturing process to construct large-scale integrated circuits (LSI),
SITL will continue to be composed of Si. However, when extremely high-speed logical operations are required, materials with high carrier mobility may be used.
SITL configuration is now required. With the exception of Si, GaAs is a material that can be obtained relatively stably and of high quality, has some existing manufacturing processes, and has high electron mobility. The possibility of an I ² L circuit using GaAs has already been shown by one of the inventors of the present invention (Japanese Patent Laid-Open No. 18392/1983), and several other proposals have been made. However, since the emitter region of the injector transistor and the gate region of the driving SIT are not in contact with the common source region,
There was an accumulation effect of minority carriers, and there was a limit to high-speed operation.

The purpose of the invention is to operate at very high speeds.
The present invention relates to a GaAs electrostatic induction transistor integrated circuit and provides an integrated circuit having an electrical←→optical conversion element in a signal input/output section.

The present invention will be described in detail below with reference to the drawings.

FIG. 1a shows a one-input, two-output I ² L type SITL inverter circuit using an SIT as a driving transistor and a bipolar transistor as a load transistor.

FIGS. 1b and 1c are a plan view and a sectional view taken along the line A-A' of a specific example of the inverter circuit shown in FIG. 1a. The n ⁺ region 11 is a substrate, the n ^- region 12 is an epitaxially grown layer, and the n ⁺ region on the surface is also an epitaxially grown layer. That is, p ⁺ regions 13 and 14 are formed at predetermined positions on a wafer in which an n ^- layer and an n ⁺ layer of a predetermined thickness and impurity density are successively epitaxially grown on an n ⁺ GaAs substrate by diffusion, ion implantation, etc. It has a configuration formed by. The n ⁺ region 11 serves as the source of the drive SIT, and the n ^- region 12 serves as the channel of the drive SIT and the base of a load bipolar transistor (hereinafter referred to as BJT). The p ⁺ region 13 is the emitter of the load BJT, and the p ⁺ region 14 is the collector of the load BJT and the drive SIT.
It is the gate of The n ⁺ regions 15-1 and 15-2 are the drains of the driving SIT, respectively. 11′,
13', 14', 15-1', and 15-2' are electrodes, respectively. The ohmic electrode in the p ⁺ region is InAg,
Ohmic electrodes in the n ⁺ region such as AgZn, AuGe, etc.
Made of AuGeNi etc. Furthermore, other metals may be provided in layers thereon. 16 is an insulating layer;
For example, the sputter may be SiO ₂ or Si ₃ N ₄ formed by CVD, Al ₂ O ₃ formed by sputter, GaO _x N _y formed by CVD, or a composite insulating film formed by stacking a plurality of these.
In particular, when an insulating layer with few surface states is required, GaO _x N _y with a small O to N ratio may be provided near the surface, and the O to N ratio may be increased as the distance from the surface increases. The channel width and impurity density of the driving SIT are selected so that the channel is completely pinched off only by the diffusion potential between the gate and the channel, and the SIT is in a cut-off state. p ⁺
When the impurity density of the region is about 10 ¹⁸ to 10 ²⁰ cm ^-3 , the depletion layer extends almost only to the n ^-channel region side. The impurity density in the n ^-region is 1×10 ¹⁴ cm ^-3 , 1×
The diffusion potential at 10 ¹⁵ cm ^-3 is about 1.2V and 1.27V in GaAs.

Therefore, if the impurity density of the channel is set to, for example, 1
×10 ¹⁴ cm ^-3 and 1 × 10 ¹⁵ cm ^-3 , if the channel width is at least about 5.7 μm and 1.8 μm or less, the cutoff state is achieved at zero gate bias.
In other words, normally-off SIT is realized. If the impurity density N _D channel width is 2a, then N _D (2a) ² is
It should be selected so that it is 2.5×10 ¹⁵ cm ^-3 or less. However, 2a is in μm. As the source-drain length becomes shorter, the value of N _D (2a) ² needs to be gradually smaller than the above-mentioned value. If the source-drain distance l becomes too short compared to the channel width 2a, no matter how low the impurity density is,
It becomes impossible to achieve a shut-off state. A potential barrier of a certain height is created to prevent current from flowing even if a certain drain voltage is applied.
l/2a must be at least greater than 0.5. The distance between the p ⁺ regions 13 and 14 is desirably long enough to prevent holes injected from the emitter from disappearing by recombination within the base. That is, it is desirable that the length of the region where electrons exist without forming a depletion layer is equal to or less than the hole diffusion length. The hole diffusion distance l _d in GaAs is, for example, the hole mobility 400 cm ² /V.
sec, and the life time is 10 nsec, it is about 3 μm.
Therefore, the spacing between p ⁺ regions 13 and 14 is level or lower. however,
N _D is the impurity density in the n ⁻ region, e is the unit charge, ε is the dielectric constant, and l _d is the diffusion length.

For example, if N _D is 1×10 ¹⁴ cm ⁻³ or 1×10 ¹⁵ cm ⁻³ , the value is about 8.7 μm, 4.8 μm or less. Of course, a punching-through state may also occur.

V _EE is the supply voltage, V _io is the input power, V _put1 , V _put2
are the output voltages, respectively. V _EE is naturally selected to a value such that no forward current flows directly between the p ⁺ region 13 and the n ⁺ region 11. Since the impurity density of n ⁺ region 11 is usually about 1×10 ¹⁸ cm ^-3 or higher, the diffusion potential between p ⁺ region 13 and n ⁺ region 11 is about 1.4 to 1.5 V. Therefore, _VEE is selected to be, for example, about 1.0 to 1.3V. of course,
It may be lower than this. Input voltage to the gate V _io
is at a low level (e.g. 0.1-0.3V),
The drive SIT is in a cut-off state. Therefore, the output voltage _Vput is at a high level (for example, about 0.8 to 1.2V)
It is in. The current supplied from the load BJT flows to the drain of the SIT in the previous stage. When the input voltage changes to a high level, the driving SIT becomes conductive and the output voltage transitions to a low level. In other words, it operates as an inverter. When the gate voltage changes to a high level, the potential barrier created in the channel is lowered or disappears, and at the same time, the space charge effect of the holes injected from the gate promotes the injection of electrons from the source, and the small This allows a large drain current to flow even with the channel area, which is the reason for the increased speed.

Further, the electron mobility in GaAs is about five times higher than the electron mobility in Si.

Therefore, even if the same voltage is applied between the source and drain and the same number of carriers exist, the current will be larger in GaAs due to its greater mobility.
That is, since the same current can be passed through a small channel area, gate capacitance is reduced and high-speed operation can be performed. To shut off SIT when it is conducting, the gate is turned low, but the accumulation time of the minority carriers, or holes, injected into the channel limits the speed.
In the case of GaAsSIT, since GaAs is a direct transition crystal, the recombination time of electrons and holes is short, and the accumulation time is short, so extremely high-speed operation is possible.

Except for the part that should be the drain of the drive SIT,
The n ⁺ layer existing on the surface has no positive meaning and does not need to exist. An example of a one-input, two-output SITL inverter constructed by removing that part is shown in FIG. In the same structure where the surface n ⁺ layer is removed, the load transistor is
Figure 3 shows an example of a MOSFET. electrode 14'
The insulating layer interposed between the n ^- region 12 is formed thinly so that an inversion layer is formed on the surface. When using a GaAs MOSFET, the gate insulating film is required to have a small number of surface states. Therefore. The GaO _x N _y film produced by the CVD method is excellent. When a GaO _x N _y film with an O/N ratio of about 0.1 to 0.2 is placed in direct contact with the surface and the O/N ratio is gradually increased as it moves away from the surface, the strength of the film also improves.
desirable. In this example, the gate and drain are directly connected. Of course, the gate may be directly connected to the source or may be operated by applying a predetermined potential.

In Figures 1 to 3, an example is shown in which the p ⁺ area has just reached the n ⁺ area 11, but it is not necessary to do this, and the p + area has not yet reached the n ⁺ area. It may also be sufficient to reach the n ⁺ region.
The manufacturing process for GaAs is still insufficient. However, in multilayer epitaxial growth, the thickness and impurity density can be controlled with good reproducibility in both vapor phase growth and liquid phase growth. Therefore, for example, if the impurity density is about 5×10 ¹³ to 5×10 ¹⁵ cm ^-3
The n ^- layer is grown on the n ⁺ substrate to a thickness of, for example, 0.5 to 2 μm,
Furthermore, it is easy to grow an n ⁺ layer having an impurity density of about 10 ¹⁷ to 10 ¹⁸ cm ^-3 to a thickness of, for example, about 0.2 to 0.5 μm. Of course, the values of the thickness and impurity density of each layer are not limited to these values. The p ⁺ region is formed by Zn diffusion. For this reason, the impurity density in the n ⁺ region is set lower than that in the p ⁺ region. Currently GaAs
In this case, diffusion by Zn is the only diffusion process that can be performed stably. During Zn diffusion, if As escapes from the GaAs crystal and deteriorates the crystallinity, it is necessary to add As at the same time to suppress the escape of As.
If a vapor pressure of
Can be spread. The p ⁺ formation may be performed by ion implantation of Cd or Be. The surface n ⁺ layer may be formed by ion implantation or diffusion of S, Se, Te, etc., depending on the case. For example ^, an n + layer having an impurity concentration of about 10 ¹⁸ cm ^-3 and a thickness of 0.1 to 0.2 μm may be selectively formed in a portion other than the portion to become a p ⁺ region by using Se ion implantation. In the current situation where there is no insulating layer that can serve as a good diffusion mask, ion implantation in the p ⁺ region may be more accurate. Regarding the insulating layer, it is currently impossible to perform processes such as thermal oxidation on Si, so we use sputtering or CVD methods to create SiO ₂ , Si ₃ N ₄ ,
Al ₂ O ₃ , AlN or GaO _x N _y may be provided.
Therefore, the structures shown in FIGS. 1 to 3 can be sufficiently produced by a relatively simple process of n ^- and n ⁺ double-layer epitaxial growth on an n ⁺ -GaAs substrate and p ⁺ selective Zn diffusion. It can be achieved.

As the scale of an integrated circuit increases, the number of input and output terminals to the chip naturally increases. Currently, bonding pads are provided around the chip and taken out to the outside using metal wire or metal tape, but as the number of input/output terminals increases, the area for this increases, which hinders the improvement of the degree of integration. Furthermore, when the number of bonding parts increases, it becomes a cause of lowering yield and reliability. GaAs is a direct transition crystal, making it an extremely efficient light-emitting diode. If a thin p ⁺ region of a predetermined size is formed at a predetermined location that will become the input/output terminal part, and a forward bias is applied to allow current to flow, an extremely efficient light emitting diode can be obtained. It becomes a photodiode for light detection. In other words, information can be transmitted between chips using light rather than electricity using metal wires. To improve the efficiency of light extraction to the outside and focus the light on a predetermined location on other chips, the GaAs surface is coated with SiO ₂ , SiO, Si ₃ N ₄ , GaAlO,
It is also effective to provide Al ₂ O ₃ , GaO _x N _y or a mixture thereof on a light emitting diode or photodiode so as to have a lens effect. Of course, it is also effective to connect a large number of predetermined locations in parallel using optical fibers. Optical coupling does not necessarily have to be performed around the chip; it is sufficient to provide the input/output terminals at optimal and efficient locations. To connect many chips, a chip with a photodiode for receiving light is placed in a position corresponding to a portion of one chip that corresponds to a light emitting diode serving as an output terminal. For example, by arranging the chips in alternating upward and downward directions, many chips can be operated by optical coupling. An example of an output terminal section using a light emitting diode and an input terminal section using a photodiode is shown in FIGS. 4 and 5. In Figure 4, T ₁ and T ₂ are bipolar transistors for load, T ₃ is SIT for drive,
D is a light emitting diode. When T ₃ is in the cutoff state, the drain of T ₃ is at a high level, so
The current flowing through the load transistor _T2 flows through the light emitting diode D and emits light to the outside. When T ₃ is conductive, the output terminal of T ₃ is at a low level, so no current flows through diode D and no light is emitted. That is, when the output level is high, there is optical output, and when the output level is low, there is no optical output. 61: n ⁺ substrate, 62: n ^- epitaxial growth layer, 63: emitter of T ₂ , 64: collector of T ₂ ,
65: Gate of T ₃ , 66: Drain of T ₃ , 6
7: p ⁺ region of light emitting diode D, 68: insulating layer,
63': emitter electrode, 65': gate electrode of SIT, 66': drain electrode. P ⁺ region 64 is connected to drain region 66 through an electrode. p ⁺
Almost no forward current flows between region 63 and n ⁺ region 61, and current flows in p ⁺ 67-n ^- 62-n ⁺ 61 because the diffusion potential difference of p ⁺ n ^- is small. . In order to make it easier for current to flow through the light emitting diode portion, the impurity density in the region sandwiched between the p ⁺ region 67 and the n ⁺ region 61 may be lowered. GaAs
In materials where there is a large difference in the mobility of electrons and holes, as in the case of materials with large mobility differences, electrons, which have higher mobility, play a leading role in injection. Therefore, p ⁺ region 67 and n ⁺ region 61
The region between is preferably a p-type high resistance region. Of course, it is also effective to set the power supply voltage at the output stage a little higher than at other parts to make it easier for the current to flow. The output part is not a light emitting diode,
Of course, a semiconductor laser may also be used.

In FIG. 5, _T4 is a driving SIT, _T5 is a bipolar transistor for load, and _D1 is a photodiode. When no light is incident on D ₁ , the gate of T ₄ is at a high level and T ₄ is in a conducting state. When light enters D ₁ , the voltage across D ₁ decreases,
The current of the load transistor T ₅ will now mostly flow through D ₁ , and T ₄ will be in a cut-off state. Figure 5b is a plan view, c is a sectional view along line A-A', and d is B-
FIG. 3 is a sectional view taken along line B'. 71:n ⁺ board, 7
2: n ^- epitaxial growth layer, 73: emitter of load transistor, 74: collector of load transistor and drive gate of drive SIT, 75: drive SIT
fixed potential gate, 76-1, 76-2 are drains of SIT, 77: p ⁺ region of photodiode,
78: Insulating layer, 73': Emitter electrode, 76-
1', 76-2': Drain electrode. The p ^- region 79 is a high resistance region for improving light receiving efficiency. Although the photodiodes are connected in the forward direction in FIG. 7, they can of course be connected in the reverse direction.

FIG. 6 shows an example in which a photodiode is connected in the opposite direction to form an optical input section. This is an example in which the load transistor is a MOSFET. The optical input P _io is incident on a reverse biased photodiode. When light is incident, current flows through the photodiode, so the gate of SIT is charged to a predetermined potential,
SIT becomes conductive. When light is no longer incident, no current flows into the gate, the gate potential returns to a low level, and the SIT becomes cut off. power supply
V _EE ′ is determined by the characteristics of the photodiode. Usually V _EE ′ will be higher than V _EE .

If the gate and drain of an SIT that operates as an inverter is biased too deeply in the forward direction, the operating speed will also decrease. For example, 0.8~1.1V with gate high level and 0.1~1V with drain low level.
Too deep forward bias between the gate and drain, such as 0.2V, is inconvenient for increasing operating speed. In order to prevent the voltage between the gate and drain from becoming too deep, shotgun diodes D ₁ and D ₂ may be inserted between the gate and drain of the SIT, as shown in FIG. In this example, the load transistor is a MOSFET
As shown in the example below. If the forward voltage drop of a Schottky diode is _Vf , then the difference between the high level and low level of the voltage will not be larger than _Vf . Schottky diodes can be formed by vapor deposition or plating of metals such as Al, Pt, and Pd. Inverter SIT p ⁺
A shotgun diode made of the metal described above may be provided on a part of the surface of the gate region and directly connected to the drain through an electrode. Alternatively, the metal Schottky diode may be provided in a part of the drain of the SIT and connected to the gate region. Usually GaAs
Then, the barrier height of the Schottky junction in the n-type region is p
Higher than the short junction barrier height of the shaped region. Therefore, if you want to reduce the difference between high and low voltage levels, you can create a shot junction in the p ⁺ gate region, and if you want a slightly larger difference, you can create a shot junction in the n ⁺ drain region. All you have to do is set it up.

I ² L-type SITL using GaAsSIT with the structure of the present invention
Because GaAs has high electron mobility and is a direct transition crystal, minority carriers injected into the channel recombine quickly and have little accumulation effect, increasing the current delivery rate of lateral bipolar transistors. It is extremely effective, especially in areas where high-speed operation is required, and GaAs has a higher diffusion potential than Si, so the operating voltage can be higher than that of Si.
It has a large noise margin and can be manufactured satisfactorily using current manufacturing technology, so its industrial value is extremely high.

[Brief explanation of drawings]

Figure 1 shows an example of an I ² L type GaAs SIT inverter (1 input, 2 outputs) used in the present invention, where a is an equivalent circuit, b is a plan view, and c is a cross section taken along line A-A' in figure b. Figure 2 shows an I ² L type GaAsSIT used in the present invention.
Another cross-sectional structure example of an inverter, Figure 3 shows the load
Another example of the cross-sectional structure of the I ² L-type GaAsSIT inverter used in the present invention, which is an IGFET, is shown in FIG. The figure shows an embodiment of the present invention in which a photodiode is provided at the input section, where a is an equivalent circuit, b is a plan view, c is a cross-sectional structural diagram taken along line A-A' in figure b, and d is a B-- A cross-sectional structural diagram taken along line B', FIG. 6 is an embodiment of the present invention that operates with optical input;
FIG. 7 is an equivalent circuit diagram of an embodiment of the present invention.

Claims (1)

[Scope of Claims] 1. A low resistivity n-type GaAs substrate, a relatively high resistivity layer grown in two layers on the first main surface of the substrate, and a low resistivity n-type GaAs surface. a plurality of p-type regions having an impurity density higher than that of the n-type GaAs, the plurality of p-type regions having a higher impurity density than the n-type GaAs, which are formed so as to penetrate the growth layer and contact the n-type substrate; the first and second p-type regions have two common parts and at least two adjacent pairs of p-type regions, and the first and second forming a horizontal bipolar transistor, at least a portion forming a third vertical static induction transistor formed by the p-type common portion, the substrate, and the n-type growth layer, and having the p-type layer as a gate; comprising a portion configured such that the collector region of the first bipolar transistor is as common as the gate region of the static induction transistor, and is adjacent to the drain region of the third vertical static induction transistor; A GaAs semiconductor device characterized by being equipped with a light emitting diode that converts electrical signal output into an optical signal. 2. The GaAs semiconductor device according to claim 1, wherein the first and second load transistors are insulated electrode type transistors. 3. A low resistivity n-type GaAs substrate, a relatively high resistivity layer and a low resistivity n-type GaAs surface layer grown on the first main surface of the substrate, and a plurality of p-type regions having an impurity density higher than that of the n-type GaAs, which are formed so as to penetrate through the layer and be in contact with the n-type substrate; and a pair of p-type regions in which the plurality of p-type regions are at least adjacent to each other. forming a first lateral bipolar transistor using the pair of p-type regions and the GaAs high resistivity layer existing therebetween, one of the pair of p-type regions and the substrate; and an n-type growth layer,
A portion forming a second vertical static induction transistor having the p-type layer as a gate, and a portion configured such that the collector region of the bipolar transistor is as common as the gate region of the static induction transistor. , converting an optical input signal into an electrical signal, comprising the substrate configured to contact the preferably common portion, a relatively high resistivity p-type region, and a relatively low resistivity p-type surface layer. It is characterized by being equipped with a photodiode that
GaAs semiconductor device. 4. The GaAs semiconductor device according to claim 3, wherein the first load transistor is an insulated electrode transistor.