JPH0376071B2 - - Google Patents
Info
- Publication number
- JPH0376071B2 JPH0376071B2 JP57104444A JP10444482A JPH0376071B2 JP H0376071 B2 JPH0376071 B2 JP H0376071B2 JP 57104444 A JP57104444 A JP 57104444A JP 10444482 A JP10444482 A JP 10444482A JP H0376071 B2 JPH0376071 B2 JP H0376071B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- light receiving
- substrate
- accumulating section
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 13
- 238000003384 imaging method Methods 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 5
- 230000010354 integration Effects 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は固体撮像装置に係り、特にインタク
ライン転送方式の固体撮像装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a solid-state imaging device, and particularly to an intercline transfer type solid-state imaging device.
固体撮像装置のうち、インタライン転送方式と
呼ばれるものの構造を示せば、第1図及び第2図
に示す様である。
Among solid-state imaging devices, the structure of a so-called interline transfer method is shown in FIGS. 1 and 2.
半導体基板10には、複数の且つとびとびの半
導体領域11a,11b,11c,…から成る受
光蓄積部11が形成され、この蓄積部11は基板
10と共にpnを接合を形成し外部からの光照射
によつて得られる信号電荷を蓄積する。この信号
電荷はシフトゲート15に印加されるゲートパル
スによつて電荷転送路12を形成する半導体領域
に移送される。 A light receiving and accumulating section 11 is formed on the semiconductor substrate 10 and is made up of a plurality of discrete semiconductor regions 11a, 11b, 11c, . The signal charge thus obtained is accumulated. This signal charge is transferred to the semiconductor region forming the charge transfer path 12 by a gate pulse applied to the shift gate 15.
電荷転送路12は蓄積部11の各領域11a,
11b,11c,…に対応してとびとびに設けた
転送電極16に所定のクロツクパルスを印加する
ことにより、前記信号電荷を出力部(図示せず)
まで転送し電気信号として取出す。 The charge transfer path 12 connects each region 11a of the storage section 11,
By applying a predetermined clock pulse to transfer electrodes 16 provided at intervals corresponding to 11b, 11c, . . . , the signal charges are transferred to an output section (not shown).
and extract it as an electrical signal.
また、ドレイン13は蓄積部11で生じた過剰
電荷を排除し、これらの電荷が信号に悪影響を及
ぼさない様にするためのものである。このため、
蓄積部11とドレイン13の間の領域14の上に
ゲート17を設け、例えば第2図で示す導電型の
各領域に対して第3図に示す様なポテンシアルの
山P14及び谷P13を形成することにより、蓄
積部の過剰電子18をドレイン13側に引込む様
にする。 Further, the drain 13 is used to eliminate excess charges generated in the storage section 11 and to prevent these charges from adversely affecting signals. For this reason,
A gate 17 is provided on the region 14 between the storage portion 11 and the drain 13, and potential peaks P14 and valleys P13 as shown in FIG. 3 are formed for each region of the conductivity type shown in FIG. 2, for example. By doing so, the excess electrons 18 in the storage section are drawn toward the drain 13 side.
しかし、以上の様な構成によれば、ドレイン1
3及び領域13がかなりの面積を占めるため、半
導体素子の集積化の障害となつていた。
However, according to the above configuration, the drain 1
3 and region 13 occupy a considerable area, which has been an obstacle to the integration of semiconductor devices.
この発明は、以上の様な従来技術の欠点を除去
するために成されたものであり、素子の集積度を
向上させ得る新規な構成の固体撮像装置を提供す
ることを目的とする。
The present invention was made in order to eliminate the drawbacks of the prior art as described above, and an object of the present invention is to provide a solid-state imaging device with a novel configuration that can improve the degree of integration of elements.
〔発明の概要〕
この目的を達成するため、この発明によれば、
半導体基板上に形成しこの基板と共にpn接合を
形成した外部からの光照射によつて得られる信号
電荷を蓄積する複数の且つとびとびの半導体領域
から成る受光蓄積部と、この受光蓄積部の付近の
前記基板上に形成され前記信号電荷を取出すため
の半導体領域である電荷転送路とを具えた固体撮
像装置において、前記受光蓄積部の各半導体領域
中に前記基板と同じ導電型で外部から電圧を印加
し得る島状領域を有する様にする。[Summary of the invention] In order to achieve this object, according to this invention,
A light receiving and accumulating section is formed on a semiconductor substrate and consists of a plurality of discrete semiconductor regions that accumulate signal charges obtained by external light irradiation, forming a pn junction with this substrate, and a light receiving and accumulating section in the vicinity of this light receiving and accumulating section. In a solid-state imaging device comprising a charge transfer path formed on the substrate and serving as a semiconductor region for extracting the signal charge, each semiconductor region of the light receiving and accumulating section has the same conductivity type as the substrate and is supplied with an external voltage. It is made to have an island-like area to which the voltage can be applied.
更に詳しくは、この島状領域に電圧を印加して
ドレインとして活用するようにする。 More specifically, a voltage is applied to this island-like region to use it as a drain.
以下、添付図面に従つてこの発明の実施例を説
明する。
Embodiments of the present invention will be described below with reference to the accompanying drawings.
第4図及び第5図はこの発明の実施例に係るイ
ンタライン転送方式の固体撮像装置を示し、それ
ぞれ上断面図及び横断面図である。同図によれ
ば、半導体基板40上に受光蓄積部41及び電荷
転送路42が形成され、また双方の間にはシフト
ゲート45が設けられ、電荷転送路42には転送
電極46が設けられている。 FIGS. 4 and 5 show an interline transfer type solid-state imaging device according to an embodiment of the present invention, and are a top sectional view and a horizontal sectional view, respectively. According to the figure, a light receiving and accumulating section 41 and a charge transfer path 42 are formed on a semiconductor substrate 40, a shift gate 45 is provided between the two, and a transfer electrode 46 is provided in the charge transfer path 42. There is.
以上の構成において、この発明によれば、受光
蓄積部41の構成が著しく異なる。すなわち、受
光蓄積部41は複数の且つとびとびの半導体領域
41a,41b,…から成り、基板40と共に
pn接合を形成し外部上方からの光照射によつて
信号電荷を発生蓄積させるようにするものであ
る。 In the above configuration, according to the present invention, the configuration of the light receiving and accumulating section 41 is significantly different. That is, the light receiving and accumulating section 41 is made up of a plurality of discrete semiconductor regions 41a, 41b, . . . together with the substrate 40.
A pn junction is formed and signal charges are generated and accumulated by external light irradiation from above.
しかも、この実施例によれば、この受光蓄積部
41の各半導体領域41a,41b,…中に基板
40と同じ導電型の島状領域43a,43b,…
を設けてある。この島状領域43a,43b,…
は後述するようにドレインとして用いることがで
きる。 Moreover, according to this embodiment, in each of the semiconductor regions 41a, 41b, .
is provided. These island-like regions 43a, 43b,...
can be used as a drain as described later.
これらの各要素41,42,43を有する半導
体基板40の表面は絶縁膜47で蔽われており、
また絶縁膜47中にはシフトゲート45及び転送
電極46が埋設されている。更に、この絶縁膜4
7の上には受光用の窓部分48′を除いてしや光
用のシールド金属層48で蔽われている。この
際、このシールド金属を利用して前述の島状領域
43a,43b,…への接続を行うべく、接続路
48aを設けてある。 The surface of the semiconductor substrate 40 having each of these elements 41, 42, 43 is covered with an insulating film 47,
Further, a shift gate 45 and a transfer electrode 46 are buried in the insulating film 47. Furthermore, this insulating film 4
7 is covered with a shielding metal layer 48 for low light except for a window portion 48' for light reception. At this time, a connection path 48a is provided in order to connect to the above-described island regions 43a, 43b, . . . using this shield metal.
ここで、第5図に示す様な導電型の固定撮像装
置の島状領域43をドレインとして用いる場合に
は次の様に駆動する。駆動に先立つてシブトゲー
ト45はオフ状態としておく。次に、シールド金
属層48を介して第6図に示す様に領域43に電
圧P3を印加しておく。こうすることにより、受
光用窓部分48′を介して光照射された際、領域
41で光電変換された信号電荷が蓄積され領域4
1のポテンシヤルP1が下がる。電荷の蓄積によ
つて領域41のポテンシヤルP1が領域43に印
加したポテンシヤルP3より小さくなると、領域
41及び領域43の間のpn接合が順バイアス状
態となり、過剰電荷が電源iとして流出する。ポ
テンシヤルP1はポテンシヤルP3より小さくな
ることはなく、従つて、強い入射光により発生し
た過剰電荷を領域43を介して排出させることが
できる。 Here, when using the island-shaped region 43 of a conductive type fixed imaging device as shown in FIG. 5 as a drain, it is driven as follows. Prior to driving, the shift gate 45 is turned off. Next, a voltage P3 is applied to the region 43 via the shield metal layer 48 as shown in FIG. By doing this, when light is irradiated through the light receiving window portion 48', signal charges photoelectrically converted in the region 41 are accumulated and transferred to the region 4.
1's potential P1 decreases. When potential P1 of region 41 becomes smaller than potential P3 applied to region 43 due to charge accumulation, the pn junction between region 41 and region 43 becomes forward biased, and excess charge flows out as power supply i. Potential P1 is never smaller than potential P3, so that excess charges generated by strong incident light can be drained away via region 43.
以上の実施例において、導電型が第5図の場合
と逆であつてよいのはもちろんのことであり、ま
た島状領域43を領域41内に形成する場合の場
所も特に第4図の部分に限定されることはない。 In the above embodiments, it goes without saying that the conductivity type may be opposite to that shown in FIG. It is not limited to.
この発明は、以上の様に受光蓄積部を成す半導
体領域中に島状領域を設け、これをドレインとし
て活用することにより、素子の集積度を向上させ
ることのできる新規な構成の固体撮像装置を提供
することができる。
As described above, this invention provides a solid-state imaging device with a novel configuration that can improve the degree of integration of elements by providing an island-like region in the semiconductor region forming the light receiving and accumulating section and utilizing this as a drain. can be provided.
第1図は従来のインタライン転送型固体撮像装
置の上断面図、第2図は第1図のXX′線における
横断面図、第3図は第1図従つて第2図の装置に
ポテンシヤルを印加した場合の動作説明図、第4
図はこの発明の実施例に係る装置の上断面図、第
5図は第4図のYY′線における横断面図、第6図
は第4図従つて第5図の装置にポテンシヤルを印
加した場合の動作説明図である。
40……半導体基板、41……受光蓄積部、4
2……電荷転送路、43……島状領域、45……
シフトゲート、46……転送電極、47……絶縁
膜、48……シールド金属層、48′……受光用
窓部分。
Figure 1 is a top sectional view of a conventional interline transfer type solid-state imaging device, Figure 2 is a cross-sectional view taken along line XX' in Figure 1, and Figure 3 shows the potential of the device in Figure 1 and therefore Figure 2. Explanatory diagram of operation when applying , 4th
The figure is a top sectional view of a device according to an embodiment of the present invention, FIG. 5 is a cross-sectional view taken along the YY' line of FIG. 4, and FIG. FIG. 40...Semiconductor substrate, 41...Light reception storage unit, 4
2...Charge transfer path, 43...Island region, 45...
Shift gate, 46... Transfer electrode, 47... Insulating film, 48... Shield metal layer, 48'... Light receiving window portion.
Claims (1)
合を形成し外部からの光照射によつて得られる信
号電荷を蓄積する複数の且つとびとびの半導体領
域から成る受光蓄積部と、この受光蓄積部の付近
の前記基板上に形成され前記信号電荷を取出すた
めの半導体領域である電荷転送路とを具えた固体
撮像装置において、前記受光蓄積部の各半導体領
域中に前記基板と同じ導電型の島状領域を形成
し、この島状領域に前記電荷転送路を蔽う光シー
ルド金属を電気的に結合して電圧を印加したこと
を特徴とする固体撮像装置。1. A light receiving and accumulating section formed on a semiconductor substrate and consisting of a plurality of discrete semiconductor regions that form a pn junction together with this substrate and accumulating signal charges obtained by external light irradiation, and the vicinity of this light receiving and accumulating section. A solid-state imaging device comprising a charge transfer path formed on the substrate and serving as a semiconductor region for extracting the signal charge, wherein each semiconductor region of the light receiving and accumulating section includes an island-like region of the same conductivity type as the substrate. What is claimed is: 1. A solid-state imaging device characterized in that a light shield metal covering the charge transfer path is electrically coupled to the island-shaped region, and a voltage is applied thereto.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57104444A JPS58220578A (en) | 1982-06-17 | 1982-06-17 | Solid-state image pickup device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57104444A JPS58220578A (en) | 1982-06-17 | 1982-06-17 | Solid-state image pickup device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58220578A JPS58220578A (en) | 1983-12-22 |
JPH0376071B2 true JPH0376071B2 (en) | 1991-12-04 |
Family
ID=14380810
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57104444A Granted JPS58220578A (en) | 1982-06-17 | 1982-06-17 | Solid-state image pickup device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58220578A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5775455A (en) * | 1980-10-29 | 1982-05-12 | Sony Corp | Solid state pickup element |
-
1982
- 1982-06-17 JP JP57104444A patent/JPS58220578A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5775455A (en) * | 1980-10-29 | 1982-05-12 | Sony Corp | Solid state pickup element |
Also Published As
Publication number | Publication date |
---|---|
JPS58220578A (en) | 1983-12-22 |
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