JPH02278767A - Solid-state image sensing device - Google Patents

Abstract

PURPOSE:To reduce a knee effect by a method wherein substrates are pasted, a transfer electrode is arranged and installed in a region between a substrate and another substrate for reinforcement use and a high-concentration impurity region is formed around a picture-element region. CONSTITUTION:In a frame-transfer type charge-coupled device formed by pasting substrates, a silicon substrate 1 where a plurality of picture-element regions 3 have been arranged on the surface side is pasted on an n-type silicon substrate 2 as a substrate for reinforcement use. Transfer electrodes 32, 33 which are formed on the rear of the substrate and which are taken out between the picture-element regions 3 are provided. In addition, a highconcentration impurity region 4 is formed so as to surround the picture-element regions 3. In this case, an aperture rate can be increased by a pasted structure. Accordingly, even when an impurity concentration is made sufficiently high, it is possible to restrain a sensitivity from being deteriorated. A low resistance can be realized by the high concentration; a knee effect can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frame transfer type solid-state imaging device constructed by bonding substrates together.

[Summary of the Invention] The present invention provides a solid-state imaging device in which a reinforcing substrate is bonded to the back side of a substrate, in which a transfer electrode is disposed between the substrates, a plurality of pixel regions are formed on the surface of the substrate, and the transfer electrode is removed. By forming a frame transfer type in which the pixel region is surrounded by a high concentration impurity region, the knee effect can be reduced.

[Conventional technology]

Generally, a solid-state imaging device such as a COD (charge-coupled device) has a structure in which pixels are arranged on one main surface of a substrate. FIG. 7 shows an example of a typical conventional solid-state imaging device, in which a p-type well region 102 is formed in a silicon substrate 101. A transfer electrode 104 is formed under the light shielding film 103 formed on the substrate surface, and an n-type impurity '+yJ region formed in the well region 102 under the transfer electrode 104 forms a charge transfer section 105.
It is said that The light receiving section 106 of each pixel has its charge transfer section 1
05 through a gate portion 107, and each pixel is surrounded by a channel stopper region +08 made of a p-type impurity region.

In the solid-state I-imaging device with this structure, when light enters the light receiving section 106, an electron-hole bear is generated in the light receiving section 106, and the electrons therein pass through the charge transfer section 105 and become signal charges. being carried out.

In addition, pixels each having a light receiving section are arranged on one main surface of a semiconductor substrate such as a silicon substrate, and a charge transfer section is formed on the other main surface of the substrate. A solid-state imaging device with a structure in which parts are pasted together (
For example, see JP-A-63-129661. ) is also known.

[Problem to be solved by the invention]

As described above, in the light receiving section 106, not only electrons but also holes are generated. This hole is transferred to the channel stopper region 10
8, and a potential drop occurs in the channel stopper region 108. As a result, the depth of the potential in the light receiving section 106 becomes deeper, and a knee effect occurs in which the signal charge increases only slightly with the light intensity.

In order to alleviate this knee effect, it is sufficient to reduce the resistance of the channel stone bar region 108. but,
In order to reduce the resistance of the channel stopper region 108,
If the impurity concentration is increased, the impurities will be greatly diffused, and the area of the light receiving section 106 will eventually become smaller.If the area of the light receiving section 106 is reduced in this way, the amount of signal charge will decrease. This is disadvantageous in achieving high density and high resolution carbonization.

SUMMARY OF THE INVENTION Therefore, the present invention aims to provide a solid-state imaging device that utilizes a technique for bonding substrates together, and particularly to provide a solid-state imaging device that can reduce the knee effect.

[Means for Solving the Problem] In order to achieve the above object, the solid-state imaging device of the present invention is a frame transfer type solid-state imaging device,
A substrate, a plurality of pixel areas formed on the front side of the substrate, a transfer electrode formed on the back side of the substrate and taken out between the pixel areas, and a reinforcing substrate bonded to the back side of the substrate. A high concentration impurity region is formed to surround the pixel region.

[Function] By forming a bonded structure in which the reinforcing substrate is bonded to the NWJ side of the substrate, a structure in which a plurality of pixel regions are formed on the front side of the substrate and transfer electrodes are formed on the back side of the substrate. Can be done. Therefore, no transfer electrode is formed on the front surface side, which is the light-receiving side, and a large light-receiving area can be obtained. The transfer electrode is sandwiched between the substrate and the reinforcing substrate, but since it is taken out between the pixel area, a metal electrode for shunting, etc. can be placed on the surface side, and the signal charge can be transferred at high speed. Transfer becomes possible. Further, such a structure in which the light is extracted between the pixel regions prevents an adverse effect on the potential due to the work function of the metal electrode or the like. Then, a high concentration impurity region is formed around the pixel, but since the aperture ratio can be increased due to the bonded structure, deterioration of sensitivity is suppressed even if the impurity concentration is sufficiently high, and the high concentration reduces resistance. can be realized and the knee effect can be reduced.

[Example] Preferred embodiments of the present invention will be described with reference to the drawings.

The solid-state imaging device of this embodiment is an example of a frame transfer type CCD in which substrates are bonded together. First, the structure of the CCD will be explained.

As shown in FIGS. 1 to 3, in the COD of this embodiment, a silicon substrate 1 on which a plurality of pixel regions 3 are arranged on the surface side is bonded to an n-type solicon substrate 2, which is a reinforcing substrate. It has a similar structure.

As shown in FIG. 5, each pixel region 3 has a planar shape in which each cell has a substantially rectangular pattern, and each pixel region 3 is arranged in a matrix.

Each of these pixel regions 3 is separated by a p° type high concentration impurity region 4 in the transfer direction shown as the ■ direction in the figure, and is similarly separated by a p° type high concentration impurity region 4 in the H direction in the figure perpendicular to the transfer direction. A silicon oxide film 5 separated by region 4 and formed between the p° type high concentration impurity region 4, and a transfer electrode extraction portion 6 formed between the silicon oxide film 5. It is also separated by and,
In each pixel region 3, a region surrounded by the p'-type high concentration impurity region 4 in both the V direction and the H direction in the figure functions as a light receiving section. Further, the P' type high concentration impurity region 4 is a region surrounding the pixel region 3, and functions as a channel stone bar. This p-type high concentration impurity region 4 covers the sides of the pixel regions 3 from the front surface to the back surface of the substrate l between each pixel region 3 in the H direction in the figure, and covers the sides of each pixel region 3 in the A buried channel layer 1 is formed between the pixel region 3 from the surface of the base IFil.
1. This p° type high concentration impurity region 4 is made to have a sufficiently high impurity concentration. In the CCD of this embodiment, which uses a region surrounded by such a p-type high concentration impurity region 4 as a light receiving section, members such as a light shielding section and a transfer electrode are not formed on the light receiving surface of the light receiving section. The light receiving section itself can have a large area. In other words, since a large light-receiving area can be obtained, the light-receiving area is not impaired even if the impurity concentration of the ρ type high-concentration impurity region 4 is made sufficiently high. Therefore, as described above, the impurity concentration of the p-type high concentration impurity region 4 can be made sufficiently high, and as a result, the knee effect can be reduced.

The structure in the depth direction of each pixel region 3 having such a planar shape is as shown in FIGS. 1 and 2, in which the silicon oxide film 7. Thin p-type impurity H region8. P-type well head loading9. N-type well regions 10 are formed in sequence. The silicon oxide film 7 formed on the most surface side 1s is a film that covers the substrate surface, and is a film formed on the substrate surface for shunting. It is also used to separate the electric scratching layer 31 and the control electrode layer 21 of the npn transistor 20.

P-type impurity '# formed on the back side of the silicon oxide film 7
6MMB2 is an M region formed for noise reduction, and is continuous to the next p-type well region 9. On the back side of this p-type well region 9, an n-type well region IO is successively formed. A potential mountain is formed between the n-type well region 10 and the p-type well region 9, and when light from an object is incident, photoelectrons are collected as signal charges on the n-type well region IO side. In addition, n-type well region 1
The depths of the 0 and p-type well regions 9 are determined by their spectral sensitivities.

A buried channel layer 11 is formed on the back side of this n-type well region 10. This embedded channel 1
As shown in FIG. 3, the reference numeral 111 is commonly used in each column between the pixel regions 3 arranged in the ■ direction, and is continued in the ■ direction on the back side of each n-type well region IO of each pixel region 3. Ru. Therefore, the CCD of this embodiment can transfer frames. Silicon oxide I on the back side of this buried channel ill.
T! J5 is formed, and transfer electrodes 32 and 33 are formed on the back side of the substrate with the silicon oxide film 5 interposed therebetween. The transfer electrodes 32 and 33 are composed of two polysilicon layers, in which the 1st and 2Nth polysilicon layers are alternately arranged at predetermined intervals in the transfer direction, and each layer has a longitudinal direction perpendicular to the transfer direction. It is formed into a common electrode pattern in the transfer column. A drive signal is supplied to each transfer electrode 32, 33 with a wiring configuration described below, and the drive signal is, for example, two-phase. As shown in FIG. 3, the buried channel layer 11 is designed to reflect the pattern of these transfer electrodes 32 and 33, and to form an n'' type storage section and a transfer section consisting of stepped potentials. impurity regions 34 and n'' type impurity regions 35 are alternately formed. An interlayer insulating film 36 is provided on the back side of these transfer electrodes 32 and 33.
is formed, and each transfer electrode 32 is formed by this interlayer insulating film 36.
．． 33 is coated. By arranging the transfer electrodes 32 and 33 on the back side lb of the silicon substrate 1, the area of the light receiving portion of each pixel region 3 can be increased compared to a CCD in which the transfer electrodes are formed on the light receiving surface side. A thin polysilicon layer 37 is formed over the entire surface of the interlayer insulating film 36, and the n-type silicon substrate 2 is bonded to the back surface of the thin polysilicon layer 37 for reinforcement. The thin polysilicon layer 37
is also used to sweep out unnecessary charges.

The transfer electrodes 32 and 33 are arranged on the back side 1 of the silicon substrate l.
The transfer electrodes 32 and 33 are arranged between the silicon substrate 2 and the silicon substrate 1 which are bonded together for reinforcement, but are taken out from the front side Is of the substrate. That is, on the surface side lS of the silicon substrate l,
A low-resistance aluminum wiring layer 30, 31 for the shunt is formed. The aluminum wiring layers 30 and 31 contain a trace amount of silicon. Note that it is also possible to use other metal wiring layers for the shunt. These aluminum wiring layers 30 and 31 each have signals Φ1. Φ is supplied and wired on the area between each pixel area 3 with the ■ direction as the longitudinal direction. These aluminum wiring layers 30.3
1 is connected to the transfer electrode lead-out portion 6 made of a polysilicon layer through an opening 36 formed in the silicon oxide film 7 covering the surface of the substrate. This transfer electrode extraction part 6 is
A region sandwiched between a p° type high concentration impurity region 4 provided between each column of the pixel region 3 and a silicon oxide film 5 formed therebetween, and penetrating the front and back surfaces of the substrate l. This is a part of the electrode formed in the groove. This electrode extraction part 6
are formed continuously with one of the transfer electrodes 32.33, and the signals Φ1. One of Φ will be supplied. As described above, since the CCD of this embodiment has a bonded structure, the transfer electrodes 32 and 33 formed between the substrates are taken out between the pixel areas 3, and the aluminum wiring is formed on the surface side IS! 32.33, the resistance of the entire transfer electrode can be reduced, which is advantageous for high-speed transfer. In addition, the aluminum wiring N3233 is also connected between the pixel areas 3 and ffJI.
Since the light receiving area is formed in the area, the light receiving area does not become smaller. Furthermore, since the aluminum wiring layers 30.31 are connected via the transfer electrode lead-out portion 6, the work function of the aluminum wiring layers 30.31 affects the transfer electrodes 32, 33, causing potential fluctuations. Prevented.

On the back side of each pixel region 3, a buried channel layer 11 as described above is formed, and in each pixel region 3, an npn type bipolar transistor 20 is formed in succession to the buried channel layer 11. . First, the emitter of this bipolar transistor 20 is formed on the buried channel layer 11 formed on the back surface side of the pixel region 3.
, whose embedded channel Jill
A p-type impurity region 22 is formed along the silicon oxide film 5 on the back side of the substrate adjacent to the p-type impurity region 22 . This p° type impurity region 22 is formed surrounding each pixel region 3.
It is connected to the high concentration impurity region 4 of the mold. This p-type high concentration impurity region 4 is formed from the back surface to the front surface of the substrate 1, and is connected to the 99-type channel stopper region 23 on the surface of the substrate 1. A potential is applied to the p° type channel stopper region 23 from a control electrode layer 21 formed on the substrate surface side IS, and by supplying a base potential to this control electrode layer 21, an npn type bipolar transistor is formed. 20 is controlled. The collector of this npn type bipolar transistor 20 is
p0 type impurity region 22 and its p゛ type impurity region 2
This is an n-type impurity region 24 surrounded by a p-type impurity region 25 formed on the surface side of the second region. This n-type impurity region 24 is connected to a polysilicon layer 26 on the back side. The polysilicon layer 26 is a layer used as a wiring between the n° type impurity region 24, which is the collector, and the thin polysilicon layer 37.

In order to connect these n-type impurity regions 24 and polysilicon layer 37, a silicon oxide film 5. The transfer electrode 32 arranged on the back side of the silicon oxide film 5, the transfer electrode 3
A through groove 27 is formed to penetrate the glabella insulating film 36 disposed on the back side of the device. The through groove 2 of the transfer electrode 32
A silicon oxide film 28 is formed on the side wall of the polysilicon layer 2, and the transfer electrode 32 and the polysilicon layer 2 are formed by this silicon oxide film.
6 is insulated.

Such a bipolar transistor 20 functions as an overflow controller and an electronic shutter,
Unnecessary charges in the buried channel l1ill can be swept out to the polysilicon layer 37 through the polysilicon layer 26. The sweeping is controlled by the voltage applied to the control electrode layer 21 wired on the surface of the substrate. FIG. 4 shows an equivalent circuit in each pixel. The cathode side of the photodiode 51 is connected to the emitter of a bipolar transistor 52, and signal charges are accumulated when light is incident on this emitter. When sweeping out unnecessary charges, bipolar transistor 5
By applying a required voltage to the base of the bipolar transistor 52, unnecessary charges are swept out to the collector of the bipolar transistor 52. Thereby, the bipolar transistor 52 functions as an electronic shutter or an overflow drain.

Since the CCD of this embodiment having such a structure has the silicon substrates 1 and 2 bonded together, the transfer electrodes 32 and 33 can be placed between the substrates. Therefore, there is no need to provide a transfer electrode on the light receiving surface of the pixel region 3, and the light receiving area can be increased to one size. Therefore,
The p-type high concentration impurity region 4, which functions as a channel stopper, can be made to have a sufficiently high impurity concentration, and as a result, the knee effect can be reduced.

Further, the p type high concentration impurity region 4 which can be made to have such a high impurity concentration not only functions as a channel stopper but also functions as a wiring for controlling the bipolar transistor 20. Therefore, it becomes easy to increase the density.

Further, in the CCD of this embodiment, the transfer electrodes 32 and 33 are arranged between the silicon substrates 1 and 2 due to the bonded structure. However, since these transfer electrodes 32 and 33 are taken out to the front surface side Is of the substrate l between each pixel region 3, the shunt aluminum wiring layers 30 and 33 are placed on the front surface side.
can be arranged. Therefore, high-speed transfer is possible, and the buried channel layer 1
I will not give it to 1.

In addition, in the CCD of this embodiment, the buried channel layer 1
Since the bipolar transistor 20 is formed continuously from the transistor 1, electronic shutter operation and overflow control are possible.

Next, referring to FIGS. 6a to 6r, the CCD of this embodiment will be described.
An example of a manufacturing method will be described.

First, as shown in FIG. 6a, a p-type silicon substrate 61
An n-type epitaxial layer 62 is formed thereon, and an n-type impurity is introduced into the main surface of the n-type epitaxial layer 62 to form an n-type impurity region 63. This n-type impurity region 63 is used as a buried channel layer. Further, along with the formation of the n-type impurity region 63, a p-type impurity region 64 is formed for each pixel region. This p-type impurity region 64 functions as a base region of an npn-type bipolar transistor. Such an n-type impurity region 6
Etching is performed from the main surface of the n-type epitaxial layer 62 in which the p-type impurity regions 64 and 3 are formed to form grooves 65 that separate the columns of each pixel region. This groove 65 is formed by cutting down to the p-type silicon substrate 61,
The RYE method is performed using a so-called trench technique.

Further, the groove 65 is formed in contact with the p-type impurity region 64.

Next, as shown in FIG. 6, p-type impurities are introduced at a high concentration into the sides and bottoms of trenches 65 formed to separate the columns of each pixel region. By introducing this p-type impurity, a p-type high concentration impurity region 66 is formed on the sides and bottom of the isolation layer 65. This p' type high concentration impurity region 66 is connected to the p type impurity region 64.

Next, as shown in FIG. 6C, a silicon oxide film 6 is formed on the entire surface.
7 is formed. The silicon oxide film 67 can be formed by surface oxidation or CVD. The silicon oxide film 67 separates each pixel region from column to column, and provides a channel for transferring signal charges in a MOS structure.

Next, as shown in FIG. 6d, a first layer of polysilicon 1168 is formed, and this first layer of polysilicon 6
8 is patterned into a pattern of transfer electrodes having predetermined intervals in the transfer direction and with the longitudinal direction perpendicular to the transfer direction. This first polysilicon layer 68 is connected to the groove 65.
The filled portion functions as a transfer electrode extraction portion. The first polysilicon layer 6
After patterning 8, the surface of the polysilicon layer 68 is oxidized. Then, selective ion implantation is performed using the polysilicon layer 68 as a mask, so that the n-type impurity region 63 is formed with a storage region and a transfer region having a stepped potential. Next, a second polysilicon layer 69 is formed on the entire surface, and patterned into a transfer electrode pattern so that it remains in the region between each first polysilicon layer 68.

A two-layered transfer electrode is now placed on the silicon oxide film 67.

Next, a glabellar insulating film 70 is formed on the first and second layers of polysilicon 1168 and 69 that will become transfer electrodes. This glabellar insulation 870 is, for example, a flowable membrane,
After forming by the C, VD method, it is flattened by heat treatment. After forming the glabellar insulating film 70, although not shown, the glabellar insulating film 70. A through trench penetrating the 11th polysilicon layer 68 and silicon oxide film 67 is formed. The inside of the through trench is oxidized, and an insulating film is formed between it and the polysilicon layer 68. After such a through groove is formed, a polysilicon layer 71 is formed on the entire surface, and the inside of the through groove is also filled. Then, as shown in FIG. 6e, a silicon substrate 72 is bonded onto the polysilicon layer 71 or via an oxide film for reinforcement.

Next, as shown in FIG. 6f, the p-type silicon substrate 61 is shaved from the side opposite to the surface to which the silicon substrate 72 is bonded. By cutting this p-type silicon substrate 61 to the depth of the groove 65, the p-type silicon substrate is first separated into each column, and then a polysilicon layer 6 that becomes a transfer electrode is separated.
A take-out portion 8.69 is exposed on the substrate surface 73. Next, a p-type high-degree impurity region 74 is formed to separate the pixel regions in each column, a p-type high-concentration impurity region is formed to connect to the control electrode, and a p-type high-concentration impurity region is formed for noise reduction. A p-type impurity region as a surface accumulation layer is formed by ion implantation or the like. Next, a control electrode for controlling the bipolar transistor is formed, an insulating film between the eyebrows is formed, a contact hole is formed, and an aluminum wiring layer for a shunt is formed to complete the device.

[Effects of the Invention] The solid-state image device of the present invention has a structure in which the substrates are bonded to each other, and the transfer electrodes are arranged in the area between the substrate and the reinforcing substrate. can be formed. Therefore, the amount of signal charge increases and the sensitivity increases. In addition, since large pixels can be formed on the surface side of the substrate, even if a highly concentrated impurity region is formed around the pixel region, the area of the pixel will not be lost, and the impurity region can be made highly concentrated, which is a desirable feature. The effect can be reduced.

Further, since the transfer electrode is taken out from between the pixels to the front surface side, a metal wiring layer such as an aluminum wiring layer can be formed to reduce resistance, which is advantageous for high-speed transfer.

[Brief explanation of drawings]

FIG. 1 is a perspective view of a main part of an example of the solid-state image device of the present invention, FIG. 2 is a cross-sectional view of the main part of the example taken along a plane perpendicular to the charge transfer direction, and FIG. 3 is an example of the above-mentioned example. FIG. 4 is an equivalent circuit diagram of each pixel in the above example, and FIG. 5 is a plan view of the main part of the above example. Also,
FIGS. 6a to 6f are process cross-sectional perspective views showing an example of a manufacturing method of the solid-state image device, and FIG. 7 is a cross-sectional view of essential parts showing an example of a conventional solid-state image device. It is. 1.2...Silicon substrate 3...Pixel? iU region 4...High concentration impurity region 5...Silicon oxide film 6...Transfer electrode extraction portion 9...P type well region 10...N type well region 11...Buried channel layer 20...Bipolar transistor 21...Control electrode layer 30.31...Aluminum wiring layer 32.33...Transfer electrode 36...Interlayer insulating film 37...Polysilicon layer

Claims (1)

[Claims] A substrate, a plurality of pixel areas formed on the front side of the substrate, a transfer electrode formed on the back side of the substrate and taken out between the pixel areas, and a reinforcing substrate bonded to the back side of the substrate. A frame transfer type solid-state imaging device comprising: a high concentration impurity region formed to surround the pixel region.