JPH02278768A - Solid-state image sensing device - Google Patents

Abstract

PURPOSE:To sweep out unnecessary electric charges such as an electronic shutter operation, an overflow control operation or the like by a method wherein substrates are glued together, a transfer electrode is arranged and installed in a region between a substrate and another substrate for reinforcement use and a bipolar transistor is formed in a picture-element region. CONSTITUTION:In a frame-transfer type charge-coupled device formed by pasting substrates, a silicon substrate 1 where a plurality of picture-element regions 3 have been arranged on the surface side is glued on an n-type silicon substrate 2 as a substrate for reinforcement use. In addition, the following are provided: transfer electrodes 32, 33 which are formed on the rear of the substrate 1 and which are taken out between the picture-element regions 3; a bipolar transistor 20 for which one part of the picture-element regions 3 is used as an emitter. When a base potential of the bipolar transistor 20 is applied from the surface side of the substrate 1, a storage charge amount of the picture-element regions 3 is controlled. Thereby, it is possible particularly to sweep out unnecessary electric charges.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a frame transfer type solid-state imaging device whose device is constructed by bonding substrates together. In a solid-state imaging device in which substrates are bonded together, a transfer electrode is arranged between the substrates 1, a plurality of pixels are formed on the surface of the substrate, and the transfer electrode is taken out.
By performing this on the surface of the pixel and using a frame transfer type in which the pixel is surrounded by a high concentration impurity region, an operation such as sweeping out unnecessary charges is realized.

[Conventional technology]

Generally, a solid-state imaging device such as a CCD (charge-coupled device) has a structure in which pixels are arranged on one main surface of a substrate. FIG. 7 shows an example of a typical conventional solid-state imaging device, in which a p-type well region 102 is formed in a SIFCON substrate +01. A transfer electrode 104 is formed under the light shielding film 103 formed on the substrate surface, and an n-type impurity region formed in the well region 102 under the transfer electrode 104 serves as a charge transfer portion 105. The light receiving section 1 of each pixel (16 is the charge transfer section 105)
are continuous to each other via a gate portion 107, and each pixel is surrounded by a channel stopper region 108 made of an n-type impurity region.

This solid-state imaging device has a vertical overflow drain structure, and when unnecessary charges are generated in the light receiving section 106, the unnecessary charges are swept out to the silicon substrate 101 by applying a predetermined voltage to the substrate. It has a mechanism that allows Also, not only the overflow control 1Itl,
Electronic shutter operation is also possible.

In addition, pixels each having a light receiving section are arranged on one main surface of a semiconductor substrate such as a silicon substrate, and a charge transfer section is formed on the other main surface of the substrate. A solid-state imaging device having a structure in which solid-state imaging devices are bonded together is also known, and this technique is also described in, for example, Japanese Patent Laid-Open No. 12966/1983.

[Problems that the invention attempts to solve]

As mentioned above, in the vertical overflow drain structure,
Unnecessary charges can be swept out to the substrate. However, in a structure in which substrates are bonded together as in the technique described in the above-mentioned publication, the side of the substrate on which the light-receiving section is formed is shaved off pixel by pixel, making it difficult to sweep out unnecessary charges to the substrate.

On the other hand, by adopting a horizontal overflow drain structure, unnecessary charges can be swept out even in a solid-state imaging device in which the substrates are bonded together. However, in order to form a small area for overflow, the light receiving area is reduced, resulting in deterioration of sensitivity.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a solid-state imaging device that utilizes a technique for bonding substrates together, and particularly to provide a solid-state imaging device that can perform an operation of sweeping out unnecessary charges.

[Means for Solving the Problems] In order to achieve the above-mentioned object, the solid-state imaging device of the present invention is a frame transfer type solid-state imaging device that includes a substrate and a substrate formed on the surface side of the substrate. a plurality of pixel regions, a transfer electrode formed on the back surface of the substrate and taken out between the pixel regions, a reinforcing substrate bonded to the back surface side of the substrate, and a portion of the pixel region serving as an emitter. A bipolar transistor is provided, and a base potential of the bipolar transistor is applied from the front side of the substrate to control the accumulated charge in the pixel region.

[Function] By forming a bonded structure in which the reinforcing substrate is bonded to the back side of the substrate, a structure in which a plurality of pixels are formed on the front side of the substrate and transfer electrodes are formed on the back side of the substrate can be created. can. Therefore, no transfer electrode is formed on the front surface side which is the light receiving side.1. Large light receiving area can be obtained. The transfer electrode will be sandwiched between the substrate and the reinforcing substrate, but since it is taken out between the pixels, a metal electrode for shunt, etc. can be placed on the surface side, allowing high-speed transfer of signal charges. becomes possible. Furthermore, such a structure in which light is taken out between pixels prevents an adverse effect on the potential due to the work function of the metal electrode or the like. Then, a bipolar transistor having an emitter is formed in the pixel region, and its control is performed.
By performing this from the front side of the substrate, it is possible to control electronic shutter operation and overflow.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

The solid-state imaging device of this embodiment is an example of a frame transfer type CCD in which substrates are bonded together. First, the structure of the CCD will be explained.

As shown in FIGS. 1 to 3, the COD of this embodiment has a plurality of pixels M on an n-type silicon substrate 2, which is a reinforcing substrate.
It has a structure in which a silicon substrate 1 on which hi 3 is arranged on the surface side is bonded together.

As for the planar shape of each pixel area 3, as shown in FIG.
They are arranged in a matrix.

Each of these pixel regions 3 is separated by a P type high concentration impurity region 4 in the transfer direction shown as the direction (■) in the figure, and is similarly separated by a p type high concentration impurity region 4 in the H direction in the figure perpendicular to the transfer direction. A silicon oxide film 5 is separated by the impurity region 4 and formed between the p type high concentration impurity regions 4.
They are further separated by a transfer electrode extraction portion 6 formed between the silicon oxide film 5 and the silicon oxide film 5. In each pixel region 3, a region surrounded by the p-type high concentration impurity region 4 in both the {circle around (2)} direction and the H direction in the figure functions as a light receiving section. Further, the P° type high concentration impurity region 4 is a region surrounding the pixel region 3, and functions as a channel stopper. This p° type high concentration impurity region 4 is located at H in the figure.
The sides of the pixel regions 3 are covered between each pixel region 3 in the direction from the front surface to the back surface of the substrate 1; layer 1
1. This p type high concentration impurity region 4 is made to have a sufficiently high impurity concentration. Such a p°
In the CCD of this embodiment, the area surrounded by the high-concentration impurity region 4 of the mold is used as a light-receiving part.Since no members such as a light-shielding part or a transfer electrode are formed on the light-receiving surface of the light-receiving part, the light-receiving part itself is Can be made into a large area. In other words, since a large light-receiving area can be obtained, the light-receiving area is not impaired even if the impurity concentration of the p-type high-concentration impurity region 4 is made sufficiently high. Therefore, as described above, the impurity concentration of the p° type high concentration impurity region 4 can be made sufficiently high, and as a result, the knee effect can be reduced.

The structure in the depth direction of each pixel region 3 having such a planar shape is as shown in FIGS. 1 and 2, in which the silicon oxide film 1. 'ap-type impurity region 8. p-type well region9. N-type well regions 10 are formed in sequence. The silicon oxide film 7 formed on the most surface side 1s is a film that covers the substrate surface, and is a film formed between the Al electrode layer 31 formed on the substrate surface for shunting and the control electrode layer 21 of the npn transistor 20. Also used for separation.

A p-type impurity region 8 formed on the back side of silicon oxide II (J7) is a region formed for noise reduction and is continuous to the next p-type well region 9.This p-type well An n-type well region 10 is successively formed on the back side of the region 9. A mountain of votents is formed between the n-type well region 10 and the p-type well region 9, and light from the subject is incident thereon. In this case, photoelectrons are collected as signal charges on the n-type well region 10 side.
The depths of the 0 and p-type well regions 9 are determined by their spectral intensities.

A buried channel layer 11 is formed on the back side of this n-type well region 10. As shown in FIG. 3, this buried channel N11 is commonly used in each column among the pixel regions 3 arranged in the V direction, and is located on the back surface side of each n-type well region IO in each pixel region 3 in the is continued. Therefore, the CCD of this embodiment can transfer frames. The back side of this buried channel layer 11 is silicon oxidized +
125 is formed, and transfer electrodes 32 and 33 are formed on the back side of the substrate with the silicon oxide film 5 interposed therebetween. The transfer electrodes 32 and 33 are composed of two polysilicon layers, in which the first and second polysilicon layers are alternately arranged at predetermined intervals in the transfer direction, and the longitudinal direction is perpendicular to the transfer direction. A common electrode pattern is formed in each transfer column. A drive signal is supplied to each transfer electrode 32, 33 in the arrangement line configuration described below, and the drive signal is, for example, two-phase. As shown in FIG. 3, the buried channel N11 is filled with low-type impurities so as to form a storage part and a transfer part, each having a stepped potential, while reflecting the pattern of the transfer electrodes 32 and 33. Regions 34 and n-type impurity regions 35 are alternately formed. On the back side of these transfer electrodes 32 and 33, there is a glabella insulating film 36.
is formed, and each transfer electrode 32 is formed by this interlayer insulating film 36.
．． 33 is coated. By arranging the transfer electrodes 32 and 33 on the backside lb side of the silicon substrate 1, the area of the light receiving portion of each pixel region 3 can be increased compared to a CCD in which the transfer electrodes are formed on the light receiving surface side. A thin polysilicon layer N37 is formed on the entire surface of the interlayer insulating film 36, and the n-type silicon base ui2 is bonded to the back surface of the thin polysilicon layer 37 for reinforcement. The thin polysilicon layer 3
7 is also used for sweeping out unnecessary charges.

The transfer electrodes 32 and 33 are arranged on the back side 1 of the silicon substrate 1.
b, and are eventually formed between the silicon substrate 2 and the silicon substrate 1 which are bonded together for reinforcement, but the transfer electrodes 32 and 33 are taken out from the front surface side 1s of the substrate. That is, on the surface side is of the silicon substrate 1,
Low resistance aluminum wiring layers 30 and 31 for shunting are formed. The aluminum wiring layers 30 and 31 contain a trace amount of silicon. Note that it is also possible to use other metal wiring layers for the shunt. These aluminum wiring layers 30 and 31 have signals Φ6. Φ2 is supplied and wired on the area between each pixel area 3 with the ■ direction as the longitudinal direction. These aluminum wiring layers 30.3
1 is connected to the transfer electrode lead-out portion 6 made of a polysilicon layer through an opening 36 formed in the silicon oxide film 7 covering the surface of the substrate. This transfer electrode extraction part 6 is
A groove that penetrates the front and back surfaces of the substrate 10 in a region sandwiched between the p° type high concentration impurity region 4 provided between each column of the pixel region 3 and the silicon oxide film 5 formed therebetween. It is part of the electrode formed inside. This electrode extraction part 6
are formed continuously with one of the transfer electrodes 32.33, and the signals Φ1. One side of Φ2 will be supplied. As described above, since the CCD of this embodiment has a bonded structure, the transfer electrodes 32 and 33 formed between the substrates are taken out between the pixel areas 3, and the aluminum wiring layer 32 is formed on the surface side Is. .33, the resistance of the entire transfer electrode can be reduced, which is advantageous for high-speed transfer. Further, since the aluminum wiring layers 32 and 33 are also formed in the separation region between the pixel regions 3, the light receiving area is not reduced. moreover,
The aluminum wiring layers 30 and 31 are the transfer electrode extraction portions 6
The aluminum wiring layer 30.
The work function of 31 influences the transfer electrodes 32 and 33, thereby preventing potential fluctuations.

A buried channel layer 11 as described above is formed on the back surface side of each pixel region 3, and in each pixel region 3, an npn type bipolar transistor 20 is formed in succession to the buried channel layer. First, the emitter of this bipolar transistor 20 is connected to a buried channel layer 11 formed on the back surface side of the pixel region 3.
, and its head is part 1 of the channel layer 11
A p-type impurity region 22 is formed along the silicon oxide film 5 on the back side of the substrate adjacent to the p-type impurity region 22 . This p' type impurity region 22 is connected to a p' type high concentration impurity region 4 formed surrounding each pixel region 3. This p-type high-concentration impurity off region 4 is formed from the back surface to the front surface of the substrate l, and is connected to the p-type channel stopper region 23 on the front surface of the substrate l. A potential is applied to the p° type channel stopper region 23 from the control electrode layer 21 formed on the substrate surface side Is.
By supplying a base potential to the 8-electrode layer 21, the np
An n-type bipolar transistor 20 is controlled. The collector of this npn type bipolar transistor 20 includes a p° type impurity region 22 and a p type impurity region 25 formed on the surface side of the p° type impurity region 22.
This is an n-type impurity region 24 surrounded by. This n-type impurity region 24 is connected to the polysilicon layer 26 on the back side. The polysilicon layer 26 includes an n-type impurity region 24 which is a collector and the thin polysilicon layer 37.
This layer is used as wiring between.

These n-type impurity 9A regions 24 and polysilicon layer 37
In order to connect the silicon oxide film 5. A through groove 27 is formed so as to penetrate through the transfer electrode 32 disposed on the back side of the silicon oxide film 5 and the glabellar insulating film 36 disposed on the back side of the transfer electrode 32. A silicon oxide film 28 is formed on the side wall of the through groove 27 of the transfer electrode 32, and the silicon oxide film 28 insulates the transfer electrode 32 and the polysilicon layer 26.

Such a bipolar transistor 20 functions as an overflow control and an electronic shutter,
Unnecessary charges in the buried channel layer 11 can be swept out to the polysilicon layer 37 via the polysilicon layer 26. The sweeping is controlled by the voltage applied to the control electrode layer 21 wired on the surface of the substrate. FIG. 4 shows an equivalent circuit in each pixel. The cathode side of the photodiode 51 is connected to the emitter of a bipolar transistor 52, and signal charges are accumulated when light is incident on this emitter. When sweeping out unnecessary charges, a required voltage is applied to the base of the bipolar transistor 52 to sweep out the unnecessary charges to the collector of the bipolar transistor 52. This results in
The bipolar transistor 52 functions as an electronic shank and an overflow drain.

Since the CCD of this embodiment having such a structure has a structure in which the silicon substrates 1 and 2 are bonded together, the transfer electrodes 32 and 33 can be placed between the substrates. Therefore, there is no need to provide a transfer electrode on the light-receiving surface of the pixel region 3, and a large light-receiving area can be obtained. Therefore, the p-type high concentration impurity region 4 that functions as a channel stopper can be made to have a sufficiently high impurity concentration,
As a result, the knee effect can be reduced.

Furthermore, the p-type high-4 degree impurity region 4, which can be made to have a high impurity concentration, not only functions as a channel stopper but also functions as a wiring for controlling the bipolar transistor 20. Therefore, it becomes easy to increase the density.

Furthermore, in the COD of this embodiment, the transfer electrodes 32 and 33 are disposed between the silicon substrates 1 and 2 because of the bonded structure. However, since these transferred electric currents i32, 33 are taken out to the surface side 1s of the substrate l between each pixel region 3, an aluminum wiring layer 30, 33 for shunting is formed on the surface side.
can be arranged. Therefore, high-speed transfer is possible, and the influence of potential fluctuations due to the work functions of the aluminum wiring layers 30 and 31 can be suppressed through the buried channel 1'.
It will not be given to W11.

In addition, in the CCD of this embodiment, the buried channel layer 1
Since the bipolar transistor 20 is formed continuously from the transistor 1, electronic shutter operation and overflow control are possible.

Next, referring to FIGS. 6a to 6r, the CCD of this embodiment will be described.
An example of a manufacturing method will be described.

First, as shown in FIG. 6a, a p-type silicon substrate 61
An n-type epitaxial layer 62 is formed thereon, and an n-type impurity is introduced into the main surface of the n-type epitaxial layer 62 to form an n-type impurity region 63. This n-type impurity region 63 is used as a buried channel layer. Further, along with the formation of the n-type impurity region 63, a p-type impurity region 64 is formed for each pixel region. This p-type impurity region 64 functions as a base region of an npn-type bipolar transistor. Such an n-type impurity region 6
Pitaxial II! Etching is performed from the main surface of 162,
Grooves 65 are formed to separate the columns of each pixel region. This groove 65 is formed by cutting down to the p-type silicon substrate 61, and is formed by RIE using a so-called trench technique.

Further, the groove 65 is formed in contact with the p-type impurity region 64.

Next, as shown in FIG. 6, p-type impurities are introduced at a high concentration into the sides and bottoms of trenches 65 formed to separate the columns of each pixel region. By introducing this p-type impurity, a p-type high concentration impurity region 66 is formed on the sides and bottom of the isolation groove 65. This p° type high-4 degree impurity region 66 is connected to the p type impurity region 64.

Next, as shown in FIG. 6C, a silicon oxide film 6 is formed on the entire surface.
7 is formed. The silicon oxide film 67 can be formed by surface oxidation or CVD. If this silicon oxidation! 67 separates each pixel region column by column, and the channel for transferring signal charges has an MO3 structure.

Next, as shown in FIG. 6d, a 1Nth polysilicon layer 68 is formed.
are patterned into a pattern of transfer electrodes having predetermined intervals in the transfer direction and with the longitudinal direction perpendicular to the transfer direction. This first polysilicon layer 68 also fills the trench 65, and the filled portion functions as a transfer electrode extraction portion. After patterning the first polysilicon layer 68, the surface of the polysilicon layer 68 is oxidized. Then, selective ion implantation is performed using the polysilicon layer 68 as a mask, so that the n-type impurity region 63 is formed with a storage region and a transfer region having a stepped potential. Next, a second polysilicon layer 69 is formed on the entire surface, and patterned into a transfer electrode pattern so that it remains in the region between each first polysilicon layer 6B.

A two-layered transfer electrode is now placed on the silicon oxide film 67.

Next, an interlayer insulating film 70 is formed on the first and second layers of polysilicon [68, 69, which will become transfer electrodes. This interlayer insulating film 70 is, for example, a flowable film, and C
After forming by the VD method, it is flattened by heat treatment. After forming the interlayer insulating film 70, although not shown, the interlayer insulating film 7
0. A through trench penetrating the 171st polysilicon layer 68 and silicon oxide film 67 is formed. The inside of the through trench is oxidized, and an insulating film is formed between it and the polysilicon layer 68. After such a through groove is formed, a polysilicon layer 71 is formed on the entire surface, and the inside of the through groove is also filled.

Then, as shown in FIG. 6e, a silicon substrate 72 is bonded onto the polysilicon layer 71 or via an oxide film for reinforcement.

Next, as shown in FIG. 6f, the p-type silicon substrate 61 is shaved from the surface opposite to the surface to which the silicon substrate 72 is bonded. By cutting this p-type silicon substrate 61 to the depth of the groove 65, the p-type silicon substrate is first separated into each column, and then a polysilicon layer 6 that becomes a transfer electrode is separated.
A take-out portion 8.69 is exposed on the substrate surface 73. Next, a p° type high concentration impurity region 74 is formed to separate the pixel regions in each column, a p゛ type high concentration impurity region is formed to connect to the control electrode, and furthermore, a A p-type impurity region as a surface accumulation layer is formed by ion implantation or the like. Next, a control electrode for controlling the bipolar transistor is formed, a glabellar insulation ++g is formed, a contact hole is formed, and an aluminum wiring layer for a shunt is formed to complete the device.

Because it is possible to form a pixel with a high density, even if a high-1 degree impurity region is formed around the jl region of the pixel, the area of the pixel will not be reduced, and since the impurity region can be made highly concentrated, the knee effect can be reduced. can be achieved.

Further, since the transfer electrode is taken out from between the pixels to the front surface side, a metal wiring layer such as an aluminum wiring layer can be formed to reduce resistance, which is advantageous for high-speed transfer.

〔Effect of the invention〕

The solid-state imaging device of the present invention has a structure in which the substrates are bonded together, and the transfer electrode is disposed in the 6-inch area between the substrate and the 1i-strong substrate, so large pixels are formed on the surface side of the substrate. can do. Therefore, the amount of signal charge increases and the sensitivity increases. Further, a bipolar transistor is formed in the pixel region, and this bipolar transistor is controlled by applying a base potential from the surface side, so that unnecessary charge can be swept out by electronic shutter operation, overflow control, etc. In addition, there is a thick

[Brief explanation of drawings]

FIG. 1 is a perspective view of a cross section of a main part of an example of a solid-state imaging device of the present invention, FIG. 2 is a cross-sectional view of a main part of the example along a plane perpendicular to the charge transfer direction, and FIG. FIG. 4 is an equivalent circuit diagram of each pixel in the above example, and FIG. 5 is a plan view of the main portion of the above example. Also,
FIGS. 6a to 6r are process cross-sectional perspective views showing an example of a manufacturing method for an example of the solid-state imaging device, and FIG. 7 is a main part sectional view showing an example of a conventional solid-state imaging device. . 2...Silicon substrate...Pixel region...High concentration impurity region...Silicon oxide film...Transfer electrode extraction portion...N-type well region 0...N-type well region 1. ...Buried channel layer 0...Bipolar transistor...Control electrode layer 0.31...Aluminum wiring layer 2.33...Transfer electrode 6...Interlayer insulating film 7...Polysilicon layer Patent application Person Sony Corporation Patent Attorney Akira Koike (and 2 others) Figure 2, Figure 3! ! I Fig. 5 Fig. 6 d Fig. 6 e Fig. 6+! Ic Figure 6f Figure 7

Claims (1)

[Claims] A substrate, a plurality of pixel areas formed on the front side of the substrate, a transfer electrode formed on the back side of the substrate and taken out between the pixel areas, and a reinforcing substrate bonded to the back side of the substrate. and a bipolar transistor whose emitter is a part of the pixel region, and a frame transfer type in which the base potential of the bipolar transistor is applied from the front surface side of the substrate to control the amount of charge accumulated in the pixel region. solid-state imaging device.