JPH0374422B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for processing correctable errors occurring in the memory section of an information processing device, and in particular to a process for classifying and counting information on errors occurring in the memory section. It is related to the method.

An error failure occurring in a memory section of an information processing device, ie, a main storage MS, a control storage CS, etc., has a large effect on the system, and sometimes the system goes out of control and becomes unusable.

Therefore, when an error occurs in the memory unit, it is necessary to grasp the error information in order to quickly make an accurate processing decision. Among errors, a 1-bit error in the memory section is a precursor to a system failure, so detection and processing thereof are important for ensuring reliability of the device.

[Conventional technology]

Various techniques have been implemented to detect and handle errors that occur in the memory section before they become a problem in the use of the device.

One such method is the patrol diagnosis method, which reads and checks the words stored in memory at regular intervals, corrects any errors, and stores them again at the original address, which is automatically repeated. Generally, the system monitors to make sure there are no abnormalities, and if a correctable (for example, 1-bit) error is detected, it is sent to the 1-bit error correction circuit, recorded, and the number of occurrences is counted in a counter. .

[Problem that the invention seeks to solve]

Looking at the occurrence of one-bit errors, for example, if the cause of the error is damage to a semiconductor recording element, errors will occur repeatedly in the same word. Also, a word whose configuration is related to the element, i.e.
Many errors occur in words that follow the error-generated word. In this case, it is naturally necessary to promptly replace the damaged memory element.

On the other hand, an error may occur due to a cause other than the above, such as electrical noise jumping into the signal circuit during writing to and reading from the memory, and in this case, it will not be detected again. It is normal not to have one.

Conventionally, the error situation was determined by looking at the count value of the error counter and, for example, parts were replaced immediately. That is, in the conventional method, there was a problem in that it was impossible to distinguish whether it was a temporary error or a fixed error that could not be recovered unless the error data was dumped and checked.

[Means for solving problems]

In order to solve the above problem, the present invention counts a 1-bit error using a plurality of counters when it is detected. For example, it is equipped with two counters that count the number of occurrences of fixed errors and soft errors, and the records are reflected in flag codes and displayed on a display.

In other words, when a 1-bit error is detected in a read/write operation (hereinafter referred to as read/write) of a single word in the memory section targeted for patrol diagnosis, such as the main storage MS or control storage CS, the error word A check is performed by reading/writing n consecutive words from the beginning.

If a 1-bit error is detected in the above read/write, the same word is read/written again and checked, and if an error still occurs, it is counted as a fixed error.

If a 1-bit error is detected after reading/writing and checking, read/write the same word again.
Write and check, and if no error occurs, it is counted as a soft error.

[Effect]

According to the 1-bit error detection method described above, errors detected during read/write are confirmed during read/write again, are classified into fixed errors and soft errors, and are counted separately in their respective counters. Since the word is checked, the situation in which the error has occurred becomes clear, and thus error processing can be performed accurately.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, 1 is a read/write control unit including an address counter 3 and a loop counter 4, and 2 is a patrol address register that stores a patrol address that is input thereto.

5 is the memory section monitored by patrol diagnosis,
6 is a word register in which a word read from the memory section is set.

7 is a 1-bit error detection/correction section, 8 is an error control section including a fixed error counter 9 and a soft error counter 10, a display section 11 and a log recording section 1.
2 displays and records the counted values of the fixed error counter and soft error counter.

Figure 2 is a flowchart of the method of this invention.
The operation of this system will be explained in detail with reference to this figure. However, FIG. 2 is an example in which patrol diagnosis of the main memory MS is performed.

First, patrol address (hereinafter address A)
) is fetched into the patrol address register 2 (step 1), the read/write control unit 1 fetches the memory unit 5 via the address counter 3.
The word at the address A specified by is called into the word register 6 (step 2).

Hereinafter, numbers in parentheses will be used for the status classifications in FIG.

The called word is detected by the 1-bit error detection unit 7.
checks (3). If no error is detected, 1 is added to the address counter 3 (4), and the process moves to the next step. If a 1-bit error is detected in this word, n consecutive bits starting from address A of this word
words are checked.

The loop counter 4 is set to n, the fixed error counter 9 to 0, and the soft error counter 10 to 0 (5).

Once corrected and stored at the original address, the word that caused the error is returned to the word register 6.
(6), 1-bit error detection/correction section 7
Checked by (7).

If no error is detected, 1 is added to the soft error counter 10 (8), and if an error is detected, 1 is added to the fixed error counter 9.
(9).

In either case, address counter 3 is incremented by 1 and becomes A+1, and loop counter 4 becomes 1.
is subtracted and becomes n-1 (10).

If the loop counter 10 is not 0 (11), address A+1 is called by the read/write control section 1 (12) and checked by the 1-bit error detection/correction section 7 (13).

It is called again (6) when an error is detected.
Checked (7). If no error is detected in step (13), each counter is reset (10), the value of the loop counter is checked (11), the word at address A+2 is called (12) and checked (13). .

As described above, (10), (11), (12), and (13) are repeated, and when the loop counter is 0, that is, when n words have been checked from the first word where an error occurred, error processing is performed. Logging processing and flag code creation are performed from section 8 (14), flag code display, that is, classified error display is performed on display display section 11 (15), and is recorded in log recording section 12, and the next processing is performed. to move to.

Although the above description has been made regarding the memory 1-bit error processing method of the control memory MS, it goes without saying that there is no problem in applying this method to the control memory CS as well.

Furthermore, each block in Figure 1 functions in a system consisting of local storage LS, control storage CS, main storage MS, registers, and others.

〔Effect of the invention〕

As explained above, according to the present invention, 1-bit errors that occur in the memory section are classified and recorded according to the error state, and are displayed, so that it is possible to quickly determine what to do with the error and take appropriate measures. be able to. For example, when a maintenance person is notified of error information, he or she can immediately decide on countermeasures and take necessary measures such as replacing the printed circuit board.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the memory 1-bit error processing method of the present invention, and FIG.
This is a flowchart of the figure. In the figure, 1 is a read/write control section, 5 is a memory section, 7 is a 1-bit error detection section, 8 is an error control section, 9 is a fixed error counter, 10 is a soft error counter, 11 is a display section, and 12 is a log record. Department.

Claims (1)

[Claims] 1. In an information processing device that performs patrol diagnosis of the memory section and corrects and writes when a correctable error is detected, the error detection section rechecks the word in which a correctable error has been detected and detects a correctable error again. When a correctable error is detected, it is counted in a first error counter, and when it is not detected, it is counted in a second error counter. A memory error processing method characterized in that the values of both the counters are displayed by performing the discrimination control.