JPS58115698A - Logging system for memory error - Google Patents

Abstract

PURPOSE:To log a fault of a memory element accurately even when a relatively small logging file is used by updating the contents of a counter area specified by a memory word address and an error bit number by a unit amount when an error of read data of a memory is detected. CONSTITUTION:A logging file 5 consists of plural counter areas A specified by rows and colums. Each column corresponds to each bit number of a word. Respective rows corresponds to numbers represented by bit parts having >=64K- bit weight of memory word addresses. As shown in a figure, a 22-bit word consists of 22 memory elements and when those memory elements have 64KX1-bit size, one counter area a corresponds to one emmory element. For example, data in a memory word address 200K is read out and an error in a bit #2 is detected, the contents of a counter area A in the 1st row and 2nd column of the logging file as shown by slanting lines are updated by a unit amount.

Description

Detailed Description of the Invention (1) Technical Field of the Invention The present invention provides a plurality of counter areas determined by the numerical value represented by the upper bits of a memory word address and the pit position of the word. This invention relates to a memory e-error logging method in which when an error is detected in read data, eight of the counter areas determined by the error bit number and memory word address are updated by a unit amount.

(2) Prior art and problems Figure 1 shows the system configuration of a memory error logging method.

2 is a central processing unit, 3 is an input/output device, 4 is an external storage, 5
indicates logging files, etc., respectively. When an error is detected in the main storage device 1, memory error information is stored in the logging file 5.

FIG. 2 shows the details of the main memory device l, where 6 is a memory element group, 7 is a data register, 8 is an ECC circuit, 9 is an error bit number register, and 10 is an address superior register t. It shows. The ECC circuit 8 has 1-bit error correction and 2-bit error detection functions. Error bit number register 9 contains error bit number register 9.
Bit number is set. In addition, the central execution outfit fIt1
is microprogram controlled.

FIG. 3 shows the arrangement of memory elements, where 11 is 6
It is a 4K x 1 bit memory element. As shown in FIG. 3, 22 memory elements 11 are arranged horizontally, and the same address information and control information are given to the 22 memory elements 11 belonging to one row. One word consists of 22 bits, bits 0 to 15 are pure data and bits 16 to 21 are check codes. In addition.

The 22 memory elements constituting one row are mounted on one card.

No. 41'N is the conventional memory machine 2-ler segging method Y
This is to explain. In the conventional memory error logging method, the memory address where the error occurred and the bit number indicating the bit position of the error are recorded as is.
Logging is performed in file 5. In this type of conventional method, when a burst error occurs (all addresses are corrupted instead of only a fixed address being corrupted), only the memory address of the faulty memory element is recorded due to logging file area constraints. The disadvantage is that a large number of memory elements are logged, and information about intermittent failures of other memory elements is lost.

(3) Object of the Invention The present invention is based on the above consideration, and an object thereof is to provide a memory error logging method that allows failure logging of all memory elements.

(4) Structure of the invention Therefore, the memory error logging method of the present invention provides error information logging that indicates the error location when an error is detected in data read from the main memory.
In the memory error logging method that is now stored in a file, the logging file is configured as a set of multiple counter areas that can be specified by each bit position of a word and each numerical value represented by the upper bit part of a memory word address. However, when an error is detected in the read data of the memory, six volumes of a counter area specified by the memory word address and error bit number are updated by a unit amount.

(5) Examples of the invention The present invention will be explained below with reference to the drawings.

FIG. 5 shows the structure of an embodiment of a logging file according to the present invention. The logging file 5 is composed of a plurality of color areas A specified by rows and columns. Each column corresponds to each bit number of the word. Also, each row has 64K (2) of memory word addresses.
It corresponds to each numerical position represented by a bit part having the above weight. As shown in FIG. 3, if a 22-bit word is made up of 22 memory elements, and each of these memory elements is 64K x 1 bit in size, one counter area A is It corresponds to one memory element. Now, for example, when reading data at memory word address 200, bit +2
If an error is detected in the logging file 5
The contents of the diagonally shaded counter area A in the first row and second column of are updated by a unit amount.

FIG. 6 shows the logging process in the present invention. In the main memory device I as shown in FIG. 2, at the time of memory access, a memory word number address is set in the address number register 10, and the memory element group 6 is accessed using the contents as an address. Read data is data
The contents of data register 7 are E.
It is checked by the CC circuit 8, and errors are detected and automatically corrected. At this time, if an error is detected, a machine check interrupt t is caused in the microprogram of the central processing unit 1, and an error correction bit number is stored in the error bit number register 9. The machine check interrupt processing routine of the microprogram performs the following processing.

■ Determine whether the machine check interrupt is due to a memory error. If Yes, perform the process (■).

■ Address information χ Read from address register 10, error bit number read from error bit number register 9.

■ After storing the address information and error bit number in the fixed area of the main memory, a soft level machine check interrupt t° is generated.

■ End machine check interrupt processing.

In the software level machine number check interrupt processing routine, processing such as manure is performed.

■'Determine whether the machine check interrupt is due to a memory error. If Yes, the process of ■I is performed.

, 2' Read address information and error bit number Z from the fixed area of the main memory.

■' Read the logging information of the corresponding T or counter area A from the address information and error bit number O ■' Update the logging information and write to the original counter area again.

■'/7) - Ends the machine life check interrupt processing at the -level.

If all memory elements have a 64K x 1 bit configuration, one counter area A in FIG.
Since this corresponds to C memory elements, by checking the contents of counter area A, it is possible to know in which C memory element faults are occurring most frequently. However, for example, the memory word address is 12 with address 0 to 64.
The 8KJ3 memory area consists of 22 64K x 1 bit memory elements, and the memory word address is the first one.
If the 256KB memory area having addresses 28 to 384 is composed of 22 memory elements of 128K x 1 bit, it is necessary to know the layout and the configuration of the printed board. FIG. 7 shows a configuration for knowing the configuration of the memory printed board, in which 12-1 to 12-8 indicate memory cards, and 13 indicates a status flag storage area. memory card 12
-1゜12-3.12-4.12-5 are 256 each
KB memory card, memory card 12-2
．． 12-6.12-7 is a 128KB memory card. 128KB memory card has 22 64KX
Consists of 1-bit memory element, 256KB
The memory card consists of 22 128K x 1 bit memory elements. Memory card 12 now
If -1 is given a memory word address from address 0 to address 64, then memory card 12-2 is given a memory word address from address 64 to address 192. The same applies hereafter. The memory card is provided with a status flag information generation mechanism that indicates capacity and whether it is currently used or served. When a memory card is inserted into a mounting rack, these status flag information are output from the mounting position. At the end of the IPL sequence in which nothing is output from the unmounted positions, the central processing unit 20i microprogram reads the status flag information output from each mounted position and sets it in the status flag storage area 13. The meaning of the status flags is shown in FIG. The monitor program that obtains execution rights after IPL1 reads the status flag storage area 13Y and stores it in the Elging area of the external storage device. During maintenance, the logging information analysis program analyzes the memory address information and error bit number that are logged as memory error failures, as well as the memory implementation status.
A faulty memory card and its memory element are determined and output to the outside.

(6) Effects of the Invention As is clear from the above description, according to the present invention, it is possible to accurately log memory element failures even when a relatively small logging file is used.

[Brief explanation of drawings]

Figure 1 shows the system configuration of a memory error logging system, Figure 2 shows the configuration of the main memory, Figure 3 shows the arrangement of memory elements, and Figure 4 shows the conventional memory error logging system.
Figure 5 is a diagram explaining the error logging method, Figure 5 is a diagram showing the configuration of one embodiment of the logging file according to the present invention, Figure 6 is a diagram explaining the logging process according to the present invention, and Figure 7 is a diagram showing the memory print. FIG. 8 is a diagram illustrating an example of a configuration for knowing the configuration of a board, and is a diagram illustrating the meaning of status flags. 1... Main storage device, 2... Central processing unit, 3...
Input/output device, 4...external storage, 5...logging/
File, 6...Memory element group, 7...Data register, 8...FCC circuit, 9...Error bit transfer error, 10...Address register, A...
・Counter Area・ Patent Applicant Nizak Electronic Industry Co., Ltd. Representative Patent Attorney Kyotani 4th Department 1 other person left ・1 drawing ・2 drawings, 4-shi 4121 Saizu Homme Kasuga 2 drawings

Claims (1)

[Claims] When an error is detected in data read from main memory, error information indicating the error location is stored in a logging file.In this memory error logging method, each bit position of a word and memory word address are stored in a logging file. The above logging file is configured as a set of multiple counter areas that can be determined by each numerical value represented by the upper bit part of A memory error logging method characterized by updating the contents of a counter area by a unit amount.