JPH04178748A - Controller - Google Patents

Abstract

PURPOSE:To allow error logging information, which is probably uncorrectable, to remain by preferentially logging double bit error in a logging register at the time of overflow of the logging register due to double bit error and single bit error. CONSTITUTION:When a logging address pointer 10 of double bit error and a logging address pointer 9 of single bit error coincide with each other, double bit error is preferentially logged, and logging of single bit error is stopped. Thus, logging information of double bit error are registered up to the number of logging registers 8 independently of the frequency in occurrence of single bit error though the total sum of frequencies in occurrence of single bit error and double bit error exceeds the number of logging registers 8 at the time of read operation of a memory part 1. Thus, logging information of double bit error which are more important than that of single bit error on prevention and maintenance of a memory system remain in logging registers 8 at its maximum.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for logging memory errors in a memory system having an error detection and correction function.

[Conventional technology]

As described in Japanese Patent Laid-Open No. 61-290556, conventional devices perform patrol diagnosis on faulty locations where errors have been logged and perform rewriting, etc.
There were drawbacks such as reduced memory system throughput.

[Problem to be solved by the invention]

When recording 1-bit errors and 2-bit errors using a limited number of logging registers,
When performing preventive maintenance, 2-bit errors are highly likely to become uncorrectable errors, so logging information for 2-bit errors is
1 is more important than bit and error logging information, and in a series of memory read operations, when the sum of 1-bit errors and 2-bit errors exceeds the number of logging registers, One object of the present invention is to log 2-bit errors with priority and leave error logging information that is highly likely to become uncorrectable.

[Means to solve the problem]

In order to achieve the above purpose, in a logging register with multiple addresses that logs 1-bit errors and 2-bit errors, an address pointer for logging 1-bit errors and an address pointer for logging 2-bit errors are dedicated respectively. When logging a 1-bit error, it is logged every time a 1-bit error occurs in the logging register from the upper address, and when logging a 2-bit error, 2-bit errors occur in the order from the lower address. I started logging every time I did it. Furthermore, when the logging address pointer for a 2-bit error and the logging address pointer for a 1-bit error match, logging is given priority to the 2-bit error, and logging for the 51-bit error is stopped. be.

[Effect]

In a series of memory read operations, even if many 1-bit errors and 2-bit errors occur and the sum of both exceeds the number of logging registers, 2-bit errors will occur regardless of the number of 1-bit errors. Since error logging information can be registered for the maximum number of logging registers, logging information for 2-bit errors, which is more important than logging information for 1-bit errors, can be left in the logging registers as much as possible for preventive maintenance of the memory system. can.

〔Example〕

An embodiment of the present invention is shown in FIGS. 1 and 2 below.

In the memory system shown in Figure 1, the data read from the address addressed by the memory address register 6 is checked by the error correcting circuit 2 for the presence of 1-bit errors and 2-bit errors. . In such a memory system, before executing a series of read operations, the 1-bit error shown in 13, 2
The error status register that stores whether a bit error or uncorrectable error has occurred, the 1-bit error pointer shown at 9, and the 2-bit error pointer shown at 10 are reset. By this reset operation, 1 shown in 9.
The bit error pointer is set to the highest address of the error logging register shown at 8, and the 2-bit error pointer is set to the lowest address of the error logging register shown at 8.

If a 1-bit error is detected in the error correcting circuit 2 for the data read from the memory section 1, the data in the address register 6 used when reading from the memory section is stored in the error logging register 8. , the syndrome pattern decoded by the second error correcting circuit is used as logging data for 9 1-bit errors.
At the same time as being written to the register indicated by the pointer, information indicating the occurrence of a 1-bit error is set in the 1-bit error bit of the 13 error status registers.

After that, the 1-bit error counter 9 is counted down by one address in preparation for the next occurrence of a 1-bit error.

When registering a 1-bit error in the logging register,
Comparators 12 compare the values of the 1-bit error pointer 9 and the 2-bit error pointer 14 in the backup register (the register that stores the last write address of the 2-bit error register), excluding the least significant 1 bit, and find a match. In this case, the 1-bit error will not be registered in the logging register, and the 1-bit error will not be logged thereafter until it is reset.

If a 2-bit error is detected in the data read from memory section 1, write the address to the memory section and the syndrome pattern of 2 bits each to the logging register of 8 at the same time, and then write the 2-bit error to the logging register of 8. Count down step by step. Also, at this time, the 2-bit error bit of the error status register 13 is set.

As a result of the above, the total number of 1-bit errors and 2-bit errors in a series of read operations from memory can be calculated by logging.
Even if a similar number of registers occurs.

2-bit error information is preferentially logged as many times as there are logging registers.

〔Effect of the invention〕

According to the present invention, logging information for 2-bit errors, which is more important for preventive maintenance of the memory system, is logged to the maximum extent on the error logging register with priority over 1-bit errors. Logging registers can be used more effectively than when separate registers are provided for exclusive use and for 2-bit errors.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a memory system according to an embodiment of the present invention, and FIG. 2 is a block diagram of a logging register section in FIG. 1. DESCRIPTION OF SYMBOLS 1... Memory section, 2... Error correcting circuit, 3... Memory read/write bus, 4... Correction code bus,
5...Address bus, 6...Address register, 7...Logging register section, 8...
...Logging register, 9...1 bit error pointer IO...2 bit error pointer, 11...Selector, 12...Comparator, 13 ...Error status register, 14
・・・・・・Backup plan l Diagram 2 Diagram

Claims (1)

[Claims] 1. In a memory system consisting of a 1-bit error correction circuit, a 2-bit error correction circuit, and multiple error logging registers, the order in which the logging registers are used when an error occurs is as follows: , are used in order from the upper address, and when a double bit error occurs, are used in order from the lower address, and when the logging register overflows due to a double bit error and a single bit error, priority is given to the double bit error, A control device characterized by logging to a logging register.