JPH0374054U

JPH0374054U -

Info

Publication number: JPH0374054U
Application number: JP13572589U
Authority: JP
Priority date: 1989-11-21
Filing date: 1989-11-21
Publication date: 1991-07-25

Description

[Brief explanation of drawings]

第１図はＤＲＡＭの制御信号を作り出すブロツ
ク図、第２図はダイナミツク・バス・サイジング
を行う回路のブロツク図、第３図はパリテイー検
査を行い、エラーの場合バスエラーをアサートす
る回路のブロツク図である。１〜４……ＤＦ／Ｆ、５……同期式カウンタ、
６……タイミング発生同期式ＰＡＬ１、８……バ
ス・サイジングを行う組合わせ論理のＰＡＬ２、
１７……バス・サイジングに対応したパリテイー
結果を集める組合わせ論理ＰＡＬ３、１９……バ
スエラー作成タイミングを作り出す同期式ＰＡＬ
４。 Figure 1 is a block diagram of a circuit that generates DRAM control signals, Figure 2 is a block diagram of a circuit that performs dynamic bus sizing, and Figure 3 is a block diagram of a circuit that performs a parity check and asserts a bus error in case of an error. It is. 1 to 4...DF/F, 5...Synchronous counter,
6... Timing generation synchronous PAL1, 8... Combinational logic PAL2 that performs bus sizing,
17...Combinational logic PAL3 that collects parity results corresponding to bus sizing, 19...Synchronous PAL that creates bus error creation timing
4.

Claims

[Scope of utility model registration request]

Dynamic RA used in CPU systems with a data bus consisting of multiple bytes
The M controller includes a dynamic RAM corresponding to each byte of the data bus, a parity check circuit that checks a parity bit corresponding to the contents of the dynamic RAM, and a dynamic bus that selects the bit width of the data bus in units of bytes. - A dynamic RAM control circuit comprising a sizing circuit, wherein the parity check circuit performs a parity check operation only on bytes selected by the dynamic bus sizing circuit.