JPH0373903B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an information processing apparatus having a diagnostic function, and more particularly to an information processing apparatus having a function of diagnosing an input device such as a key matrix or a display circuit. As microcomputers become more widespread, devices or devices dedicated to key input and display have been developed and are beginning to appear on the market in order to lighten the burden on microcomputers. Such an element (hereinafter referred to as a key and display element), for example, in a copying machine, transmits to the microcomputer which key on the key matrix has been pressed, and also receives data on the copy setting number and the number of copies. It is used for purposes such as converting this into display data and displaying it. KD elements usually use a microcomputer as a master, operate under the microcomputer, and cannot operate independently. Therefore, in order to diagnose whether or not the key matrix and display circuit are operating normally, it is necessary to transfer data between the master computer and the KD element. For this reason, on the master computer side, a program is required for the above-mentioned diagnosis, which has disadvantages in that it requires personnel and additional memory to create this program. Therefore, an object of the present invention is to eliminate the above-mentioned conventional drawbacks and provide an information processing device having a diagnostic function that can independently diagnose key input and display without using a master computer. do. In the present invention, the information processing unit that processes key input information or display information is provided with a diagnostic function to diagnose the key matrix and display circuit. Therefore, the present invention eliminates the need for data transfer between the master computer and the master computer for diagnosis, reduces the effort required to create a program, and provides excellent effects such as making the master computer smaller. Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In FIG. 1, 1 is a master CPU, which is connected to a key input and display control element 2 (hereinafter referred to as KD element) via a control signal line 1a and a data signal line 1b, and is used to signal display data, key input data, etc. The communication is carried out via this signal line. 3 is a decoder circuit that decodes the multiplexed signal. The decoder circuit 3 is provided to reduce the number of signal lines of the KD element 2, but is not particularly necessary when there is enough signal line of the KD element 2. A scan signal 3a is successively output from the KD element 2 at regular time intervals, and based on this signal, the key matrix 4 is dynamically scanned to determine which key has been operated, and the display driver circuit and display element 5 are It is dynamically driven to light up the display element. Key matrix 4 is
For example, in the case of a copying machine, keys are provided in association with each input key on the operation panel, such as a numeric keypad, a copy key, a stop key, and a paper feed switching key. The scan signal 3a inputted to the key matrix 4 passes through the key matrix 4, returns to the KD element 2 as a return signal 4a, and the KD element 2 makes a key input determination. On the other hand, the display driver circuit and display element 5 perform dynamic lighting of the display element based on the scan signal 3a and the display data 2a output from the KD element 2 in synchronization with the scan signal. Reference numeral 6 denotes a switch for inputting to the KD element 2 whether or not to perform key input and display diagnosis.When the switch 6 is operated, the KD element 2 independently performs key input and display diagnosis. The specific configuration of each circuit shown in Figure 1 is shown in the second section.
In the figure, reference numeral 10 denotes a KD element, which corresponds to element 2 in FIG. In this embodiment, this KD element is used, for example, in Intel's 1-chip microcomputer 8041A for peripheral device control.
The key input and display control functions are mainly realized by software. 8041A is 8
It is a 1-chip microcomputer that is capable of bit-parallel processing, and has 1K byte of RM, 64 bytes of RAM, 16 general-purpose I/ports, and 2 input terminals, and can be used as a slave computer for others. For convenience, it has two data bus buffers (abbreviated as DBB) for input and output. Furthermore, it has data bus signals and control signals for data transfer with the master CPU 1, and is designed to be easily connected to chips such as Intel's 8080A and 8085A.
For a detailed explanation of the 8041A, please refer to the user's manual published by Intel. XTAL is a crystal oscillation element, and capacitors C1 and C2
It is also connected to the oscillation terminals X1 and X2 of the KD element 10, and performs clock oscillation for the operating clock of the KD element 10 and the internal timer. DB0～
DB7 is the data input/output between master CPU1.
This is a bus signal. P24 is the master CPU1 for key input
The interrupt request signal line is used to notify the interrupt request signal line, and is turned on and off according to the contents of the internal DBBUT buffer by executing an enable flag (ENFLG) command inside the KD element 10. (Write signal), (Read signal), AO (Address signal),
CS (chip select signal) and (reset signal) are input terminals that receive control signals from the master CPU 1, respectively. Ports P20~P22 are scan signal outputs SL0~
It is assigned to SL2 and sequentially outputs numerical data signals of 0 to 7 at fixed time intervals determined by the oscillation frequency by XTAL and the set time of the internal timer of the KD element 10. The signals SL0 to SL2 are sent to a decoder circuit 11 (corresponding to 3 in FIG. 1) composed of 3→8 decoder elements of 74LS138, for example, and are converted into eight signals Y0 to Y7. This Y0～
The signal Y7 is connected to the inverter driver circuits 20 to 27 and the driver circuits 30 to 37, and serves as a signal for key scanning and dynamic lighting of the display element. Inverter driver circuit 20
The outputs of ~27 are connected to key switches 60~67, and key scan return signals RL0~
RL3 is input to the P23, P26, P27, and T1 terminals of the KD element 10 through pull-down resistors R1 to R3.
In this embodiment, RL0 to RL3 go high when the key switch is pressed. On the other hand, display data SD0 to SD7 are output from P10 to P17 of the KD element 10, and the driver circuits 40 to 47
The display elements 50 to 57 are driven through. In this embodiment, the driver circuits 30 to 37 to which the display element is connected are selected (in this embodiment, when Yn becomes low level), and the driver circuits 40 to 47 to which the display element is connected are selected. Selection (in this example, when SDn becomes high level)
When the display element 30a is turned on, the display element 30a lights up. The generation timing of each signal SL0 to SL2, Y0 to Y7, and SD0 to SD7 is illustrated in Figure 4, and the signal SL0
~SL2 becomes a waveform whose frequency is sequentially divided, and signals Y0 to Y7, which are sequentially dynamically scanned, are obtained. T0 to T7 indicate the selected time interval and constitute one scan cycle. In this embodiment, it is possible to scan a 4×8 key matrix, and it is also possible to drive and light six 7-segment LEDs and 22 LEDs. FIG. 3 is a diagram showing a specific arrangement of display elements 50-57, and blocks 50'-57' in the figure correspond to display element blocks 50-57 of FIG. 2, respectively. Blocks 50' to 55' are 7-segment LEDs V0 to V5 and individual LEDs (hereinafter referred to as 1 for distinction).
(referred to as segment LED) consists of G16 to G21,
Each segment a to g of the 7-segment LED V0 to V5 is divided into one segment by the signals SD0 to SD6.
LEDG16 to G21 are each driven and lit by a signal from SD7. The one-segment LEDG0 to G15 of blocks 56' and 57' are driven and lit by signals SD0 to SD7, respectively. The 7-segment LED and 1-segment LED can each be turned on or off independently, and all 7-segment LEDs V0 to V5,
Group A consisting of 1 segment LEDG0~G7,
Group B consisting of 1 segment LED G8 to G15,
Group C consisting of 1 segment LED G16 to G21
It is possible to independently clear (turn off) the four groups. The check switch SW in Fig. 2 is a diagnostic mode selection switch for key input and display, and corresponds to switch 6 in Fig. 1.
When the check switch SW is open, the system enters diagnostic mode, and when the check switch SW is closed, the system enters normal operation mode. The check switch SW signal is connected to the TO input terminal of the KD element 10,
By executing the internal commands JTO and JNTO of the KD element 10, the state of the TO terminal can be determined by software. Next, data exchange between the master CPU 1 and the KD element 10 will be explained. The master CPU 1 transfers data via the data bus signal lines DB0 to DB7 using the signals . This can be determined by software, so this is used for data exchange. From the KD element 10, (1) When the address signal AO = 0 (key input data reading mode) and DBB out is read, R is the data of RL0 to RL3, S is the data of Y0 to Y7, and "0,0 ,0,S,S,S,R,
Data of "R" is sent via signal lines DB0 to DB7. (2) Also, when the address signal AO = 1 (status word read mode) and DBB out is read, "X, X, X, F, S, IBF, OBF"
data is sent. However, F is the F1 flag, when S is "1", it is a specific key mode described later, when IBF is "1", the input buffer (DBB in) is full, and OBF is "1". indicates that the output buffer (DBB out) is full. On the other hand, from master CPU 1 to KD element 10, (3) 8 of "*0XCCCCC" when address signal AO = "0" (7 segment data set mode)
Sends bit data. However, if the "*" bit is "0", there is no blinking, and it is "1".
When , it is displayed with blinking, and C is a 7-segment character code (0 to 31). X
may be either "1" or "0". (4) Also, when address signal AO = “0” (1 segment data set mode), “*1XXXXXX”
Send the data. When the first "*" bit is "0", no blinking is displayed, "1"
, the blinking display will be displayed, and the last "*" will be displayed.
When the bit is "0", it is "off", and when it is "1", it is "on". X may be either "0" or "1". (5) Furthermore, when address signal AO = “1” (data address set mode), “1**AAAAAA”
data is sent. The value of A is a 7-segment data address (0-5) when the "**" bit is "00", a specific key code (0-31) when it is "01", and a specific key code (0-31) when it is "10". 1 segment data address (0 to 21), "11"
In this case, the specific key code is (0 to 31). (6) Also, when address signal AO = "1" (command set mode), data of "0XNSCBAV" is sent. N is a normal key mode (described later), S is a specific key mode selection, C is a bit that clears 1 segment group C, B is a bit that clears 1 segment group B, A is a bit that clears 1 segment group A, and V is a bit that clears 7 segments. It is active when the value is 1. Also, X is “0”,
Either "1" is fine. FIGS. 5a and 5b show the correspondence between the characters and codes displayed on the 7-segment LEDs V0 to V5. Next, the flow of control in the present invention will be explained with reference to the flowchart of FIG. The 64 bytes of RAM provided inside the KD device 10 implemented using the chip 8041A are allocated as shown in the table below.

【table】

[Table] First, in FIG. 6a, step SP1 is executed when a reset signal is input to the terminal of the KD element 10 to clear the RAM and perform various initial settings such as initial settings of the I/O port. Here, we also set the timer and enable timer interrupts. If a timer interrupt occurs, the interrupt processing program (step SP22 described later)
In order to set the timer, a timer interrupt is generated at regular intervals. Steps SP2 to SP15 in Figure 6 a to c form a loop, during which the 7-segment character code is converted to 7-segment data, data manipulation for blinking display, key input, and display self. Running some of the diagnostic programs. In step SP2, the content of the check switch SW is checked to determine whether to perform normal operation or perform diagnosis. When the check switch SW is on, IBF interrupts are disabled, a self-diagnosis mode is entered, and all data transfer data from the master CPU 1 is ignored. This prevents noise from entering the data bus and control signal lines and causing malfunctions when diagnosis is performed independently without using the master CPU 1. If the check switch SW is off, IBF
Interrupts are enabled and transfer data from the master CPU 1 can be accepted. At step SP3, the contents of the self-diagnosis mode of the RAM are checked, and if the self-diagnosis mode is a blank code, the process proceeds to step SP5, and otherwise, the process proceeds to step SP4. The self-diagnosis mode is a blink code of "8" or a code from 0 to 31, and when a key is pressed, the key code corresponding to the pressed key is stored in the self-diagnosis mode. While the key is being pressed, a display corresponding to the key code (see FIG. 5) is displayed on the 7-segment LED at step SP4. However, when the self-diagnosis mode is numerical data 31, that is, when it is a blank code, step SP5 is executed in order to switch to the mode for display checking. step
In SP5, the blinking character “8” is displayed on 7-segment LEDV0 to V5, and 1-segment LEDG0 to G21
Similarly, the display is blinked to check the display. Also, when no key is pressed and the mode is other than display check mode, the 7 segment LED V0~
A blinking character "8" is displayed on V5, and 1-segment LEDG0 to G21 are turned off, indicating that self-diagnosis is in progress. At the time of reset, the self-diagnosis mode is set to the display check mode by step SP1, and it is designed so that the keys can be checked after checking the display. By performing the above diagnosis, key input and display checking can be performed using the KD element 10 alone, making it easy to discover circuit failures and check operation. At step SP6, the value of the counter N for the loop processing at steps SP7 to SP11 is set to 0 for initialization. At step SP7, the character code data indicated by the counter N is converted into 7 segment bit data. However, Z is a working register. In step SP8, the character code is determined as the blink data, and it is further determined whether it is a blank section determined by the blink counter, and if it is a blank section, Z (character code data) is determined.
Set to 0. In step SP9, it is indicated by counter N.
The data of LEDG16 to G21 is set to the most significant bit (MSB) of Z, and processing for blinking display is similarly performed at step SP10. step
At SP11, Z is stored in the Nth display RAM, and steps SP7 to SP11 are repeated until N becomes 6. By executing steps SP6 to SP11,
Display data to be output to display blocks 50' to 55' in FIG. 3 is set. In steps SP12 to SP15, display data to be output to display blocks 56' and 57' in FIG. 3 is set. Step SP12 is the initial setting of the loop counter N. In step SP13, display data Z is set, in step SP14, processing for blinking display is performed in the same way, and in step SP15, Z is set.
is stored in the display RAM, and steps SP13 to SP15 are repeated until N becomes 2. By making the data conversion to the display RAM an interruptible processing program as described above, the number of interrupt processing programs can be reduced, and the processing time for data writing from the master CPU 1 can be shortened. Next, the timer interrupt processing routine will be explained with reference to FIGS. 6d to 6f. When a timer interrupt occurs in FIG. 6d, first, at step SP20, the register bank is switched to 1, and the contents of the accumulator ACC are saved. Next, in step SP21, display data signal lines SD0 to SD7 are cleared, signal lines SL0 to SL2 are set, and preparations are made for outputting the next display data signal lines SD0 to SD7. In step SP22, the display corresponds to the contents of the scan counter.
Outputs the contents of RAM to signal lines SD0 to SD7, sets the timer, and prepares for the next timer interrupt. Step SP24 is the key of steps SP24 to SP27.
Initialize counter R for checking. At step SP24, a return signal RLO is checked, and when RLO=1, it is assumed that a key has been pressed and the subroutine KEY-SR at step SP28 is executed. At step SP28, a value obtained by multiplying the contents of the scan counter by 4 is added to the counter R, and the result is stored in the key buffer. Therefore, the key buffer stores a binary number "000SSSRR" in which the leftmost 0 is the MSB and the rightmost R is the LSB. However, "SSS" is the content of the scan counter,
"RR" indicates the contents of counter R. The data stored in this way is used as the data of the pressed key. In step SP28, the contents of the key counter are further incremented by 1, and it is stored whether several keys have been pressed during one scan cycle. At step SP25, the contents of the counter R are incremented by 1, and the return signal RL1 is checked as in step SP24.
Check return signals RL2 and RL3. In step SP29, the contents of the scan counter are incremented by 1, and it is checked whether one scan cycle has been completed. If it has been completed, the process advances to step SP30.
If the interrupt processing does not end, the process advances to step SP38 and ends the interrupt processing. At step SP30, a scan counter is initialized, and the contents of the blink counter for measuring the blink period of blinking are incremented by 1. Subsequently, in steps SP31 to SP37, a key input is determined, and it is determined that a key input has been made only when all of the following conditions are met. (1) When only one key is pressed. (2) When a key is pressed and the same key is pressed for at least three scan cycles. Furthermore, when the same key is pressed for a long time, only the first key input determination is made valid, so that the master CPU 1 is not interrupted by multiple consecutive inputs of the same key. In step SP31, the contents of the key counter are judged and if there is no key input, the key data = “8”.
The blink code is set so that the blink character "8" is displayed when no key is pressed during self-diagnosis. It is also used to prevent the next key input from being accepted until all keys have been released, in order to prevent continuous interrupts to the master CPU due to the same key input described above. Next, proceed to step SP32 and the key counter will be 1.
Determine whether If key/counter = 1, step to increment key/match/counter by 1.
Proceed to SP33. At step SP33, the contents of the key/coincidence/counter are checked to determine whether the same key has been pressed three times in succession. If it is determined that the same key has been pressed three times, the process advances to step SP34 and the contents of the key buffer and key data are compared, and if it is determined that the same key has been pressed continuously, the key data is Ignore the contents of the buffer and proceed to step SP37. If not, the key data = key buffer and the process advances to step SP35. At step SP35, check the check SW.
When the check switch SW is on, self-diagnosis mode = key data. When the check switch is off, the process advances to step SP36, and if the key data is in a specific key mode, it is determined whether the key data=specific key code. If the judgment result is YES, DBBUT the contents of the key data.
and sends a key input interrupt request to master CPU1. After the KD element 10 executes the enable flag instruction, data is written to the output data bus buffer (DBBUT), and an interrupt request signal P24 to the master CPU is set by the hardware. Similarly, when master CPU1 reads DBBUT, hardware signal P24 is reset. Step SP37 is a step for initializing the key/coincidence/counter and the key/counter. Step SP38 is a step for terminating the interrupt processing, in which the accumulator ACC is restored and the RETR instruction is executed to set the register bank to 0, and the program returns to the normal program processing routine at the time of the interrupt. Next, the IBF interrupt processing routine will be explained with reference to FIGS. 6g to 6i. IBF interrupt is from master CPU1 to KD element 10
This is an external interrupt that occurs when data is written to the input data bus buffer (DBBIN), and as mentioned above, IBF interrupts are disabled during self-diagnosis. If an IBF interrupt occurs, step
Switch the register bank to 1 with SP40 and save the contents of the accumulator ACC. Next step
Read the contents of DBBIN with SP41. Step according to the contents D of DBBIN and the contents of address signal AO
Branches to each processing routine at SP42, SP43, and SP44. Step if D is character data
Proceeding to SP45, D is stored in the character code data RAM indicated by the character data address. Next, the content of the character data address is incremented by 1, and the process advances to step SP46. Step SP46
Then, it is determined whether the content of the character data address is 7, and if it is 7, the character data address is set to 0. By doing this,
When writing character data to the KD element 10 continuously, the 7-segment LED V0→V1→
Character data written as V2→V3→…→V7→V0→… are displayed one after another. When writing character data skipping from V0 to V4, an address command for setting a character code address can be written to the KD element 10. As described above, this embodiment is designed to facilitate data writing for display. On the other hand, if D is 1 segment data, steps SP47 and SP48 are similarly executed to set 1 segment data and 1 segment data address. At step SP49, it is determined whether D is specific key code data, and if YES, it is stored in the specific key code. By doing this, a specific key can be arbitrarily designated by software, making it versatile in use. In this embodiment, there is one specific key code, but this embodiment is not limited to this. The number of specific key codes can be easily increased by programming. At step SP50, D is determined and stored in the character code data address or one segment data address. If D is command data, execute steps SP51 to SP56 and
Each process is performed according to the contents of the . Steps SP51 to SP54 determine the clear bits of the 7-segment character groups A, B, and C, and if the bits are on, perform data manipulation to clear the display data of each group. In steps SP55 and SP56, it is determined whether the specific key mode is specified or canceled, and the specific key mode flag is set or reset. As is clear from the above description, the present invention includes a master computer that controls image information processing and a slave computer that controls key input means and display means, and when no diagnostic command is input, normal operation is performed. mode, the slave computer outputs information indicating that a key input has been made to the master computer in response to data input from the key input means, operates the display means based on the data from the master computer, and performs diagnosis. When a command is input, the system enters a diagnostic mode, and the display means performs different display operations depending on the type of data received from the key input means, with data transmission and reception with the master computer prohibited. Therefore, failure checks on the key input means and display means can be performed only by the slave computer, and in the normal operation mode, the master computer does not need to constantly monitor the key input means, reducing the burden on the master computer. In the diagnosis mode, the slave computer can perform diagnosis in response to key inputs independently of the master computer, and the master computer can perform other processing. Furthermore, during the diagnosis mode, the slave computer is prohibited from transmitting or receiving data with the master computer, so accurate diagnosis can be made by using data from the master computer or noise in the data bus or control signal line. This has excellent effects such as being able to prevent operations from becoming impossible.

[Brief explanation of drawings]

Each figure is for explaining an embodiment of the present invention, and FIG. 1 is a block configuration diagram showing the configuration of a control section centering on key input and display control elements, and FIG.
The figure is a more detailed block diagram of Figure 1, Figure 3 is a block diagram showing the configuration of the display element, Figure 4 is a timing chart of signals for dynamic driving, and Figures 5a and 5b are character codes. and FIGS. 6A to 6I are flowcharts showing the flow of control. 1... Master CPU, 2, 10... Key input and display control element, 3, 11... Decoder, 4...
Key matrix, 5...Display driver circuit and display element, 6...Check switch, 30-3
7, 40-47...driver circuit, 50-57...
...Display element.

Claims (1)

[Scope of Claims] 1. Key input means for generating data related to image processing conditions; Display means for displaying data related to image processing conditions; and Data for controlling image processing operations and operating the display means. a master computer for outputting an output, and a diagnostic command input means for inputting a diagnostic command for checking a failure of at least one of the key input means and the display means, the diagnostic command input means being connected to the master computer, If no diagnostic command is entered,
enters a normal operation mode, outputs information indicating that a key input has been made to the master computer in response to data input from the key input means, and operates the display means based on the data from the master computer; , when a diagnostic command is input from the diagnostic command input means, the system enters a diagnostic mode and prohibits data transmission and reception with the master computer;
An information processing apparatus having a diagnostic function, comprising a slave computer that causes the display means to perform different display operations depending on the type of data input from the key input means.