JPH0371668B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronous detection device that introduces a signal under test (input signal) and a specific reference signal and detects only the component of the signal under test that is in phase with the reference signal.

FIG. 1 is a block diagram showing a conventionally known synchronous detection device, and FIG. 2 is a vector diagram showing each voltage shown in FIG. 1. Now, if the switch SW shown in Fig. 1 is turned upward (to the E ₁ side), the input voltage E ₁ is applied to the synchronous detector 2, and the phase shift amount of the phase shifter 4 is set to zero, Fig. 2 A Bertol diagram as shown in is obtained. In other words, there is a constant phase difference θ between the reference voltage Eref and the input voltage _E1 .
exists at the output terminal 6 of the synchronous detector 2.
"a" volts, which is the in-phase component with Eref, is obtained.
Further, by setting the phase shift amount of the phase shifter 4 to 90 degrees, a quadrature component "b" volt can be obtained. Similarly, "c" and "d" volts are obtained for the input voltage _E2 . And the above information “a” and “b”
The vector voltage ratio of the two input voltages E ₁ and E ₂ is calculated from "c" and "d" (by the built-in microprocessor). Figure 3 shows the phase shifter 4 shown in Figure 1. 2 is a voltage waveform diagram for explaining the operation of the synchronous detector 2. FIG. The illustrated signal A corresponds to the voltage _E1 , and the signal B indicates the phase shifter output signal when the phase shift amount of the phase shifter 4 is set to zero. As explained in Fig. 2, there is a phase difference of ±
Suppose that θ has occurred. And the switch SW is E ₁
When the device is tilted to the side, the synchronous detector 2 sends out a detection signal C. Applying this to the vector diagram shown in Figure 2, the phase shifter output signal B corresponds to the reference voltage Eref, and the detection signal C corresponds to the reference voltage.
Corresponds to point a (a volt) of Eref.

When the phase shift amount of the phase shifter 4 is set to π/2, a phase shifter output signal d is obtained. The synchronous detector 2 into which the signal A and the phase shifter output signal D are introduced sends out a detected signal E. Applying this to the vector diagram shown in Figure 2, the phase shifter output signal D corresponds to the quadrature reference voltage E _Y , and the detection signal E corresponds to point b (b volts) of the quadrature reference voltage E _Y. do. The vector E 2 shown in FIG. ₂ can be considered in the same way.

The phase difference θ mentioned above (see Figures 2 and 3) is
Ideally, it should be zero. However, as long as the value θ remains unchanged, it is possible to correct it by calculation. However, the problem lies in whether the phase shift amount of the phase shifter 4 is exactly 90 degrees. In other words, in Figure 2, Eref and
If E _Y does not have a phase difference of exactly 90°, the correction calculations in the subsequent stage will be meaningless. In this way, the accuracy of the phase of the reference signal Eref (or _EY ) introduced into the synchronous detector 2 determines the accuracy of the entire synchronous detector. Therefore, reference signal generation circuits based on various analog methods or digital methods have been devised and used in practice. But the reference signal Eref and the input signal E ₁
There is still no known method for accurately setting the phase shift amount to 90° (or 45°, 180°, etc.) while keeping the phase difference θ constant.

Therefore, an object of the present invention is to make it possible to accurately control the amount of phase shift of the reference signal while keeping the phase difference between the signal under test (input signal) introduced into a synchronous detector and the reference signal constant. The purpose of this invention is to provide a synchronous detection device.

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 4 is a block diagram showing an embodiment of a synchronous detection device constructed based on the first invention of the present application. Further, FIG. 5 is a time chart for explaining the operation of FIG. 4. In Fig. 4, input signals E ₁ and E ₂ are selectively input to input switch 1.
One end of 0 is connected to the voltage comparator 12 and the synchronous detector 14. The output terminal of the comparator 12 is a D-type flip-flop (hereinafter referred to as F/F) 1
Connected to the 6 CK terminal. In addition, the above F/F16
The D terminal of is always held at logic level "1". The Q ₁ output terminal of the F/F 16 is connected to the shift/load terminal (indicated by S/L) of the first shift register 18 (for example, Texas Instruments SN74LS165 parallel load 8-bit shift register). be done. A clock signal 30 having a frequency 8f that is eight times the frequency f of the input signal elements E ₁ and E ₂ is applied to the clock terminal CK1 of the first shift register 18 (hereinafter referred to as the first SR). Also, each bit A, B, C of the 1st SR18,
D, E, F, G, H have 0, 0, 0, respectively.
0, 1, 1, 1, 1 are stored in advance. No.
The output terminal QH1 of the 1SR 18 is connected to the serial in terminal (indicated as S/I) of the 1SR 18 and the CK terminal of the D-type F/F 20. Said F/F
The D terminal of No. 20 is always held at logic level "1". The clear terminals CL ₁ and CL ₂ of F/F16 and F/F20 will be shown later. A signal (described in FIG. 5) is applied. F/F20
The _Q2 output terminal is connected to the shift/load terminal S/L of the second SR22. Clock terminal of SR22
A signal having an opposite phase to the clock signal applied to the CK1 terminal of the first SR 18 is applied to CK2 (because the inverter 24 is connected). Also the first
The contents stored in each bit A to H of the 2SR 22 are controlled by the controller 24 as necessary (details will be described in FIG. 5). The output terminal QH2 of the second SR22 is the serial in terminal S/
I and the synchronous detector 14.

According to this embodiment, the phase difference between the input signal 26 introduced into the synchronous detector 14 and the reference signal 28 (output signal of the second SR 22) is accurately set to θ or θ+90°. The reason for this will be explained below using FIG.

The input signal 26 (frequency f) is applied to the comparator 12 only for a short time (although it is of course also possible to apply the input signal 26 continuously). Then, the comparator 12 outputs the output signal 2.
9 is obtained (see Figure 5e). Note that there is no particular phase relationship between the comparator output signal 29 and the clock signal 30 applied to the CK1 terminal of the first SR 18 (see FIGS. 5a and 5c). Also F/F
Since a high level signal is previously applied to the clear terminal CL ₁ of F/F 16 (see FIG. 5b), an output signal 32 is obtained from the F/F 16 in response to the comparator output signal 29 (see FIG. (see figure d). Then, the first SR18 starts shifting and the output terminal QH1
1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, in response to the clock signal (frequency 8f).
1... is periodically generated (see FIG. 5e). Here, the repetition period of the output signal (QH1) is equal to the repetition period of the input signal 26 (frequency f). Even after the input signal 26 (and therefore the comparator output signal 29) disappears, the phase information of the input signal 26 will be retained by the output signal (QH ₁ 1; see FIG. 5e). . Then, a high level signal 34 is generated at the _Q2 terminal of the F/F 20 (see Figure 5g).
2nd SR shift begins. Now, each bit A to H of the second SR22 has A=0, B=0, C=0, D.
If the signals 0, E=1, F=1, G=1, H=1 are stored by the controller 24, then in response to the clock signal 30 applied to the CK2 terminal, the signals shown in FIG. A reference signal 28 as shown in FIG. The reference signal 28 has a phase lag of θ with respect to the comparator output signal 29 (see FIGS. 5c and 5i). Thus, a phase difference of θ exists between the input signal 26 introduced into the synchronous detector 14 and the reference signal 28 (see FIG. 2). Next, if you want to phase shift the reference signal 28 by 90 degrees, use the controller 24 to shift the phase of the reference signal 28 by 90 degrees.
It is only necessary to change the signals stored in each bit of the 2SR22. That is, A=0, B=0, C=
1, D=1, E=1, F=1, G=0, H=0 (see FIG. 5j). As a result, in response to the clock signal 30, the reference signal 28' of 0, 0, 1, 1, 1, 0, 0 is output from the QH2 output terminal.
is obtained (see Figure 5j). Such reference signal 2
8' has a phase delay of 90° compared to the reference signal 28 (see FIGS. 5i and 5j). The reference signal 28
Applying 28' and 28' to Figure 2, we get
The reference signal 28 corresponds to Eref, and the reference signal 28' corresponds to
This corresponds to E _Y. Similarly, the reference signal 28
If you want to advance the phase by 45 degrees with respect to
As shown, A=1, B=0, C=0, D=
1, E=0, F=1, G=1, and H=1. In this example, the minimum unit of phase shift amount is
It is 45°. This is because the frequency 8f of the clock signal 30 is selected to be eight times the frequency f of the input signal 26. Therefore, if the minimum phase shift amount is 10 degrees, the clock signal 30 should be selected so that the frequency difference is 36 times. Note that in this embodiment, the 8-bit first SR18
The reason for using the second SR22 is that the clock signal 3
0 and the input signal 26 is 8:1. Further, as described above, according to this embodiment, by applying the signal under test (input signal 26) for a short period of time, it is possible to continuously output the reference signal 28 thereafter.

FIG. 6 is a block diagram showing an embodiment of a synchronous detection device constructed based on the second invention of the present application. Further, FIG. 7 is a time chart for explaining the operation of FIG. 6. In FIG. 6, one end of an input switch 40 for selectively introducing input signals E ₁ and E ₂ is connected to a voltage comparator 42 and a synchronous detector 44 . The output terminal of the comparator 42 is connected to the CK terminal of the D-type F/F 46.
Note that the D terminal of the F/F 46 is always held at logic level "1". A high level signal is previously applied to the clear terminal _CL1 of the F/F 46 (see FIG. 7b). The output terminal _Q1 of the F/F 46 is connected to the shift/load terminal S/L of a shift register 48 (eg, Texas Instruments SN74LS165 parallel load 8-bit shift register). A clock signal 50 having a frequency 8f which is eight times the frequency f of the input signals E ₁ and E ₂ is applied to the clock terminal CK1 of the shift register (hereinafter referred to as SR) 48. The clock signal 50 is a JK type F/F.
54 and the clock terminal CK of the D type F/F 56. In addition, the clock terminal CK2 of the JK type F/F 52 is connected to a control signal 72 (FIG. 7f), which will be described later.
reference) is applied. The K terminals of F/Fs 52 and 54 are always held at logic level "0". The Q ₂ terminal of F/F52 is connected to the J terminal of F/F54, and the Q ₃ terminal of F/F54 is connected to F/F56.
Connected to the D ₄ terminal. _The Q4 terminal of F/F56 is connected to the clear terminal CL of F/F52 and F/F54. The clear terminal CL of the F/F 56 is always held at logic level "1". The F/Fs 52, 54, and 56 described above collectively constitute a "shift inhibit pulse generation circuit" 60 (indicated by a broken line). And the _Q4 terminal of F/F56 is
Connected to shift inhibit terminal INH of SR48. S.R.
The QH output terminal of 48 is connected to the serial in terminal S/I of the SR 48 and the synchronous detector 44.
A=1 in front of each bit (A to H) of SR48,
B=0, C=0, D=0, E=1, F=1, G=
1, H=1 is stored.

Also in this embodiment, the phase difference between the input signal 62 introduced into the synchronous detector 44 and the reference signal 64 (output signal of the SR 48) is accurately set to θ or θ+90°. The reason for this will be explained below using FIG.

Input signal 62 is applied to comparator 42, resulting in a comparator output signal 66 (see Figure 7c). There is no particular phase relationship between this comparator output signal 66 and the clock signal 50 (see FIGS. 7a and 7c). Since a high level signal is previously applied to the clear terminal CL ₁ of the F/F 46 (see FIG. 7b), a shift control signal is applied from the Q ₁ terminal of the F/F 46 in response to the comparator output signal 66. 68 is emitted (see Figure 7d). At this time, since a low level signal is applied to the shift inhibit terminal INH of SR48,
SR48 starts shifting. Therefore, the output terminal EQH of SR48 outputs 1, 1, 1, 1, 0, 0, 0, in response to the clock signal 50 (frequency 8f).
A reference signal 64 of 0... is obtained (see FIG. 7e). The reference signal 64 has a phase delay of θ with respect to the comparator output signal 66 (see FIGS. 7c and 7e). Thus, a phase difference θ exists between the input signal 62 introduced into the synchronous detector 44 and the reference signal 64 (see FIG. 2).

Next, the operation of the shift inhibition pulse generation circuit 60 will be explained. When the shift prohibition pulse 70 is emitted from the circuit 60 (see FIG. 7i),
SR48 is for stopping the shift operation.
That is, when a shift inhibit pulse 70 as shown in FIG.
Since the clocks (hatched in FIG. 7a) are ignored, a reference signal 64' delayed by one clock from the output signal QH is obtained (see FIG. 7h). As a result, the reference signal 64' is delayed in phase by exactly 45° (see FIGS. 7e and 7h).
Therefore, if it is desired to obtain a reference signal whose phase is delayed by 90 degrees, it is sufficient to generate the shift inhibit pulse again after that. In this embodiment, the minimum phase shift amount is 45° because the clock signal is 50°.
This is because the frequency 8f of the input signal 62 is eight times the frequency f of the input signal 62. Note that the shift prohibition pulse generation circuit 60 shown in FIG. 6 consists of two JK type F/Fs.
52, 54 and one D-type F/F 56;
It is possible to adopt any circuit configuration as long as it is a circuit that generates the shift inhibit pulse 70 at an arbitrary time within the range shown in (-).
In this embodiment, in response to the control signal 72 (see FIG. 7 f) applied to the CK2 terminal of the F/F 52, a high level signal is generated in the F/F 52 (see FIG. 7 g), As a result, F/F54
The _Q3 output terminal is set to a high level (Fig. 7h), thereby generating a shift inhibit pulse 70 (see Fig. 7i). The reason why 8-bit SR48 is used in this embodiment is that the clock signal 5
This is because the frequency ratio between 0 and the input signal 62 is 8:1.

As described in detail above, according to the present invention, it is possible to accurately phase shift the reference signal using the clock period as the minimum phase shift amount, and to keep the phase difference θ between the reference signal and the signal under test (input signal) constant. This is achieved using digital technology, so
A synchronous detection wave device with improved stability over time is realized.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a conventionally known synchronous detection wave device, Fig. 2 is a vector diagram showing each voltage shown in Fig. 1, and Fig. 3 is a diagram showing the voltages shown in Fig. 1. A voltage waveform diagram for explaining the operation of the phase shifter 4 and the synchronous detector 2, FIG. 4 is the first voltage waveform diagram according to the present application.
FIG. 5 is a block diagram showing an embodiment of a synchronous detection device constructed based on the invention of FIG. 4, and FIG. 6 is a time chart for explaining the operation of FIG. 4. FIG. 7 is a block diagram showing an embodiment of a synchronous detection device constructed based on the above-described method, and FIG. 7 is a time chart for explaining the operation of FIG. 6. 12: Comparator, 14: Synchronous detector, 1
8, 22: Shift register register, 24: Controller, 28: Reference signal, 42: Comparator, 4
4: Synchronous detector, 48: Shift register, 6
0: Shift prohibition pulse generation circuit, 64: Reference signal.

Claims (1)

[Claims] 1. Start shifting in synchronization with the signal under test 62,
By sequentially shifting data in response to clock signal 50, having a number of bits associated with a predetermined minimum variable phase amount, and initializing each bit to a predetermined value, a reference having the same frequency as the signal under test is obtained. Circulating shift register 48 generating signal 64
and a synchronous detector 44 which introduces the reference signal and the signal under test and generates a detection signal, the clock being detected by applying a control signal to the cyclic shift register. A synchronous detection device characterized in that the phase difference between the reference signal and the signal under test is set to a predetermined value by interrupting a shift operation of one clock of the signal.