JPH0371357A - Data transfer system - Google Patents

Abstract

PURPOSE:To store data into a duplex external storage device without lowering the processing capacity of an information processor by providing a parallel transfer means to transmit in parallel the data sent from a direct memory access (DMA) controller to an external storage device. CONSTITUTION:When an information processor is set in a prescribed mode by a mode setting means 400, a synchronizing means 500 monitors the data transfer requesting signals outputted from the external storage devices 200-1 and 200-2 and transmits a these requesting signals to a DMA controller 300 after confirming the output of both requesting signals. A parallel transfer means 600 transmits the data received from the controller 300 to both storage devices 200-1 and 200-2 in parallel to each other. Thus the data are simultaneously transferred to a duplex external storage device. Consequently, a period during which the information processor halts its process is halved in comparison with a case where the data are transferred both external storage devices separately from each other. Then the lowering of the processing capacity is reduced for the information processor.

Description

[Detailed Description of the Invention] [Summary] Regarding a data transfer method in an information processing device equipped with a direct memory access control device that stores the storage contents of a main storage device in a duplicated external storage device, the processing capacity of the information processing device is improved. The mode setting means sets the information processing apparatus to a predetermined mode, and the mode setting means sets the information processing apparatus to a predetermined mode, with the aim of storing data in a duplicated external storage device with as little deterioration as possible. mode, the data transfer request signal output from each external storage device is monitored, and after confirming that both data transfer request signals have been output from each external storage device, the direct memory access control device synchronization means for transmitting a data transfer request signal; and parallel transfer means for transmitting data transferred by the direct memory access control device to both external storage devices in parallel when the mode setting means sets the information processing device to a predetermined mode. The system is configured to provide the following.

[Industrial application field]

The present invention relates to an information processing device, and more particularly to a data transfer method in an information processing device equipped with a direct memory access control device that stores the storage contents of a main memory device in a duplicated external storage device.

For example, in information processing equipment such as electronic exchanges that require high reliability, not only the central control unit and main memory devices are duplicated, but also the external storage devices are duplicated, and the contents of the main memory device are transferred to each external memory. It may be stored in the device.

[Prior Art] FIG. 5 is a diagram showing an example of an information processing device to which the present invention is applied, FIG. 6 is a diagram showing an example of the peripheral bus control device in FIG. 5, and FIG. 7 is a diagram showing an example of the peripheral bus control device in FIG. FIG. 8 is a diagram showing an example of a conventional selector, and FIG. 8 is a diagram showing an example of a conventional data transfer process.

In FIG. 5, a central controller (CC) 2, which is the center of various controls, a main memory (MM) 3, which stores programs and data necessary for the operation of the central controller (CC) 2, and a central controller, respectively. (CC) 2 and a main memory (MM) 3, a processor bus 4, a peripheral bus controller (PBC) 5, and multiple input/output controllers (IOC) 7.
An information processing device 1 comprising a file memory (FM) 8 and a file memory (FM) 8 is provided in duplicate. In addition, each information processing device 1 etc. will be referred to as "0 system" and "1 system", respectively.
Represented as l-O and 1-1, respectively.

Each peripheral bus controller (PBC) 5 is connected to a central controller (CC) 2 and a main memory (MM) 3 via a processor bus 4, and is connected to each input/output controller (MM) via a peripheral bus 6. The central control unit (
Controls data transfer between the central control unit (CC) 2 and various input/output devices such as file memory (FM) 8 connected to each input/output control unit (IOC) 7 under the control of the CC) 2. As illustrated in FIG. 6, each address decoder (ADC) 51 and direct memory access control unit
DMC) 52, interrupt control unit (IRC) 53, mode register (MR) 54, and two sets of selectors (SEL) 55
and 56.

Usually, one of the information processing devices 1 is used as the active system and the other as the standby system, and furthermore, the central controller (CG) 2 and the peripheral bus controller (PBC) 5 of the active system are connected to the human output control device ( IOC) 7 (hereinafter referred to as non-separated mode), and when the active central controller (CC) 2 and peripheral bus controller (PBC) 5 control the active input/output controller (
10C) 7, and a standby human output control device (I
The OC) 7 is divided into a case where it is controlled by a standby central control unit (CC) 2 and a peripheral bus control unit (PBC) 5 (hereinafter referred to as a separate mode).

For example, when operating the 0-system information processing device 1-0 as the active system and the I-system information processing device 1-1 as the backup system, and operating in non-separate mode, the central control unit (CC) 2-0 is connected to the processor bus. The separation mode signal sep stored in the mode register (MR) 54-0 in the peripheral bus controller (PBC) 5-0 via the peripheral bus controller (PBC) 4-0 is set to logic "O", and the 0-system peripheral bus controller (PBC) The active mode signal act supplied to the PBC 5-0 is set to logic III, and the active mode signal act supplied to the 1-system peripheral bus controller (PBC) 5-1 is set to logic 0''.

In such a case, the selector (SEL) 55-0 in the peripheral bus controller (PBC) 5-0 selects the output line of the address decoder (ADC) 51-0 and connects it to the peripheral bus 6-0. In addition, the selector (SEL) 55-■ in the peripheral bus control device (PBC) 5-1 is an address decoder (AD
C) Select the outgoing line 51-0 and connect it to the peripheral bus 6-1 via the confounding signal line 9.

In addition, the selector (
SEL) 56-0, the active mode signal act
(logic “l”) and separation mode signal 5ep (logic “0”)
) is input to the gate 561-0, so the gate 562-
0 and 564-0 are in a conductive state, gates 563-0 and 565-0 are in a cut-off state, and each terminal A CK o of the direct memory access control unit (DMC) 52-0 is turned on.
, . . . and DST are connected to the peripheral bus 6-0, and the selector (SE
L) In 56-1, the active mode signal act (logic "0") and the separation mode signal 5ep (logic "0")
is input to gate 561-1, so gate 563-0
and 565-0 are in a conductive state, data 1-562-0 and 564-0 are in a cut-off state, and each terminal MA CK,
, -, and DST are connected to peripheral bus 6-1 via confounding signal line 9.

In this state, the central controller (CC) 2-0 transfers the storage contents of the main memory (MM) 3-0 to the file memory (FM).
8-0 and 8-1, first the address decoder (ADC) 51-0 is sent via the processor bus 4-0.
If you set the address of the input/output control unit (IOC) 7-00 to which the file memory (FM) 8-0 is connected to,
The address decoder (ADC) 51-0 is a selector (SE
L) 55-0 and the peripheral bus 6-0 to the human output control unit (IOC) 7-00.

The input/output controller (IOC) 7-0.0 selects the peripheral bus controller (PBC) from the central controller (CC) 2-0 by receiving the selection signal transmitted from the address decoder (ADC) 51-0. ) 5-0 and the peripheral bus 6-0 are stored in the internal register (time tIo in FIG. 8), the write state is set, and the peripheral bus 6-0 and the selector (SEL) A data transfer request signal req is sent to the terminal RQ of the direct memory access control unit (DMC) 52-0 via the direct memory access control unit (DMC) 56-0. (time t2° in Fig. 8).

The direct memory access control unit (DMC) 52-0, which has received the data transfer request signal reqoo, accesses the main memory (M
M) After making preparations for data transfer from IOC 3-0 to input/output controller (IOC) 7-00, transmit an operation stop request to central controller (CC) 2-0 via processor bus 4, and ACK, to selector (SEL) 56
-0 and peripheral bus 6-0 via the input/output control device (I
OC) Response signal ack at 7-00. (8th
Figure time tso).

Response signal acko. The human output control device (IOC) that received the
) 7-00 is the peripheral bus 6-0 and the selector (SEL
) 56-0 to the direct memory access control unit (
DMC) 52-0 data transfer request signal r
Sending out eqoo is stopped (time t4° in FIG. 8).

Thereafter, the direct memory access control unit (DMC) 52-
0 is a direct memory access format, in which data is extracted from the main memory (MM) 3-0 via the processor bus 4-0, and data is extracted from the input/output control device (IO) via the peripheral bus 6-0.
C) A data strobe indicating the storage timing of the transferred data is transmitted from the terminal DST to the input/output control unit (IOC) 7-00 via the selector (SEL) 56-0 and the peripheral bus 6-0. A signal aSt is transmitted (from . to t6° as of FIG. 8).

The input/output control device (IOC) 7-00 receives the data transferred by the direct memory access control section (DMC) 52-0 based on the transmitted data strobe signal dst, and transfers the data to the file memory (FM) 8-0. Store in.

When the data specified in the write command has been transferred,
The direct memory access control unit (DMC) 52-0 connects the main memory (MM) 3-0 to the input/output control unit (IOC).
)7-00, and central control unit (CC)
) 2-0, and a response signal acko to the input/output controller (IOC) 7-00.

transmission is stopped (time t7° in FIG. 8).

By repeating the above process, the central controller (CC) 2-0 finishes storing the storage contents of the main memory (MM) 3-0 in the file memory (FM) 8-0, and then stores the contents of the main memory (MM) 3-0 in the file memory (FM) 8-0. (FM) 8-1 and main memory (MM) 3-0
An input/output control device (I) is connected to an address decoder (ADC) 51-0 via a processor bus 4-0, and a file memory (FM) 8-1 is connected to the address decoder (ADC) 51-0 in order to store the memory contents of the
When the address of OC) 7-10 is set, the address decoder (ADC) 51-0 outputs the data via the confounding signal line 9, the selector (SEL) 55-1 in the peripheral bus controller (PBC) 5, and the peripheral bus 6-1. input/output control device (IOC) 7
-10 to transmit a selection signal.

The input/output controller (IOC) 7-10 receives the selection signal transmitted from the address decoder (ADC) 51-0, thereby selecting the peripheral bus controller (PBC) 50 from the central controller (CG) 2-0. .5-1 and surrounding bus 6-
When the write command transmitted via 1 is stored in the internal register (L++ at the time of FIG. 8), the write state is set,
A data transfer request signal req+o is sent to the terminal MRQ of the direct memory access control unit (DMC) 52-0 via the peripheral bus 6-1, the selector (SEL) 56-1, the confounding signal line 9, and the selector (SEL) 56-0. to communicate (
(as of Fig. 8 Lzt).

Data transfer request signal req. The direct memory access control unit (DMC) 52-0 that received the above prepares for data transfer from the main memory (MM) 3-0 to the input/output control unit (IOC) 7-10 through the same process as described above. After that, a central control unit (CC) is connected via a processor bus 4.
) 2-0 and transmits an operation stop request to terminal MA
CK, to selector (SEL) 56-0, confounding signal line 9
, a response signal a to the human output control device (IOC) 7-10 via the selector (SEL) 56-1 and the peripheral bus 6-0.
Ck+o is transmitted (time point L3+ in FIG. 8).

The input/output control device (IOC) that received the response signal aCk+o
)7-10 is a data transfer request signal req, which was transmitted to the direct memory access control unit (DMC) 52-0 in the same manner as described above. Sending is stopped (time t□ in Fig. 8).

Thereafter, the direct memory access control unit (DMC) 52-
0 is the direct memory access format as mentioned above,
Data is extracted from the main memory (MM) 3-0 and sent to the input/output control device (MM) via the confounding signal line 9 and the peripheral bus 6-■.
IOC) 7-10, and also transfers data from terminal DST to selector (SEL) 56-0, confounding signal line 9, and selector (
A data strobe signal d is sent to the input/output controller (IOC) 7-10 via the SEL) 56-1 and the peripheral bus 6-1.
st (time ts+ to t61 in FIG. 8).

The input/output control device (IOC) 7-10 receives the data transferred by the direct memory access control section (DMC) 52-0 based on the transmitted data strobe signal aSt, and transfers the data to the file memory (FM) 8-1. Store in.

When the data specified in the write command has been transferred,
The direct memory access control unit (DMC) 52-0 connects the main memory (MM) 3-0 to the human output control unit (IOC).
) 7-10, and central control unit (CC)
) 2-0, and a response signal ack+ to the input/output control device (10C) 7-10.

(time t1 in FIG. 8).

As described above, the storage contents of the main memory (MM) 3-0 are stored in the file memories (FM) 8-0 and 8-1.

[Problem to be solved by the invention]

As is clear from the above explanation, in a conventional information processing device, a direct memory access control unit (DMC)
52-0 is file memory (FM) 8-0 and 8-1
Since data is individually transferred to the information processing apparatus 1 and a request is made to the central control unit (CC) 2-0 to suspend operation each time, there is a problem in that the processing capacity of the information processing apparatus 1 is reduced.

An object of the present invention is to store data in a dual external storage device without reducing the processing capacity of an information processing device as much as possible.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle of the present invention.

In FIG. 1, 100 is a main storage device, 200-1 and 200-2 are dual external storage devices, and 300 is a direct memory access control device.

400 is a mode setting means provided according to the present invention.

500 is a synchronization means provided according to the invention.

600 is a parallel transfer means provided according to the present invention.

[Effect]

Mode setting means 400 sets the information processing apparatus to a predetermined mode.

The synchronizing means 500 synchronizes each external storage device 20 when the mode setting means 400 sets the information processing apparatus to a predetermined mode.
After monitoring the data transfer request signals output from each external storage device 200-1.200-2 and confirming that both data transfer request signals have been output from each external storage device 200-1.200-2, direct memory access is performed. A data transfer request signal is transmitted to the control device 300.

The parallel transfer means 600 transmits data transferred by the direct memory access control device 300 to both external storage devices 200-1 and 200-2 in parallel when the mode setting means 400 sets the information processing device to a predetermined mode. do.

Therefore, since data is transferred to the duplicated external storage devices at the same time, the period during which the information processing device is not processing is halved compared to when data was transferred to each external storage device individually. However, the reduction in the processing capacity of the information processing device can be significantly reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram illustrating a selector according to an embodiment of the present invention, and FIG. 3 is a diagram illustrating a data transfer process according to an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures. Furthermore, the target information processing device and peripheral bus control device are as shown in FIGS. 5 and 6.

In FIGS. 2, 5, and 6, a main memory (MM) 3 is shown as the main memory 100 in FIG. 1, and the dual external storage 20 in FIG.
File memory (FM
) 8-1 and 8-2 are shown, a direct memory access control unit (DMC) 52 is shown as the direct memory access control device 300 in FIG. 1, and a mode register (DMC) is shown as the mode setting means 400 in FIG. MR) 54 and gate signal generator (GSG) 5
Gates 567 and 568 are provided as synchronization means 500 in FIG. 1, and gate 569 is provided as parallel transfer means 600 in FIG.

In addition, each information processing device l has an input/output control device (IOC) 7
In addition to the above-mentioned non-separation mode and separation mode, a copy mode is added as a control format.

In the copy mode, only when writing to the human output control unit (IOC) 7 in the non-separation mode, the current direct memory access control unit (DMC) 52 simultaneously writes to the input/output control unit (IOC) 7 of both systems. This allows data to be transferred.

The central controller (CC) 2 is an input/output controller (IOC)
Peripheral bus controller (PBC) 5 depending on the control type of 7.
The logic values of the separation mode signal sep and the copy mode signal cpy to be stored in the mode register (MR) 54 in the MR are set.

The gate signal generation unit (GSG) 570-0 uses the active shade signal act supplied from the solid control device (CC) 2, the separation mode signal sep and the copy mode signal cpy stored in the mode register (MR) 54. Perform the following logical operation processing and generate the gate signal. to g6°. In addition, the separation mode signal sep and the copy mode signal cpy cause the contents of the active system mode register (MR) 54 to be transmitted to the standby system peripheral bus control device via the confounding signal line 9.
PBC) 5.

g,,=act X (-5ep) Xcpyg2
゜=act x (-5ep) x (-cpy
)g ao=act +sep g4゜= (-act) x (-3ep) X
(cpy)gso=aCt x (sep)X
(cpy)g6゜is(-act)X(-5ep
) [However, x represents logical product, + represents logical sum, and - represents negation.] Note that the gate signal generation unit (GSC;) 570-1 also generates active mode signal act, separation mode signal sep, and copy mode signal CI. ) 3', the gate signal generator (GS
G) 57 (Performs the same logical operation process as in 10 and generates gate signals g to gb+.

For example, when the 0-system information processing device 1-0 is the active system and the 1-system information processing device 1-1 is the backup system and is operated in copy mode, the central controller (CC) 2-0 sends a copy mode signal. Set cpy to logic 1++ and separate mode signal s
ep is set to logic "0" and an activation mode signal act is supplied to the 0-system peripheral bus control device (PBC) 5-0.
to logic °“l”, and the l-based peripheral bus controller (PBC)
) 5-1 is set to logic “O”.
Set to °.

In such a case, the gate signal generator (GSG) 570-
0 generates a gate signal g,. and g:+.

The gate signals gs+ and gb+ generated by the gate signal generation unit (GSG) 570-1 are set to logic "'I11," and the other gate signals g2°, g4°, g,.

, g. and g, through ga+ are set to logic ``0''.

As a result, in selector (SEL) 56-0, only data 1-562-0.564-0 and 568-0 become conductive, and in selector (SEL) 56-1, gates 565-1 and 569 -1 becomes conductive, and the other gates 562-0.565-0 to 567-0.569-0.562-1 to 564-1
．． 566-1 and 568-1 are cut off, and the terminal RQo of the direct memory access control unit (DMC) 52-0 is connected to the peripheral bus 6-0 via the gate 567-0. .568-0, is connected to the peripheral bus 6-1 via the confounding signal line 9 and the selector (SEL) 56-1, and is also connected to the terminal ACK of the direct memory access control unit (DMC) 52-O. -0 to the peripheral bus 6-0, and is connected to the peripheral bus 6-1 through the selector (SEL) 56-0, the confounding signal line 9 and the gate 569-1,
Furthermore, a direct memory access control unit (DMC) 52-
0 terminal DST is connected to the peripheral bus 6-0 via the gate 564-0, and is also connected to the selector (SEL) 56-0.
0, confounding signal line 9, and '7' to peripheral bus 6-1 via gate 565-1.

Note that the selector (
SEL) 55-0 and 55-1 are set in the same manner as described above.

In this state, the central controller (CC) 2-0 transfers the storage contents of the main memory (MM) 3-0 to the file memory (FM).
8-0 and 8-1, first the address decoder (ADC) 51-0 is sent via the processor bus 4-0.
If you set the address of the input/output control unit (IOC) 7-00 to which the file memory (FM) 8-0 is connected to,
The address decoder (ADC) 51-0 is a selector (SE
L) 55-0 and the peripheral bus 6-0 to transmit the selection signal to the input/output controller (IOC) 7-00.

The human output control device (IOC) 7-00 receives the selection signal transmitted from the address decoder (ADC) 51-0, so that the peripheral bus control device (PBC) 5 -0 and the write command transmitted via the peripheral bus 6-0 are stored in the internal register (UIIO at the time of FIG. 3), the write state is set, and the selector (SEL) is transmitted via the peripheral bus 6-0. A data transfer request signal req is sent to the gate 567-0 of the gate 56-0. (L12° as of Fig. 8).

Next, the central control unit (CC) 2-0 is an input/output control unit (IOC) to which a file memory (FM) 8-1 is connected to an address decoder (ADC) 51-0 via a processor bus 4-0. When the address of 7-10 is set, the address decoder (ADC) 51-0 outputs the data to the human output controller (IOC) 7-10 via the confounding signal line 9, the selector (SEL) 55-1, and the peripheral bus 6-1. Convey a selection signal.

The input/output controller (IOC) 7-10 receives the selection signal transmitted from the address decoder (ADC) 51-0, thereby selecting the peripheral bus controller (PBC) 5 from the central controller (CC) 2-0. -0.5-1 and surrounding bus 6
-0 is stored in the internal register (time point L12+ in FIG. 8), the write state is set, and the peripheral bus 6-1 and selector (SEL) 56-1
through the gate 567- of the selector (SEL) 56-0.
0, the data transfer request signal req. (time point L12+ in FIG. 8).

The gate 567-0 receives the data transfer request signal reqoa (logic "1") at time tlzo, and further receives the data transfer request signal reqoa (logic "1") at time L.
A data transfer request signal req is sent to II+. (Logic “l”)
is transmitted, the direct memory access control unit (D
A data transfer request signal req, which is transmitted to the terminal RQo of MC) 52-0. is set to logic "l".

Direct memory access control unit (DMC) 52-0 that received the data transfer request signal r(io. (logic “1 pass”)
is based on instructions from the central controller (CC) 2-0,
From the main memory (MM) 3-0 to the human output control device (IOC)
) 7-00 and 7-10, the central control unit (CC
) 2-0 and transmits the operation stop request to terminal ACK.
.

From the gate 562-0 in the selector (SEL) 56-0
and a human output control device (IOC) via peripheral bus 6-0.
) 7-00, and transmits the response signal ackoo to the selector (SEL) 56-0, the confounding signal line 9, and the selector (
response signal ackl to human output controller (IOC) 7-10 via game I-569-1 in SEL) 56-1 and peripheral bus 6-1; (L12□ as of Figure 8)
.

Response signal ack, . The input/output control device (IOC) that received the
)7-00 is a data transfer request signal reqo that has been transmitted to the gate 567-0. and stops sending the response signal a.
ck,. Input/output control unit (IOC) 7-10 that received the
is the data transfer request signal req, which was being transmitted to the gate 567-0. The transmission is stopped (time point L12 in FIG. 8). Data 1-56 Fu0 is the data transfer request signal reqo at time t+az.

and req+o (both logic °"1°") are stopped, the direct memory access control unit (DMC)
Data transfer request signal 1 transmitted to terminal RQ of 52-0
” (sets Ioo to logic “O”.

Thereafter, the direct memory access control unit (DMC) 52-
0 is a direct memory access format, in which data is extracted from the main memory (MM) 3-0 via the processor bus 4-0, and data is extracted from the human output control device 1 (I) via the peripheral bus 6-0.
In parallel with the transfer to peripheral bus 6-00 (OC) 7-00,
564-0 and peripheral bus 6-0.
: In parallel with transmitting the data strobe signal aSt to the JO, the selector (SEL) 56-0, the confounding signal line 9,
The data strobe signal dst is also transmitted to the input/output control device (IOC) 7-10 via the game) 565-1 and the peripheral bus 6-1 (from test to LI6□ in FIG. 8).
.

Human output control device (IOC)? -00 receives data transferred by the direct memory access control unit (DMC) 52-0 based on the transmitted data strobe signal dst, and stores it in the file memory (FM) 8-0;
Further, the human output control device (IOC) 7-10 also receives data transferred by the direct memory access control section (DMC) 52-0 based on the transmitted data strobe signal dst, and receives the data transferred from the file memory (FM) 8-0. Store in 1.

When the data specified in the write command has been transferred,
The direct memory access control unit (DMC) 52-0 connects the main memory (MM) 3-0 to the input/output control unit (IOC).
) 7-00 and 7-10, and stop requesting the central control unit (CC) 2-O to stop operation, and also stop the data transfer to the central control unit (CC) 2-O, and also stop the data transfer to the central control unit (CC) 2-O.
Response signal ack for 0. (8th
Figure time t3. t).

By repeating the above process, the main memory (MM) 3
-0 is stored in parallel in file memories (FM) 8-0 and 8-1.

As is clear from the above explanation, according to this embodiment, the central control unit (CC) 2-0 is connected to the mode register (MR) 5.
The active mode signal acto and the copy mode signal CP)'o stored in the register 4-0 are set to logic "°l", and the central controller (CC) 2-1 sets the mode register (MR) 5
Copy mode signal CP) stored in 4-1
By setting it to °1, the input/output control device (IOC)
) Data transfer request signal re from 7-00 and 7-10
q. . and request,. After confirming that the data has been transmitted in full, the contents of the main memory (MM) 3-0 can be transferred and stored in the file memories (FM) 8-0 and 8-1 in parallel. Meanwhile, the central control unit (CC)
2-0 is only in a suspended state from time t, 32 to t112, and, like the conventional information processing device 1, data is individually transferred to file memories (FM) 8-0 and 8-1, respectively. Each time, the central control unit (CC) 2-
Compared to the case where 0 is set as the inactive state, the inactive time is halved.

Note that FIGS. 2, 3, 5, and 6 are merely examples of the present invention, and the configuration of the target information processing device is not limited to that shown in the figures. Although many other modifications may be considered as illustrated in FIG. 4, the effects of the present invention remain the same in either case.

FIG. 4 is a diagram showing an example of another information processing device to which the present invention is applied.

In FIG. 4, the central controller (CC) 2, main memory (MM) 3 and peripheral bus controller (PBC) 5 are single layered, and file memories (FM) 8-0 and 8-1
are input/output controllers (IOCs) 7-0 and 7-, respectively.
1 is connected in duplicate.

In such a case, the direct memory access control unit (DMC) 52 in the peripheral bus control device (PBC) 5 is configured as the direct memory access control unit (DMC) 5 in FIG.
2-0, it is possible to transfer the storage contents of the main memory (MM) 3 to the input/output control units (IOC) 7-0 and 7-1 in parallel.

〔Effect of the invention〕

As described above, according to the present invention, in the information processing device, data is simultaneously transferred to the duplicated external storage devices, so compared to the case where data is transferred to each external storage device individually, the information The period during which the processing device is not processing is halved, and the decline in the processing capacity of the information processing device can be significantly reduced.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the invention, FIG. 2 is a diagram showing a selector according to an embodiment of the invention, FIG. 3 is a diagram illustrating a data transfer process according to an embodiment of the invention, and FIG. A diagram showing an example of another information processing device to which the present invention is applied, FIG. 5 is a diagram showing an example of an information processing device to which the present invention is applied, and FIG. 6 is an example of the peripheral bus control device in FIG. 7 is a diagram showing an example of a conventional selector, and FIG. 8 is a diagram showing an example of a conventional data transfer process. In the figure, l is an information processing device, 2 is a central control device (C
G), 3 and 100 are main memory (MM), 4 is a processor bus, 5 is a peripheral bus controller (PBC), 6 is a peripheral bus, 7 is an input/output controller (IOCL8 is a file memory (FM), 9 is a confounding signal line, 51 is an address decoder (ADCL 52 is a direct memory access control unit (DMC), 53 is an interrupt control unit (IRC), 54 is a mode register (MR), 55 and 56 are selectors (S
EL), 200 is an external storage device, 300 is a direct memory access control device, 400 is a mode setting means, 50
0 is a synchronizing means, 561 to 569 are gates, 570 is a gate signal generation unit, and Akira Honbetsu's principle diagram etc. Jyuto Ah data transfer overgatai 1st

Claims (1)

Scope of Claims: An information processing device comprising a direct memory access control device (300) that stores the storage contents of a main storage device (100) in dual external storage devices (200-1, 200-2), mode setting means (400) for setting the information processing apparatus to a predetermined mode; and when the mode setting means (400) sets the information processing apparatus to the predetermined mode, each of the external storage devices (
200-1, 200-2), and confirmed that both data transfer request signals were output from each of the external storage devices (200-1, 200-2). synchronizing means (500) for transmitting a data transfer request signal to the direct memory access control device (300); and when the mode setting means (400) sets the information processing device to the predetermined mode, A data transfer system characterized by comprising: parallel transfer means (600) for transmitting data transferred by a memory access control device (300) to both external storage devices (200-1, 200-2) in parallel.