JPH0370878B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a memory control system in a microcomputer.

(Prior Art) FIG. 4 is a block diagram of a storage device using a conventional microcomputer as a central processing unit. In the figure, 1 is a selection circuit that determines whether a storage device is selected based on an address input 106 and a storage device activation signal 107 based on a read or write request; 3;
4 is a refresh address generation circuit, 4 is a refresh operation starting circuit, 5 and 6 are address switching circuits,
7 specifies the priority determination between the refresh request signal 110 and the signal 109 output when the address input 106 selects the storage device at the time of a read or write request, and the operation mode from the refresh operation or the read or write operation. priority determination circuit, 9
10 is a timing generation circuit that controls the operation of each part; 11 is a driver circuit that inputs write data from the central processing unit to the storage element array 9;
Reference numeral 12 denotes a driver circuit whose output can be controlled and sends read data from the memory element array 9 to the central processing unit.

FIG. 5 is a conventional interface time chart between a central processing unit and a storage device.

Next, the operation will be explained with reference to FIGS. 4 and 5.

The operation modes of the storage device shown in FIG. 4 include a refresh operation and a read or write operation.
The refresh operation is normally performed by the refresh operation starting circuit 4, which sends a refresh request signal 110 every 16 μs.
becomes “H” and execution begins. The signal 109 becomes "H" only when the storage device is selected by the selection circuit 1 by the address input 106 from the central processing unit and the storage device activation signal 107. The priority determination circuit 7 receives the signal 109 and the refresh request signal.
When either signal 110 becomes “H”, signal 113 becomes “H”
At the same time, the timing generating circuit 10, which specifies the operation mode of the signal 112 as either the operation "L" by the signal 109 or the operation "H" by the refresh request signal 110, starts operating when the signal 113 becomes "H". , signal 112 and signal 108 to generate and control the operation timing of each part. Here, signal 123 is
This signal is for fixing the operation mode of the priority determination circuit 7 until the time when the series of controls is completed and the next signal 109 and the refresh request signal 110 make the storage device operable. Signal 115 is a signal for switching between a row address and a column address of a dynamic type memory IC, which is a storage element. signal 116
is the RAS signal of the dynamic memory IC,
Signal 117 is also a CAS signal, and signal 118 is also a read/write signal. Signal 124 is a response signal to an operation request from the central processing unit to the storage device.

(Problem to be Solved by the Invention) However, in the case of the conventional storage device as described above, the storage device activation signal 107 is issued (fifth
Since the time priority with respect to the refresh request signal 110 is determined by the priority determination circuit 7, the time required to determine this temporal priority (time t ₁₇ in FIG. 5 _{) -t18} ) is added to the response time of the storage device to the storage device activation signal from the central processing unit.

Therefore, the present invention aims to solve these drawbacks and to speed up the response between the central processing unit and the storage device.

(Means for Solving the Problems) The present invention performs an asynchronous refresh operation using a microcomputer as a central processing unit and a dynamic memory IC as a storage element, to which an address control signal is output prior to a read or write request signal. In the storage device, there is a determining means for determining the priority between an address control signal and a refresh operation, and a central processing unit that starts an operation according to the result of the determining means and immediately responds to an address instruction output from the central processing unit. This is provided with a response means for returning the information to the processing device.

(Operation) As described above, according to the present invention, the priority of the address control signal outputted prior to the read or write request signal from the central processing unit and the refresh operation is determined, and the operation is performed according to the result of the determination. The response to the central processing unit can be sped up by starting the process and immediately returning a response to the central processing unit in response to an address instruction output from the central processing unit.

(Embodiment) FIG. 1 is a configuration diagram showing an embodiment of the present invention. In the figure, 1 is an address input 106 and a storage device activation signal due to a read or write request.
107 is a selection circuit that determines whether a storage device is selected; 2 is an address control signal control circuit for an address control signal 130 given from the central processing unit; while signal 136 is "L", signal 131 and signal 134 is controlled so that it does not become "H". 3 is a refresh address generation circuit, 4 is a refresh operation activation circuit, 5 and 6 are address switching circuits, and 7 is generated from selection circuit 1 when the address input 106 selects the storage device during a read or write request. A priority determination circuit that determines the priority of the signal 109, the signal 132 generated from the address control signal control circuit 2, and the refresh request signal 110, and determines the operation mode of refresh operation, read operation, or write operation. , 8 are activated by a signal 113 which becomes "H" when the priority determination circuit 7 is requested to operate by the refresh request signal 110 or signal 132, and the signal 134 which is the output of the address control signal control circuit 2 becomes "H". ”, a timing control circuit keeps the signal 133 at “H” until the signal 135 becomes “H” from the timing generation circuit 10, 9 is a storage element array using a dynamic memory IC, and 10 is a circuit for each part. 11 is a driver circuit that inputs write data from the central processing unit to the storage element array 9; 12 is a driver circuit that can control output and sends read data from the storage element array 9 to the central processing unit. , 13, 14, 18 are OR functional elements, 15, 16, 17, 19 are AND functional elements,
20 is a resistor so that the present storage device can be used even in a conventional central processing unit in which the signal 130 does not exist.

FIG. 2 is a time chart between the central processing unit and the storage device in this embodiment. Next, the operation will be explained based on FIGS. 1 and 2.

First, the first operation mode will be explained.

First, it is assumed that the timing generation circuit 10 has been initialized, and the signals of the main parts are as follows.

Signal 135..."L" Signal 136..."H" Signal 137..."L" Signal 138..."L" In this state, the address control signal 130 changes from "H" to "L" at time _t0 in FIG. ”, the output signal 131 of the address control signal control circuit 2 changes from “L” to “H” and maintains this state until the signal 136 changes to “L”. On the other hand, signal 134 is still “L”
It remains as it is. The priority determination circuit 7 starts operating when the output signal 131 of the address control signal control circuit 2 becomes "H". In other words, the priority determination circuit 7
The output signal 113 of is set to “H” and the signal
112 is set to "L" to indicate that it is not in the refresh operation mode. Note that at this time, the output signal 110 of the refresh operation starting circuit 4 is "L", and it is assumed that the refresh operation mode is not in effect. As described above, the output signal 113 of the timing control circuit 8 becomes "H" when the output signal 1130 of the priority determination circuit 7 becomes "H".
Therefore, the output signal 123 of the OR function element 14 is forced to be "H". When the signal 123 becomes "H", the signal 113 becomes "L" again, but the signal 112 remains unchanged and maintains the operating mode at that time.
Note that this operation mode changes when the signal 123 is "L". In the above, even if the signal 113 becomes "L", the output of the timing control circuit 8 remains "H" without changing, and this changes only when the signal 135 becomes "H". In this state, when the address control signal 130 changes from "L" to "H" at time t1 in FIG. ₂ , the output signal 134 of the address control signal control circuit 2 changes from "L" to "H".
Changes to When the signal 134 becomes "H", the output of the AND functional element 17 becomes "H", and the output of the OR functional element 1 becomes "H".
The output signal 137 of No. 8 is forcibly set to "H". As a result, the timing generation circuit 10 starts operating. By starting the operation, the signal 135 becomes "H".

Here, Figure 3 shows a dynamic memory IC.
FIG. 2 is a time chart showing the basic operation of FIG. As shown in the figure, the RAS signal 116 is set to “L” (time t ₃ ).
The address of the storage element array 9 is switched from the load address to the column address by the signal 115 (time t ₁₀ ). Therefore, assuming that this storage device is selected, when the storage device activation signal 107 becomes “L” (time t ₄ in FIG. 2), the output signal 109 of the selection circuit 1 becomes “H” and is sent to the timing generation circuit 10. conveyed,
The CAS signal 117 becomes "L" at time _t11 in FIG.
At the same time, the signal 136 also becomes "L". Signal 136 is “L”
Then, the signal 131 and the signal 134 become "L". Prior to this signal 117 going “L”, the signal 118 becomes the signal 108
According to the instruction, it is set to "H" for reading and "L" for writing. In the case of reading, the signal 119 is set to "L" and the read data 121 is transferred to the signal 112.
Output to. Note that in the case of writing, the signal 119 remains at "H". Next, at the time when the read data becomes valid, the signal 138 is set to "H" and the signal 124 is set to "L". Since the signal 124 (response signal in FIG. 2) becomes "L" at time _t5 , the central processing unit disables the signals 101, 102, 106, 107, and 108.
Due to the change in these signals, the signal 109 becomes "L", and the timing generation circuit 10 outputs the signals 115, 116,
Return signals 117, 119, 136, and 138 to their initial states.
After that, the signal 135 is set to "L" to complete the series of operations.

The second operation mode is a case where no storage device is selected by the selection circuit 1 in the first operation mode. CAS signal 117 and signal 119 are “H”
and the signal 138 remains at "L".
Further, the RAS signal 116 becomes "H" after ensuring "L" for the necessary time (time t ₁₃ in FIG. 3). after that,
Signals 135, 136 return to their initial state, terminating the operation. This operation is similar to the RAS of a dynamic memory IC.
This is the same operation as ONLY REFRESH operation. In the case of this operation, it is necessary to control the fall of the RAS signal within the time period in which the address output of the central processing unit is guaranteed.

The third mode of operation is a refresh operation.
The refresh operation starting circuit 4 changes the refresh request signal 110 to "H" approximately every 16 μs. The priority determination circuit 7 determines that the refresh request signal 110 is “H”
As a result, the signal 113 is set to "H" and the signal 112 is set to the refresh mode, that is, set to "H". signal 113
The timing control circuit 8 sets the signal 113 to “H”.
Then, the signal 137 becomes “H” through the AND function element 15 and the OR function element 18 and is input to the timing generation circuit 10. Also, when the signal becomes “H”
The signal 123 becomes "H" via the OR function element 14. When the signal 123 becomes "H", the refresh operation starting circuit 4 gives a "L" pulse to the signal 111 and the signal
Set 110 to “L”. When signal 112 becomes “H”,
The refresh address generated by the refresh address generation circuit 3 is applied to the address signal 104 via the address switching circuit 5. The timing generation circuit 10 starts operating when the signal 104 becomes "H", and since the signal 112 is "H", the address signal 104 becomes the signal 105 and is applied to the storage element array 9 under signal control of the signal 115. Thereafter, the RAS signal 116 is set to "L" (time t3 in FIG. ₃ ). In this third operating mode, the CAS signal 117 and the signal 119 remain at "H", and the signal 138 remains at "L". After ensuring that the RAS signal 116 is “L” for the required time, it becomes “H” (time in Figure 3).
t ₁₃ ), then the signals 135 and 136 are returned to their initial states to terminate the operation. When the signal 135 becomes "L", the priority determination circuit 7 changes the signal 112 to "L". When the signal 112 falls, the refresh address generating circuit 3 generates the next refresh address.

The fourth mode of operation is when the address control signal becomes significant during operation in the third mode of operation. Since signal 136 is “L”, the signal
131 and 134 remain at "L" and do not change. Therefore,
Internal operations are suspended until the end of the third mode of operation. If the signal 109 is "H" when the signal 135 becomes "L" due to the end of the third operation mode, the fourth operation mode starts operation. signal 109
is input to the priority determination circuit 7 via the OR functional element 13. When the signal 132 becomes "H", the priority determination circuit 7 changes the signal 113 to "H" and outputs the signal 112.
becomes “L”. When the signal 113 becomes "H", the timing control circuit 8 changes the signal 133 to "H".
Since the signal 109 is "H" at this time, the signal 137 becomes "H" via the AND function element 16 and the OR function element 18 and is input to the timing generation circuit 10. The subsequent operation is the same as the first operation mode.

(Effects of the Invention) As described above, according to the present invention, the priority of the address control signal outputted prior to the read or write request signal from the central processing unit and the refresh operation is determined. There is an advantage that the response to the central processing unit can be speeded up by starting an operation according to the result and immediately returning a response to the central processing unit in response to an address instruction output from the central processing unit.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is an interface time chart between the central processing unit and the storage device of this embodiment, and Fig. 3 shows the basic operation of a dynamic memory IC. FIG. 4 is a configuration diagram of a conventional storage device, and FIG. 5 is a conventional time chart of an interface between a central processing unit and a storage device. DESCRIPTION OF SYMBOLS 1... Selection circuit, 2... Address control signal control circuit, 3... Refresh address generation circuit, 4
... Refresh operation starting circuit, 5, 6 ... Address switching circuit, 7 ... Priority determination circuit, 8 ... Timing control circuit, 9 ... Storage element array, 10
...timing generation circuit, 11,12...driver circuit, 13,14,18...OR functional element,
15, 16, 17, 19...AND functional element.

Claims (1)

[Claims] 1. A dynamic memory IC with a microcomputer as the central processing unit that outputs an address control signal prior to a read or write request signal.
In a storage device that performs an asynchronous refresh operation and has a memory element as a memory element, a determination means for determining the priority of the address control signal and the refresh operation; A memory control system characterized in that a response means is provided for immediately returning a response to the central processing unit in response to an instruction of an output address.