JPH0367451U - - Google Patents
Info
- Publication number
- JPH0367451U JPH0367451U JP1989130092U JP13009289U JPH0367451U JP H0367451 U JPH0367451 U JP H0367451U JP 1989130092 U JP1989130092 U JP 1989130092U JP 13009289 U JP13009289 U JP 13009289U JP H0367451 U JPH0367451 U JP H0367451U
- Authority
- JP
- Japan
- Prior art keywords
- die pad
- frame
- lead
- semiconductor device
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 2
- 239000000725 suspension Substances 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
Description
第1図はこの考案の一実施例による半導体装置
用リードフレームを示す部分拡大図、第2図は第
1図のリードフレームを用いて、実際に半導体装
置を組み立てた場合を示した部分拡大図、第3図
はこの考案の他の実施例を示す同じく部分拡大図
、第4図〜第8図は従来のリードフレームあるい
は、従来のリードフレームを用いて半導体装置を
組み立てた場合を示したそれぞれ部分拡大図であ
る。 図において、1……ダイスパツト、2……イン
ナーリード、3……吊りリード、4……半導体素
子あるいは集積回路、5……電極、6……金属細
線示す。なお、図中、同一符号は同一、又は相当
部分を示す。
用リードフレームを示す部分拡大図、第2図は第
1図のリードフレームを用いて、実際に半導体装
置を組み立てた場合を示した部分拡大図、第3図
はこの考案の他の実施例を示す同じく部分拡大図
、第4図〜第8図は従来のリードフレームあるい
は、従来のリードフレームを用いて半導体装置を
組み立てた場合を示したそれぞれ部分拡大図であ
る。 図において、1……ダイスパツト、2……イン
ナーリード、3……吊りリード、4……半導体素
子あるいは集積回路、5……電極、6……金属細
線示す。なお、図中、同一符号は同一、又は相当
部分を示す。
Claims (1)
- 半導体素子もしくは集積回路を固着するダイパ
ツト部と、半導体素子もしくは集積回路の各電極
と金属細線等で接続される複数のリード部を有す
る半導体装置用リードフレームにおいて、前記ダ
イパツト部より延在して、フレーム枠に繋がつて
いる吊りリードがダイパツト端に対し垂直部分を
2ケ所設け、前記垂直部分を曲げ加工したことを
特徴とする半導体装置用リードフレーム。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1989130092U JPH0367451U (ja) | 1989-11-06 | 1989-11-06 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1989130092U JPH0367451U (ja) | 1989-11-06 | 1989-11-06 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0367451U true JPH0367451U (ja) | 1991-07-01 |
Family
ID=31677687
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1989130092U Pending JPH0367451U (ja) | 1989-11-06 | 1989-11-06 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0367451U (ja) |
-
1989
- 1989-11-06 JP JP1989130092U patent/JPH0367451U/ja active Pending