JPS63193836U - - Google Patents
Info
- Publication number
- JPS63193836U JPS63193836U JP8516587U JP8516587U JPS63193836U JP S63193836 U JPS63193836 U JP S63193836U JP 8516587 U JP8516587 U JP 8516587U JP 8516587 U JP8516587 U JP 8516587U JP S63193836 U JPS63193836 U JP S63193836U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- lead
- height
- semiconductor element
- bonded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 12
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Wire Bonding (AREA)
Description
第１図及び第２図は本考案半導体装置の一つの
実施例を示すもので、第１図は分解斜視図、第２
図は断面図、第３図は本考案半導体装置の別の実
施例を示す断面図、第４図は従来例を示す斜視図
である。 符号の説明、２……半導体素子がボンデイング
されたリード、３……リードの半導体素子がボン
デイングされた部分、５……半導体素子、６，７
……リード。
実施例を示すもので、第１図は分解斜視図、第２
図は断面図、第３図は本考案半導体装置の別の実
施例を示す断面図、第４図は従来例を示す斜視図
である。 符号の説明、２……半導体素子がボンデイング
されたリード、３……リードの半導体素子がボン
デイングされた部分、５……半導体素子、６，７
……リード。
Claims (1)
- 【実用新案登録請求の範囲】 装置が備える複数のリードのうちの一つのリー
ドの表面に半導体素子がボンデイングされ、該半
導体素子の電極とそれに対応するリードとの間が
コネクトワイヤを介して接続されてなる半導体装
置において、 上記半導体素子がボンデイングされたリードの
その半導体素子がボンデイングされた部分が半抜
き若しくはコイニングされてその部分の表面の高
さが他のリードの上記コネクトワイヤが接続され
た部分の表面の高さよりも低くされてなる ことを特徴とする半導体装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8516587U JPS63193836U (ja) | 1987-05-29 | 1987-05-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8516587U JPS63193836U (ja) | 1987-05-29 | 1987-05-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63193836U true JPS63193836U (ja) | 1988-12-14 |
Family
ID=30940322
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8516587U Pending JPS63193836U (ja) | 1987-05-29 | 1987-05-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63193836U (ja) |
-
1987
- 1987-05-29 JP JP8516587U patent/JPS63193836U/ja active Pending