JPS63180928U - - Google Patents

Info

Publication number
JPS63180928U
JPS63180928U JP7115687U JP7115687U JPS63180928U JP S63180928 U JPS63180928 U JP S63180928U JP 7115687 U JP7115687 U JP 7115687U JP 7115687 U JP7115687 U JP 7115687U JP S63180928 U JPS63180928 U JP S63180928U
Authority
JP
Japan
Prior art keywords
lead
semiconductor element
bonded
height
connect wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7115687U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7115687U priority Critical patent/JPS63180928U/ja
Publication of JPS63180928U publication Critical patent/JPS63180928U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第1図及び第2図は本考案半導体装置の一つの
実施例を示すもので、第1図は分解斜視図、第2
図は断面図、第3図及び第4図は本考案半導体装
置の別の実施例を示すもので、第3図は断面図、
第4図は封止前の状態を示す斜視図、第5図は従
来例を示す斜視図である。 符号の説明、2,12……半導体素子がボンデ
イングされたリード、6,7,14,15……リ
ード、3,13……リードの半導体素子がボンデ
イングされた部分、5……半導体素子。

Claims (1)

  1. 【実用新案登録請求の範囲】 装置が備える複数のリードのうちの一つのリー
    ドの表面に半導体素子がボンデイングされ、該半
    導体素子の電極とそれに対応するリードとの間が
    コネクトワイヤを介して接続されている半導体装
    置において、 上記半導体素子がボンデイングされたリードの
    その半導体素子がボンデイングされた部分の表面
    の高さが他のリードの上記コネクトワイヤが接続
    された部分の表面の高さよりも低くされてなる、 ことを特徴とする半導体装置。
JP7115687U 1987-05-13 1987-05-13 Pending JPS63180928U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7115687U JPS63180928U (ja) 1987-05-13 1987-05-13

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7115687U JPS63180928U (ja) 1987-05-13 1987-05-13

Publications (1)

Publication Number Publication Date
JPS63180928U true JPS63180928U (ja) 1988-11-22

Family

ID=30913462

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7115687U Pending JPS63180928U (ja) 1987-05-13 1987-05-13

Country Status (1)

Country Link
JP (1) JPS63180928U (ja)

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