JPH0366811B2 - - Google Patents
Info
- Publication number
- JPH0366811B2 JPH0366811B2 JP57080927A JP8092782A JPH0366811B2 JP H0366811 B2 JPH0366811 B2 JP H0366811B2 JP 57080927 A JP57080927 A JP 57080927A JP 8092782 A JP8092782 A JP 8092782A JP H0366811 B2 JPH0366811 B2 JP H0366811B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- conductivity type
- gate region
- regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 15
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 108091006146 Channels Proteins 0.000 description 19
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 9
- 230000000694 effects Effects 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 230000005669 field effect Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法、特にチヤンネ
ル領域をイオン注入で形成した接合型電界効果ト
ランジスタ（以下JFETと略記する）の製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a junction field effect transistor (hereinafter abbreviated as JFET) in which a channel region is formed by ion implantation.
第１図ないし第２図は、チヤンネル領域をイオ
ン注入で形成した汎用演算増幅器などに使用する
従来のJFETの構造を示す。 1 and 2 show the structure of a conventional JFET used in general-purpose operational amplifiers, etc., in which the channel region is formed by ion implantation.
第１図は従来のJFETの平面図であり、第２図
はＡ−Ａ線による断面図である。第２図におい
て、１はｐ型半導体基板、その一部にｎ型埋込み
領域２を設け、さらに、一平面に抵抗率数Ωcmの
ｎ型レピタキシヤル層３を積層し、次にｐ型分離
領域４を形成し、次にｐ型ソース領域５とドレイ
ン領域６とを同時に形成し、さらに、高濃度ｎ型
ゲート領域７を設ける。このｐ型ソース領域５、
ｐ型ドレイン領域６および高濃度ゲート領域７を
熱拡散および酸化工程を経て形成するときにでき
る酸化膜の一部Ｘ，Ｙを、ｐ型チヤンネル領域８
とｎ型トツプゲート領域９を設けるために、PR
（フオトレジスト）工程を経て除去する。次に不
純物としてボロンを数百Kev、1017cm-3程度の濃
度でイオン注入してｐ型チヤンネル領域８を形成
し、その直後に不純物としてリンを数十Kev、
1018cm-3程度の濃度でイオン注入してｎ型トツプ
ゲート領域９を形成する。もちろんｎ型トツプゲ
ート領域９は、高濃度ゲート領域７と短絡された
状態になつている。次に熱酸化膜１１の上に気相
成長工程により酸化膜１０を数千Å成長して、次
に電極取り出し用にコンタクト窓を開け、アルミ
ニウム等の金属電極１２を形成する。 FIG. 1 is a plan view of a conventional JFET, and FIG. 2 is a cross-sectional view taken along line A-A. In FIG. 2, 1 is a p-type semiconductor substrate, a part of which is provided with an n-type buried region 2, an n-type epitaxial layer 3 with a resistivity of several Ωcm is laminated on one plane, and then a p-type isolation region 4 is formed. , then a p-type source region 5 and a drain region 6 are formed simultaneously, and a heavily doped n-type gate region 7 is provided. This p-type source region 5,
Parts X and Y of the oxide film formed when the p-type drain region 6 and high concentration gate region 7 are formed through thermal diffusion and oxidation steps are removed as a p-type channel region 8.
In order to provide an n-type top gate region 9, PR
(photoresist) process to remove it. Next, a p-type channel region 8 is formed by ion implanting boron as an impurity at a concentration of several hundred keV and about 10 17 cm -3 , and immediately after that, phosphorus is ion-implanted as an impurity at a concentration of several tens of keV and about 10 17 cm -3.
An n-type top gate region 9 is formed by implanting ions at a concentration of about 10 18 cm -3 . Of course, the n-type top gate region 9 is in a short-circuited state with the heavily doped gate region 7. Next, an oxide film 10 of several thousand angstroms is grown on the thermal oxide film 11 by a vapor phase growth process, a contact window is opened for taking out the electrode, and a metal electrode 12 made of aluminum or the like is formed.
以上の従来構造では、以下に示す欠点があつ
た。それは、第１にJFETの電気的特性の重要な
要素の１つである飽和電流の均一度が得にくいこ
と。第２に前述、飽和電流の相対比が高精度に得
にくいこと。の２つが上げられる。欠点第１は、
第１図においてｐ型チヤンネル領域８およびｎ型
トツプゲート領域９は、高濃度ゲート領域７によ
つて包囲された全域にイオン注入により形成され
ているため、ｐ型ソース領域５とｐ型ドレイン領
域６との間のエツヂ効果（まわり込みの効果）に
より、JFETのパターン設計上のチヤンネル巾Ｗ
に対し、実際のチヤンネル巾は広いものとなると
ともにチヤンネル巾のバラツキが発生する。この
事はJFETの飽和電流のバラツキの要因になる。
欠点第２は、例えば飽和電流の相対比２対１が必
要とされる２つの従来構造によるJFETに対し、
一方のJFETは第１図に示すチヤンネル巾Ｗを設
定した場合、他方のJFETのチヤンネル巾を単に
Ｗ／２となるようにｐ型ソース領域５およびｐ型
ドレイン領域６をそれぞれ設定していた。しか
し、このような従来構造によるJFETのチヤンネ
ル巾と飽和電流の相関は、第３図の実線で示すよ
うな曲線で表わされる。これはチヤンネル巾Ｗの
場合のｐ型ソース領域５とｐ型ドレイン領域６と
の間に生ずるエツヂ効果に対して、チヤンネル巾
Ｗ／２の場合のエツヂ効果が無視できなくなるた
めに２対１の高精度の飽和電流比が得られなくな
る。この事はJFETの飽和電流の相対比を高精度
に設定することを困難にする。 The conventional structure described above has the following drawbacks. Firstly, it is difficult to obtain uniform saturation current, which is one of the important elements of JFET's electrical characteristics. Second, as mentioned above, it is difficult to obtain the relative ratio of saturation currents with high accuracy. Two things can be mentioned. The first drawback is
In FIG. 1, the p-type channel region 8 and the n-type top gate region 9 are formed by ion implantation in the entire area surrounded by the heavily doped gate region 7, so that the p-type source region 5 and the p-type drain region 6 Due to the edge effect (wrapping effect) between
On the other hand, the actual channel width becomes wider and variations in channel width occur. This causes variations in the saturation current of the JFET.
The second drawback is that, for example, compared to the two conventional JFET structures that require a relative ratio of saturation currents of 2:1,
When one JFET has a channel width W shown in FIG. 1, the p-type source region 5 and p-type drain region 6 are each set so that the channel width of the other JFET is simply W/2. However, the correlation between the channel width and saturation current of a JFET with such a conventional structure is expressed by a curve as shown by the solid line in FIG. This is because the edge effect that occurs between the p-type source region 5 and the p-type drain region 6 when the channel width is W is not negligible when the channel width is W/2. A highly accurate saturation current ratio cannot be obtained. This makes it difficult to set the relative ratio of JFET saturation currents with high precision.
本発明の目的は上記のような飽和電流のバラツ
キおよび相対比精度の改善を施した半導体装置の
製造方法を提供するものである。 An object of the present invention is to provide a method of manufacturing a semiconductor device in which the above-described variations in saturation current and relative accuracy are improved.
本発明の半導体装置の製造方法は、半導体基板
の一主面側に形成された一導電型半導体層に、前
記一主面上の第１の方向に沿つて第１の接合深さ
を有する逆導電型のソース、ドレイン領域を相対
向させて形成する工程と、前記ソース、ドレイン
領域と離隔してこれを取り囲むように前記第１の
方向に沿つて相対向して設けられた第１、第２の
領域及び、前記第１の方向と直交する第２の方向
に沿つて相対向して設けられた第３、第４の領域
を有する環状の一導電型の高濃度ゲート領域を形
成する工程と、所定形状のフオトレジストマスク
を形成しイオン注入法を用いて、前記ソース、ド
レイン領域にはさまれ、かつ、ソース、ドレイン
領域の前記第１の方向のエツジ部を越えない一導
電型半導体層に前記第１の接合深さよりも浅い、
第２の接合深さを有する逆導電型のチヤネル領域
を形成すると共に、該逆導電型のチヤネル領域の
一部に一対の突出領域を設け、前記高濃度ゲート
領域の第３、第４の領域の側面にそれぞれ終端さ
せる工程と、前記フオトレジストマスクを用いて
イオン注入法のより、前記第２の接合深さよりも
浅い第３の接合深さを有し、前記チヤネル領域と
同一形状の一導電型トツプゲート領域を形成する
と共に、該トツプゲート領域の一部に設けられた
一対の突出領域を、前記高濃度ゲート領域の第
３、第４の領域に接続する工程とを含むことを特
徴とする。 In the method for manufacturing a semiconductor device of the present invention, a semiconductor layer of one conductivity type formed on one main surface side of a semiconductor substrate has a first junction depth along a first direction on the one main surface. a step of forming conductive type source and drain regions facing each other; and a step of forming conductive type source and drain regions opposite to each other along the first direction so as to be spaced apart from and surrounding the source and drain regions. forming an annular high-concentration gate region of one conductivity type having a second region and third and fourth regions facing each other along a second direction orthogonal to the first direction; A photoresist mask having a predetermined shape is formed and an ion implantation method is used to form a semiconductor of one conductivity type that is sandwiched between the source and drain regions and that does not extend beyond the edge portion of the source and drain regions in the first direction. a layer shallower than the first junction depth;
A channel region of opposite conductivity type having a second junction depth is formed, and a pair of protruding regions is provided in a part of the channel region of opposite conductivity type, and third and fourth regions of the high concentration gate region are formed. A conductive layer having a third junction depth shallower than the second junction depth and having the same shape as the channel region is formed by ion implantation using the photoresist mask. The method is characterized in that it includes a step of forming a type top gate region and connecting a pair of protruding regions provided in a part of the top gate region to the third and fourth regions of the high concentration gate region.
次に本発明を実施例により説明する。尚、第１
図、第２図と同じ機能の個所は同じ符号で示して
いる。第４図は本発明の第１の実施例を示す平面
図であり、第５図は第４図Ａ−Ａ線における断面
図である。第５図において、第２図で説明したよ
うに、ｐ型半導体基板１にｎ型埋込み領域２をそ
なえたｎ型エピタキシヤル層の表面にｐ型分離領
域を形成した後、ｐ型ソース領域およびｐ型ドレ
イン領域を形成する。この後に高濃度ｎ型ゲート
領域を形成する。次に、ｐ型チヤンネル領域８お
よびｎ型トツプゲート領域９を形成するための酸
化膜の除去を、第４図の点線で示すようなPR形
状にて行なう。つまり、ｐ型ソース領域およびｐ
型ドレイン領域のエツヂ部を越えないようにPR
のパターニングをするとともに、ｎ型トツプゲー
ト領域９を高濃度ゲート領域７の電位を保持する
ために、JFETのｐ型チヤンネル領域８およびｎ
型トツプゲート領域９の一部からチヤンネル巾方
向へ突起を出し、高濃度ゲート領域７と短絡す
る。その様子を第４図Ｂ−Ｂの断面図である第６
図に示す。次に不純物としてボロン数百Kev、
1017cm-3程度の濃度でイオン注入しｐ型チヤンネ
ル領域８を形成し、さらに不純物としてリンを数
十Kev、1018cm-3程度の濃度でｎ型トツプゲート
領域を形成する。第５図および第６図は第４図に
対する平面図であり、第４図Ａ−Ａ断面が第５図
に、第４図Ｂ−Ｂ断面が第６図にそれぞれ相当す
る。 Next, the present invention will be explained by examples. Furthermore, the first
2. Portions having the same functions as those in FIGS. FIG. 4 is a plan view showing the first embodiment of the present invention, and FIG. 5 is a sectional view taken along line A--A in FIG. In FIG. 5, as explained in FIG. 2, after forming a p-type isolation region on the surface of an n-type epitaxial layer having an n-type buried region 2 in a p-type semiconductor substrate 1, a p-type source region and Form a p-type drain region. After this, a heavily doped n-type gate region is formed. Next, the oxide film for forming the p-type channel region 8 and the n-type top gate region 9 is removed in a PR shape as shown by the dotted line in FIG. That is, the p-type source region and p
PR should not go beyond the edge of the mold drain region.
In addition to patterning the p-type channel region 8 and n-type top gate region 9 of the JFET, in order to maintain the potential of the heavily doped gate region 7,
A projection extends from a part of the mold top gate region 9 in the channel width direction and short-circuits with the high concentration gate region 7. This situation can be seen in Figure 6, which is a cross-sectional view taken along line B-B in Figure 4.
As shown in the figure. Next, a few hundred Kev of boron as an impurity,
A p-type channel region 8 is formed by implanting ions at a concentration of about 10 17 cm -3 , and an n-type top gate region is formed using several tens of KeV of phosphorus as an impurity at a concentration of about 10 18 cm -3 . 5 and 6 are plan views of FIG. 4, and the AA cross section in FIG. 4 corresponds to FIG. 5, and the BB cross section in FIG. 4 corresponds to FIG. 6, respectively.
このようにして、本発明の製造方法を用いて得
られるJFETの従来構造と異なる点は、ｐ型チヤ
ンネル領域８およびｎ型トツプゲート領域９はｐ
型ソース領域５およびｐ型ドレイン領域６のエツ
ヂ部を含まないため、従来あつた飽和電流のバラ
ツキ低減および相対比の精度が改善される。ま
た、本発明によるJFETのチヤンネル巾と飽和電
流との相関は第３図の点線で示すような直線にな
る。このことは、JFETの飽和電流の相対比を設
定するためのチヤンネル巾の決定が簡易になる。 Thus, the difference from the conventional structure of the JFET obtained using the manufacturing method of the present invention is that the p-type channel region 8 and the n-type top gate region 9 are
Since the edge portions of the p-type source region 5 and p-type drain region 6 are not included, the conventional variation in saturation current is reduced and the accuracy of the relative ratio is improved. Further, the correlation between the channel width and the saturation current of the JFET according to the present invention is a straight line as shown by the dotted line in FIG. This facilitates the determination of the channel width for setting the relative ratio of the JFET saturation current.
第７図に第２の実施例を示す。第７図におい
て、ｐ型チヤンネル領域８の突起を取り除くと同
時に、ｎ型トツプゲート領域９を高濃度ｎ型ゲー
ト領域７と短絡するために、高濃度ｎ接ゲート領
域７も同様、JFETのチヤンネル巾方向へ突起を
形成する。こうすることにより、JFETのチヤン
ネルはエツヂ効果のない完全なチヤンネル巾Ｗが
実現できる。その様子を第７図Ｂ−Ｂの断面図で
ある第８図に示す。また、本発明の製造方法を用
いて得られるJFETは、バイポーラ型トランジス
タの製造と同時に製造することができるのでバイ
ポーラ型集積回路に組み込むことが容易である。 FIG. 7 shows a second embodiment. In FIG. 7, in order to remove the protrusion of the p-type channel region 8 and at the same time short-circuit the n-type top gate region 9 with the heavily doped n-type gate region 7, the channel width of the highly doped n-contact gate region 7 is similarly reduced. Form a protrusion in the direction. By doing this, the JFET channel can realize a perfect channel width W without edge effects. The situation is shown in FIG. 8, which is a sectional view taken along the line B-B in FIG. Further, since the JFET obtained using the manufacturing method of the present invention can be manufactured at the same time as bipolar transistors, it can be easily incorporated into a bipolar integrated circuit.
第１図および第２図は従来の接合型電界効果ト
ランジスタの製造工程を説明するための平面図お
よび断面図。第３図は従来および本発明による接
合型電界効果トランジスタのチヤンネル巾と飽和
電流の相関図。第５図、第６図および第８図は本
発明の実施例の製造工程を説明するための断面
図。第４図および第７図は本発明の実施例の製造
工程を説明するための平面図である。ただし、全
ての平面図において金属電極は省略している。
尚、図において、１……ｐ型半導体基板、２…
…ｎ型埋込み領域、３……ｎ型エピタキシヤル
層、４……ｐ型絶縁分離領域、５……ｐ型ソース
領域、６……ｐ型ドレイン領域、７……高濃度ｎ
型ゲート領域、８……ｐ型チヤンネル領域、９…
…ｎ型トツプゲート領域、１０，１１……酸化
膜、１２……金属電極である。
1 and 2 are a plan view and a cross-sectional view for explaining the manufacturing process of a conventional junction field effect transistor. FIG. 3 is a correlation diagram of the channel width and saturation current of the conventional junction field effect transistor and the present invention. FIG. 5, FIG. 6, and FIG. 8 are cross-sectional views for explaining the manufacturing process of an embodiment of the present invention. FIG. 4 and FIG. 7 are plan views for explaining the manufacturing process of the embodiment of the present invention. However, metal electrodes are omitted in all plan views. In the figure, 1... p-type semiconductor substrate, 2...
... n-type buried region, 3 ... n-type epitaxial layer, 4 ... p-type insulation isolation region, 5 ... p-type source region, 6 ... p-type drain region, 7 ... high concentration n
type gate region, 8...p type channel region, 9...
. . . n-type top gate region, 10, 11 . . . oxide film, 12 . . . metal electrode.
Claims (1)
半導体層に、前記一主面上の第１の方向に沿つて
第１の接合深さを有する逆導電型のソース、ドレ
イン領域を相対向させて形成する工程と、 前記ソース、ドレイン領域と離隔してこれを取
り囲むように前記第１の方向に沿つて相対向して
設けられた第１、第２の領域及び、前記第１の方
向と直交する第２の方向に沿つて相対向して設け
られた第３、第４の領域を有する環状の一導電型
の高濃度ゲート領域を形成する工程と、 所定形状のフオトレジストマスクを形成しイオ
ン注入法を用いて、前記ソース、ドレイン領域に
はさまれ、かつ、ソース、ドレイン領域の前記第
１の方向のエツジ部を越えない一導電型半導体層
に前記第１の接合深さよりも浅い、第２の接合深
さを有する逆導電型のチヤネル領域を形成すると
共に、該逆導電型のチヤネル領域の一部に一対の
突出領域を設け、前記高濃度ゲード領域の第３、
第４の領域の側面にそれぞれ終端させる工程と、 前記フオトレジストマスクを用いてイオン注入
法により、前記第２の接合深さよりも浅い第３の
接合深さを有し、前記チヤネル領域と同一形状の
一導電型トツプゲート領域を形成すると共に、 該トツプゲート領域の一部に設けられた一対の
突出領域を、前記高濃度ゲート領域の第３、第４
の領域に接続する工程とを含むことを特徴とする
半導体装置の製造方法。[Scope of Claims] 1. A semiconductor layer of one conductivity type formed on one main surface side of a semiconductor substrate, and a semiconductor layer of an opposite conductivity type having a first junction depth along a first direction on the one main surface. a step of forming source and drain regions facing each other; first and second regions facing each other along the first direction so as to be spaced apart from and surrounding the source and drain regions; and forming a ring-shaped high concentration gate region of one conductivity type having third and fourth regions facing each other along a second direction orthogonal to the first direction; A photoresist mask having a shape is formed and, using an ion implantation method, the semiconductor layer of one conductivity type is sandwiched between the source and drain regions and does not extend beyond the edge portions of the source and drain regions in the first direction. forming a channel region of opposite conductivity type having a second junction depth that is shallower than the first junction depth; and providing a pair of protruding regions in a part of the channel region of opposite conductivity type; The third area,
terminating each side surface of the fourth region, and forming a third junction depth shallower than the second junction depth by ion implantation using the photoresist mask and having the same shape as the channel region. A top gate region of one conductivity type is formed, and a pair of protruding regions provided in a part of the top gate region are formed in third and fourth regions of the high concentration gate region.
1. A method of manufacturing a semiconductor device, the method comprising the step of: connecting to a region of the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8092782A JPS58197885A (en) | 1982-05-14 | 1982-05-14 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8092782A JPS58197885A (en) | 1982-05-14 | 1982-05-14 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58197885A JPS58197885A (en) | 1983-11-17 |
| JPH0366811B2 true JPH0366811B2 (en) | 1991-10-18 |
Family
ID=13732061
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8092782A Granted JPS58197885A (en) | 1982-05-14 | 1982-05-14 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58197885A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3634660B2 (en) | 1999-03-09 | 2005-03-30 | 三洋電機株式会社 | Semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54114983A (en) * | 1978-02-27 | 1979-09-07 | Nec Corp | Semiconductor device |
-
1982
- 1982-05-14 JP JP8092782A patent/JPS58197885A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54114983A (en) * | 1978-02-27 | 1979-09-07 | Nec Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58197885A (en) | 1983-11-17 |
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